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@@ -3829,85 +3829,32 @@ void nand_decode_ext_id(struct nand_chip *chip)
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/* The 4th id byte is the important one */
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extid = id_data[3];
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+ /* Calc pagesize */
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+ mtd->writesize = 1024 << (extid & 0x03);
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+ extid >>= 2;
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+ /* Calc oobsize */
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+ mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
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+ extid >>= 2;
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+ /* Calc blocksize. Blocksize is multiples of 64KiB */
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+ mtd->erasesize = (64 * 1024) << (extid & 0x03);
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+ extid >>= 2;
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+ /* Get buswidth information */
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+ if (extid & 0x1)
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+ chip->options |= NAND_BUSWIDTH_16;
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+
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/*
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- * Field definitions are in the following datasheets:
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- * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
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- * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
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- *
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- * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
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- * ID to decide what to do.
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+ * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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+ * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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+ * follows:
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+ * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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+ * 110b -> 24nm
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+ * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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*/
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- if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
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- !nand_is_slc(chip)) {
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- unsigned int tmp;
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-
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- /* Calc pagesize */
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- mtd->writesize = 2048 << (extid & 0x03);
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- extid >>= 2;
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- /* Calc oobsize */
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- switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
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- case 0:
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- mtd->oobsize = 128;
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- break;
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- case 1:
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- mtd->oobsize = 224;
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- break;
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- case 2:
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- mtd->oobsize = 448;
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- break;
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- case 3:
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- mtd->oobsize = 64;
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- break;
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- case 4:
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- mtd->oobsize = 32;
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- break;
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- case 5:
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- mtd->oobsize = 16;
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- break;
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- default:
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- mtd->oobsize = 640;
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- break;
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- }
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- extid >>= 2;
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- /* Calc blocksize */
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- tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
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- if (tmp < 0x03)
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- mtd->erasesize = (128 * 1024) << tmp;
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- else if (tmp == 0x03)
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- mtd->erasesize = 768 * 1024;
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- else
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- mtd->erasesize = (64 * 1024) << tmp;
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- } else {
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- /* Calc pagesize */
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- mtd->writesize = 1024 << (extid & 0x03);
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- extid >>= 2;
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- /* Calc oobsize */
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- mtd->oobsize = (8 << (extid & 0x01)) *
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- (mtd->writesize >> 9);
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- extid >>= 2;
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- /* Calc blocksize. Blocksize is multiples of 64KiB */
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- mtd->erasesize = (64 * 1024) << (extid & 0x03);
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- extid >>= 2;
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- /* Get buswidth information */
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- if (extid & 0x1)
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- chip->options |= NAND_BUSWIDTH_16;
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-
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- /*
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- * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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- * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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- * follows:
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- * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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- * 110b -> 24nm
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- * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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- */
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- if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
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- nand_is_slc(chip) &&
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- (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
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- !(id_data[4] & 0x80) /* !BENAND */) {
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- mtd->oobsize = 32 * mtd->writesize >> 9;
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- }
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-
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- }
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+ if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
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+ nand_is_slc(chip) &&
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+ (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
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+ !(id_data[4] & 0x80) /* !BENAND */)
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+ mtd->oobsize = 32 * mtd->writesize >> 9;
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}
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EXPORT_SYMBOL_GPL(nand_decode_ext_id);
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@@ -3966,15 +3913,10 @@ static void nand_decode_bbm_options(struct nand_chip *chip)
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* Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
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* AMD/Spansion, and Macronix. All others scan only the first page.
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*/
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- if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX)
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- chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
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- else if ((nand_is_slc(chip) &&
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- (maf_id == NAND_MFR_HYNIX ||
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- maf_id == NAND_MFR_TOSHIBA ||
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- maf_id == NAND_MFR_AMD ||
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- maf_id == NAND_MFR_MACRONIX)) ||
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- (mtd->writesize == 2048 &&
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- maf_id == NAND_MFR_MICRON))
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+ if ((nand_is_slc(chip) &&
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+ (maf_id == NAND_MFR_TOSHIBA || maf_id == NAND_MFR_AMD ||
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+ maf_id == NAND_MFR_MACRONIX)) ||
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+ (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON))
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chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
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}
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