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@@ -263,6 +263,24 @@
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cache-level = <2>;
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};
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+ sdmmc0: sdio-host@a0000000 {
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+ compatible = "atmel,sama5d2-sdhci";
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+ reg = <0xa0000000 0x300>;
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+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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+ clock-names = "hclock", "multclk", "baseclk";
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+ status = "disabled";
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+ };
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+
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+ sdmmc1: sdio-host@b0000000 {
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+ compatible = "atmel,sama5d2-sdhci";
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+ reg = <0xb0000000 0x300>;
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+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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+ clock-names = "hclock", "multclk", "baseclk";
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+ status = "disabled";
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+ };
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+
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -286,7 +304,7 @@
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};
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pmc: pmc@f0014000 {
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- compatible = "atmel,sama5d2-pmc";
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+ compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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@@ -619,6 +637,18 @@
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atmel,clk-output-range = <0 83000000>;
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};
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+ i2s0_clk: i2s0_clk {
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+ #clock-cells = <0>;
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+ reg = <54>;
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+ atmel,clk-output-range = <0 83000000>;
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+ };
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+
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+ i2s1_clk: i2s1_clk {
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+ #clock-cells = <0>;
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+ reg = <55>;
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+ atmel,clk-output-range = <0 83000000>;
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+ };
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+
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classd_clk: classd_clk {
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#clock-cells = <0>;
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reg = <59>;
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@@ -697,6 +727,52 @@
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reg = <53>;
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};
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};
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+
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+ gck {
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+ compatible = "atmel,sama5d2-clk-generated";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupt-parent = <&pmc>;
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+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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+
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+ sdmmc0_gclk: sdmmc0_gclk {
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+ #clock-cells = <0>;
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+ reg = <31>;
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+ };
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+
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+ sdmmc1_gclk: sdmmc1_gclk {
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+ #clock-cells = <0>;
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+ reg = <32>;
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+ };
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+
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+ tcb0_gclk: tcb0_gclk {
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+ #clock-cells = <0>;
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+ reg = <35>;
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+ atmel,clk-output-range = <0 83000000>;
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+ };
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+
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+ tcb1_gclk: tcb1_gclk {
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+ #clock-cells = <0>;
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+ reg = <36>;
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+ atmel,clk-output-range = <0 83000000>;
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+ };
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+
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+ pwm_gclk: pwm_gclk {
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+ #clock-cells = <0>;
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+ reg = <38>;
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+ atmel,clk-output-range = <0 83000000>;
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+ };
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+
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+ i2s0_gclk: i2s0_gclk {
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+ #clock-cells = <0>;
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+ reg = <54>;
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+ };
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+
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+ i2s1_gclk: i2s1_gclk {
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+ #clock-cells = <0>;
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+ reg = <55>;
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+ };
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+ };
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};
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sha@f0028000 {
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@@ -709,7 +785,7 @@
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dma-names = "tx";
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clocks = <&sha_clk>;
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clock-names = "sha_clk";
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- status = "disabled";
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+ status = "okay";
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};
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aes@f002c000 {
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@@ -725,7 +801,7 @@
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dma-names = "tx", "rx";
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clocks = <&aes_clk>;
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clock-names = "aes_clk";
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- status = "disabled";
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+ status = "okay";
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};
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spi0: spi@f8000000 {
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@@ -820,6 +896,32 @@
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status = "disabled";
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};
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+ flx0: flexcom@f8034000 {
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+ compatible = "atmel,sama5d2-flexcom";
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+ reg = <0xf8034000 0x200>;
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+ clocks = <&flx0_clk>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0xf8034000 0x800>;
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+ status = "disabled";
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+ };
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+
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+ flx1: flexcom@f8038000 {
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+ compatible = "atmel,sama5d2-flexcom";
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+ reg = <0xf8038000 0x200>;
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+ clocks = <&flx1_clk>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0xf8038000 0x800>;
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+ status = "disabled";
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+ };
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+
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+ rstc@f8048000 {
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+ compatible = "atmel,sama5d3-rstc";
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+ reg = <0xf8048000 0x10>;
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+ clocks = <&clk32k>;
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+ };
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+
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pit: timer@f8048030 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xf8048030 0x10>;
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@@ -897,6 +999,36 @@
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status = "disabled";
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};
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+ flx2: flexcom@fc010000 {
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+ compatible = "atmel,sama5d2-flexcom";
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+ reg = <0xfc010000 0x200>;
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+ clocks = <&flx2_clk>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0xfc010000 0x800>;
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+ status = "disabled";
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+ };
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+
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+ flx3: flexcom@fc014000 {
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+ compatible = "atmel,sama5d2-flexcom";
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+ reg = <0xfc014000 0x200>;
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+ clocks = <&flx3_clk>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0xfc014000 0x800>;
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+ status = "disabled";
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+ };
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+
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+ flx4: flexcom@fc018000 {
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+ compatible = "atmel,sama5d2-flexcom";
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+ reg = <0xfc018000 0x200>;
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+ clocks = <&flx4_clk>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0xfc018000 0x800>;
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+ status = "disabled";
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+ };
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+
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aic: interrupt-controller@fc020000 {
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#interrupt-cells = <3>;
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compatible = "atmel,sama5d2-aic";
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@@ -921,6 +1053,22 @@
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clocks = <&twi1_clk>;
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status = "disabled";
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};
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+
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+ tdes@fc044000 {
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+ compatible = "atmel,at91sam9g46-tdes";
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+ reg = <0xfc044000 0x100>;
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+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
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+ dmas = <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(28))>,
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+ <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(29))>;
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+ dma-names = "tx", "rx";
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+ clocks = <&tdes_clk>;
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+ clock-names = "tdes_clk";
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+ status = "okay";
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+ };
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};
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};
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};
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