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@@ -583,6 +583,16 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
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return adev->nbio_funcs->get_rev_id(adev);
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}
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+static void soc15_flush_hdp(struct amdgpu_device *adev)
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+{
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+ adev->nbio_funcs->hdp_flush(adev);
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+}
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+
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+static void soc15_invalidate_hdp(struct amdgpu_device *adev)
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+{
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+ WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
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+}
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+
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static const struct amdgpu_asic_funcs soc15_asic_funcs =
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{
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.read_disabled_bios = &soc15_read_disabled_bios,
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@@ -594,6 +604,8 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
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.set_uvd_clocks = &soc15_set_uvd_clocks,
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.set_vce_clocks = &soc15_set_vce_clocks,
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.get_config_memsize = &soc15_get_config_memsize,
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+ .flush_hdp = &soc15_flush_hdp,
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+ .invalidate_hdp = &soc15_invalidate_hdp,
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};
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static int soc15_common_early_init(void *handle)
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