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@@ -856,6 +856,18 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
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>> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
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}
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+static void vi_flush_hdp(struct amdgpu_device *adev)
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+{
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+ WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
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+ RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
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+}
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+
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+static void vi_invalidate_hdp(struct amdgpu_device *adev)
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+{
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+ WREG32(mmHDP_DEBUG0, 1);
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+ RREG32(mmHDP_DEBUG0);
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+}
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+
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static const struct amdgpu_asic_funcs vi_asic_funcs =
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{
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.read_disabled_bios = &vi_read_disabled_bios,
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@@ -867,6 +879,8 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
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.set_uvd_clocks = &vi_set_uvd_clocks,
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.set_vce_clocks = &vi_set_vce_clocks,
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.get_config_memsize = &vi_get_config_memsize,
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+ .flush_hdp = &vi_flush_hdp,
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+ .invalidate_hdp = &vi_invalidate_hdp,
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};
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#define CZ_REV_BRISTOL(rev) \
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