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@@ -0,0 +1,487 @@
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+/*
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+ * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
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+ *
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+ * The code contained herein is licensed under the GNU General Public
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+ * License. You may obtain a copy of the GNU General Public License
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+ * Version 2 or later at the following locations:
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+ *
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+ * http://www.opensource.org/licenses/gpl-license.html
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+ * http://www.gnu.org/copyleft/gpl.html
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_domain.h>
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+#include <linux/regmap.h>
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+#include <linux/regulator/consumer.h>
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+
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+#define GPC_CNTR 0x000
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+
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+#define GPC_PGC_PDN_OFFS 0x0
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+#define GPC_PGC_PUPSCR_OFFS 0x4
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+#define GPC_PGC_PDNSCR_OFFS 0x8
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+#define GPC_PGC_SW2ISO_SHIFT 0x8
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+#define GPC_PGC_SW_SHIFT 0x0
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+
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+#define GPC_PGC_GPU_PDN 0x260
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+#define GPC_PGC_GPU_PUPSCR 0x264
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+#define GPC_PGC_GPU_PDNSCR 0x268
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+
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+#define GPU_VPU_PUP_REQ BIT(1)
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+#define GPU_VPU_PDN_REQ BIT(0)
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+
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+#define GPC_CLK_MAX 6
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+
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+struct imx_pm_domain {
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+ struct generic_pm_domain base;
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+ struct regmap *regmap;
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+ struct regulator *supply;
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+ struct clk *clk[GPC_CLK_MAX];
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+ int num_clks;
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+ unsigned int reg_offs;
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+ signed char cntr_pdn_bit;
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+ unsigned int ipg_rate_mhz;
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+};
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+
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+static inline struct imx_pm_domain *
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+to_imx_pm_domain(struct generic_pm_domain *genpd)
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+{
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+ return container_of(genpd, struct imx_pm_domain, base);
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+}
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+
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+static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
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+{
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+ struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
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+ int iso, iso2sw;
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+ u32 val;
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+
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+ /* Read ISO and ISO2SW power down delays */
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+ regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
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+ iso = val & 0x3f;
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+ iso2sw = (val >> 8) & 0x3f;
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+
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+ /* Gate off domain when powered down */
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+ regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_PDN_OFFS,
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+ 0x1, 0x1);
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+
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+ /* Request GPC to power down domain */
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+ val = BIT(pd->cntr_pdn_bit);
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+ regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
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+
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+ /* Wait ISO + ISO2SW IPG clock cycles */
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+ udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
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+
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+ if (pd->supply)
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+ regulator_disable(pd->supply);
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+
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+ return 0;
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+}
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+
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+static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
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+{
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+ struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
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+ int i, ret, sw, sw2iso;
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+ u32 val;
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+
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+ if (pd->supply) {
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+ ret = regulator_enable(pd->supply);
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+ if (ret) {
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+ pr_err("%s: failed to enable regulator: %d\n",
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+ __func__, ret);
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+ return ret;
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+ }
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+ }
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+
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+ /* Enable reset clocks for all devices in the domain */
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+ for (i = 0; i < pd->num_clks; i++)
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+ clk_prepare_enable(pd->clk[i]);
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+
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+ /* Gate off domain when powered down */
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+ regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_PDN_OFFS,
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+ 0x1, 0x1);
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+
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+ /* Read ISO and ISO2SW power down delays */
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+ regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
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+ sw = val & 0x3f;
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+ sw2iso = (val >> 8) & 0x3f;
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+
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+ /* Request GPC to power up domain */
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+ val = BIT(pd->cntr_pdn_bit + 1);
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+ regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
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+
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+ /* Wait ISO + ISO2SW IPG clock cycles */
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+ udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
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+
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+ /* Disable reset clocks for all devices in the domain */
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+ for (i = 0; i < pd->num_clks; i++)
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+ clk_disable_unprepare(pd->clk[i]);
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+
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+ return 0;
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+}
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+
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+static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
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+{
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+ int i, ret;
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+
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+ for (i = 0; ; i++) {
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+ struct clk *clk = of_clk_get(dev->of_node, i);
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+ if (IS_ERR(clk))
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+ break;
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+ if (i >= GPC_CLK_MAX) {
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+ dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
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+ ret = -EINVAL;
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+ goto clk_err;
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+ }
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+ domain->clk[i] = clk;
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+ }
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+ domain->num_clks = i;
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+
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+ return 0;
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+
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+clk_err:
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+ for (; i >= 0; i--)
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+ clk_put(domain->clk[i]);
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+
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+ return ret;
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+}
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+
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+static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
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+{
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+ int i;
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+
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+ for (i = domain->num_clks - 1; i >= 0; i--)
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+ clk_put(domain->clk[i]);
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+}
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+
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+static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
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+{
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+ /* try to get the domain supply regulator */
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+ domain->supply = devm_regulator_get_optional(dev, "power");
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+ if (IS_ERR(domain->supply)) {
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+ if (PTR_ERR(domain->supply) == -ENODEV)
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+ domain->supply = NULL;
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+ else
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+ return PTR_ERR(domain->supply);
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+ }
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+
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+ /* try to get all clocks needed for reset propagation */
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+ return imx_pgc_get_clocks(dev, domain);
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+}
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+
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+static int imx_pgc_power_domain_probe(struct platform_device *pdev)
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+{
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+ struct imx_pm_domain *domain = pdev->dev.platform_data;
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+ struct device *dev = &pdev->dev;
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+ int ret;
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+
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+ /* if this PD is associated with a DT node try to parse it */
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+ if (dev->of_node) {
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+ ret = imx_pgc_parse_dt(dev, domain);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ /* initially power on the domain */
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+ if (domain->base.power_on)
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+ domain->base.power_on(&domain->base);
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+
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+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
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+ pm_genpd_init(&domain->base, NULL, false);
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+ ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
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+ if (ret)
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+ goto genpd_err;
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+ }
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+
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+ device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);
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+
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+ return 0;
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+
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+genpd_err:
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+ pm_genpd_remove(&domain->base);
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+ imx_pgc_put_clocks(domain);
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+
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+ return ret;
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+}
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+
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+static int imx_pgc_power_domain_remove(struct platform_device *pdev)
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+{
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+ struct imx_pm_domain *domain = pdev->dev.platform_data;
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+
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+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
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+ of_genpd_del_provider(pdev->dev.of_node);
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+ pm_genpd_remove(&domain->base);
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+ imx_pgc_put_clocks(domain);
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct platform_device_id imx_pgc_power_domain_id[] = {
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+ { "imx-pgc-power-domain"},
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+ { },
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+};
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+
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+static struct platform_driver imx_pgc_power_domain_driver = {
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+ .driver = {
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+ .name = "imx-pgc-pd",
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+ },
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+ .probe = imx_pgc_power_domain_probe,
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+ .remove = imx_pgc_power_domain_remove,
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+ .id_table = imx_pgc_power_domain_id,
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+};
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+builtin_platform_driver(imx_pgc_power_domain_driver)
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+
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+static struct genpd_power_state imx6_pm_domain_pu_state = {
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+ .power_off_latency_ns = 25000,
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+ .power_on_latency_ns = 2000000,
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+};
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+
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+static struct imx_pm_domain imx_gpc_domains[] = {
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+ {
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+ .base = {
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+ .name = "ARM",
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+ },
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+ }, {
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+ .base = {
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+ .name = "PU",
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+ .power_off = imx6_pm_domain_power_off,
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+ .power_on = imx6_pm_domain_power_on,
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+ .states = &imx6_pm_domain_pu_state,
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+ .state_count = 1,
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+ },
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+ .reg_offs = 0x260,
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+ .cntr_pdn_bit = 0,
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+ }, {
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+ .base = {
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+ .name = "DISPLAY",
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+ .power_off = imx6_pm_domain_power_off,
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+ .power_on = imx6_pm_domain_power_on,
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+ },
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+ .reg_offs = 0x240,
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+ .cntr_pdn_bit = 4,
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+ }
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+};
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+
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+struct imx_gpc_dt_data {
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+ int num_domains;
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+};
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+
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+static const struct imx_gpc_dt_data imx6q_dt_data = {
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+ .num_domains = 2,
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+};
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+
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+static const struct imx_gpc_dt_data imx6sl_dt_data = {
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+ .num_domains = 3,
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+};
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+
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+static const struct of_device_id imx_gpc_dt_ids[] = {
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+ { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
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+ { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
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+ { }
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+};
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+
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+static bool imx_gpc_readable_reg(struct device *dev, unsigned int reg)
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+{
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+ return (reg % 4 == 0) && (reg <= 0x2ac);
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+}
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+
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+static bool imx_gpc_volatile_reg(struct device *dev, unsigned int reg)
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+{
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+ if (reg == GPC_CNTR)
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+ return true;
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+
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+ return false;
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+}
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+
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+static const struct regmap_config imx_gpc_regmap_config = {
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+ .cache_type = REGCACHE_FLAT,
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+ .reg_bits = 32,
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+ .val_bits = 32,
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+ .reg_stride = 4,
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+
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+ .readable_reg = imx_gpc_readable_reg,
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+ .volatile_reg = imx_gpc_volatile_reg,
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+
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+ .max_register = 0x2ac,
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+};
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+
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+static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
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+ &imx_gpc_domains[0].base,
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+ &imx_gpc_domains[1].base,
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+};
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+
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+static struct genpd_onecell_data imx_gpc_onecell_data = {
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+ .domains = imx_gpc_onecell_domains,
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+ .num_domains = 2,
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+};
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+
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+static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap)
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+{
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+ struct imx_pm_domain *domain;
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+ int i, ret;
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+
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+ for (i = 0; i < 2; i++) {
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+ domain = &imx_gpc_domains[i];
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+ domain->regmap = regmap;
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+ domain->ipg_rate_mhz = 66;
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+
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+ if (i == 1) {
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+ domain->supply = devm_regulator_get(dev, "pu");
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+ if (IS_ERR(domain->supply))
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+ return PTR_ERR(domain->supply);;
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+
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+ ret = imx_pgc_get_clocks(dev, domain);
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+ if (ret)
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+ goto clk_err;
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+
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+ domain->base.power_on(&domain->base);
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+ }
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+ }
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+
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+ for (i = 0; i < 2; i++)
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+ pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
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+
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+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
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+ ret = of_genpd_add_provider_onecell(dev->of_node,
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+ &imx_gpc_onecell_data);
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+ if (ret)
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+ goto genpd_err;
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+ }
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+
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+ return 0;
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+
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+genpd_err:
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+ for (i = 0; i < 2; i++)
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+ pm_genpd_remove(&imx_gpc_domains[i].base);
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+ imx_pgc_put_clocks(&imx_gpc_domains[1]);
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+clk_err:
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+ return ret;
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+}
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+
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+static int imx_gpc_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *of_id =
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+ of_match_device(imx_gpc_dt_ids, &pdev->dev);
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+ const struct imx_gpc_dt_data *of_id_data = of_id->data;
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+ struct device_node *pgc_node;
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+ struct regmap *regmap;
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+ struct resource *res;
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+ void __iomem *base;
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+ int ret;
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+
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+ pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
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+
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+ /* bail out if DT too old and doesn't provide the necessary info */
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+ if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
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+ !pgc_node)
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+ return 0;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
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+ &imx_gpc_regmap_config);
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+ if (IS_ERR(regmap)) {
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+ ret = PTR_ERR(regmap);
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+ dev_err(&pdev->dev, "failed to init regmap: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ if (!pgc_node) {
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+ /* old DT layout is only supported for mx6q aka 2 domains */
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+ if (of_id_data->num_domains != 2) {
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|
+ dev_err(&pdev->dev, "could not find pgc DT node\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = imx_gpc_old_dt_init(&pdev->dev, regmap);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ } else {
|
|
|
+ struct imx_pm_domain *domain;
|
|
|
+ struct platform_device *pd_pdev;
|
|
|
+ struct device_node *np;
|
|
|
+ struct clk *ipg_clk;
|
|
|
+ unsigned int ipg_rate_mhz;
|
|
|
+ int domain_index;
|
|
|
+
|
|
|
+ ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
|
|
+ if (IS_ERR(ipg_clk))
|
|
|
+ return PTR_ERR(ipg_clk);
|
|
|
+ ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
|
|
|
+
|
|
|
+ for_each_child_of_node(pgc_node, np) {
|
|
|
+ ret = of_property_read_u32(np, "reg", &domain_index);
|
|
|
+ if (ret) {
|
|
|
+ of_node_put(np);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ if (domain_index >= ARRAY_SIZE(imx_gpc_domains))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ domain = &imx_gpc_domains[domain_index];
|
|
|
+ domain->regmap = regmap;
|
|
|
+ domain->ipg_rate_mhz = ipg_rate_mhz;
|
|
|
+
|
|
|
+ pd_pdev = platform_device_alloc("imx-pgc-power-domain",
|
|
|
+ domain_index);
|
|
|
+ if (!pd_pdev) {
|
|
|
+ of_node_put(np);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ pd_pdev->dev.platform_data = domain;
|
|
|
+ pd_pdev->dev.parent = &pdev->dev;
|
|
|
+ pd_pdev->dev.of_node = np;
|
|
|
+
|
|
|
+ ret = platform_device_add(pd_pdev);
|
|
|
+ if (ret) {
|
|
|
+ platform_device_put(pd_pdev);
|
|
|
+ of_node_put(np);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int imx_gpc_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * If the old DT binding is used the toplevel driver needs to
|
|
|
+ * de-register the power domains
|
|
|
+ */
|
|
|
+ if (!of_get_child_by_name(pdev->dev.of_node, "pgc")) {
|
|
|
+ of_genpd_del_provider(pdev->dev.of_node);
|
|
|
+
|
|
|
+ ret = pm_genpd_remove(&imx_gpc_domains[1].base);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ imx_pgc_put_clocks(&imx_gpc_domains[1]);
|
|
|
+
|
|
|
+ ret = pm_genpd_remove(&imx_gpc_domains[0].base);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct platform_driver imx_gpc_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "imx-gpc",
|
|
|
+ .of_match_table = imx_gpc_dt_ids,
|
|
|
+ },
|
|
|
+ .probe = imx_gpc_probe,
|
|
|
+ .remove = imx_gpc_remove,
|
|
|
+};
|
|
|
+builtin_platform_driver(imx_gpc_driver)
|
Lucas Stach