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@@ -43,18 +43,6 @@ static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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return tmp;
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}
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-static u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
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- uint32_t idx)
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-{
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- return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
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-}
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-
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-static void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
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- uint32_t idx, uint32_t val)
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-{
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- WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
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-}
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-
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static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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@@ -284,8 +272,6 @@ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
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.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
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.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
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.get_rev_id = nbio_v6_1_get_rev_id,
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- .get_atombios_scratch_regs = nbio_v6_1_get_atombios_scratch_regs,
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- .set_atombios_scratch_regs = nbio_v6_1_set_atombios_scratch_regs,
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.mc_access_enable = nbio_v6_1_mc_access_enable,
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.hdp_flush = nbio_v6_1_hdp_flush,
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.get_memsize = nbio_v6_1_get_memsize,
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