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@@ -125,18 +125,6 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
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MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
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MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
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-MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
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-
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MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
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@@ -149,6 +137,18 @@ MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
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+MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
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+
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MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
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@@ -161,6 +161,13 @@ MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_me.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
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+MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
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+
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static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
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{
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{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
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@@ -918,17 +925,20 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
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case CHIP_FIJI:
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chip_name = "fiji";
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break;
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- case CHIP_POLARIS11:
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- chip_name = "polaris11";
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+ case CHIP_STONEY:
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+ chip_name = "stoney";
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break;
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case CHIP_POLARIS10:
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chip_name = "polaris10";
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break;
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+ case CHIP_POLARIS11:
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+ chip_name = "polaris11";
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+ break;
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case CHIP_POLARIS12:
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chip_name = "polaris12";
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break;
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- case CHIP_STONEY:
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- chip_name = "stoney";
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+ case CHIP_VEGAM:
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+ chip_name = "vegam";
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break;
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default:
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BUG();
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