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@@ -4808,7 +4808,7 @@ static void gen9_enable_rps(struct drm_device *dev)
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* Up/Down EI & threshold registers, as well as the RP_CONTROL,
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* RP_INTERRUPT_LIMITS & RPNSWREQ registers */
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dev_priv->rps.power = HIGH_POWER; /* force a reset */
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- gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
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+ gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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@@ -5595,10 +5595,10 @@ static void cherryview_enable_rps(struct drm_device *dev)
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dev_priv->rps.cur_freq);
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DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
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- intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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- dev_priv->rps.efficient_freq);
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+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
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+ dev_priv->rps.idle_freq);
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- valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
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+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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@@ -5684,10 +5684,10 @@ static void valleyview_enable_rps(struct drm_device *dev)
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dev_priv->rps.cur_freq);
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DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
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- intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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- dev_priv->rps.efficient_freq);
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+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
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+ dev_priv->rps.idle_freq);
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- valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
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+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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