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drm/i915: Set GPU freq to idle_freq initially

Currently we set the initial GPU frequency to min_freq_softlimit
on gen9, and to efficient_freq on VLV/CHV. On all the other platforms
we set it to idle_freq. Let's use idle_freq across the board to make
sure we don't waste power. This is especially relevant for VLV since
Vnn won't drop to minimum unless the GPU is at the minimum frequency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457120584-26080-3-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Ville Syrjälä 9 年之前
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當前提交
5fd9f52384
共有 1 個文件被更改,包括 7 次插入7 次删除
  1. 7 7
      drivers/gpu/drm/i915/intel_pm.c

+ 7 - 7
drivers/gpu/drm/i915/intel_pm.c

@@ -4808,7 +4808,7 @@ static void gen9_enable_rps(struct drm_device *dev)
 	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
 	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
 	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
 	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
 	dev_priv->rps.power = HIGH_POWER; /* force a reset */
 	dev_priv->rps.power = HIGH_POWER; /* force a reset */
-	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
+	gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
 
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 }
@@ -5595,10 +5595,10 @@ static void cherryview_enable_rps(struct drm_device *dev)
 			 dev_priv->rps.cur_freq);
 			 dev_priv->rps.cur_freq);
 
 
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
-			 dev_priv->rps.efficient_freq);
+			 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
+			 dev_priv->rps.idle_freq);
 
 
-	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
 
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 }
@@ -5684,10 +5684,10 @@ static void valleyview_enable_rps(struct drm_device *dev)
 			 dev_priv->rps.cur_freq);
 			 dev_priv->rps.cur_freq);
 
 
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
-			 dev_priv->rps.efficient_freq);
+			 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
+			 dev_priv->rps.idle_freq);
 
 
-	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
 
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 }