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@@ -1,5 +1,5 @@
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/*
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- * AXS101 Software Development Platform
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+ * AXS101/AXS103 Software Development Platform
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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@@ -15,8 +15,10 @@
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*/
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#include <linux/of_platform.h>
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-#include <asm/mach_desc.h>
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+#include <asm/clk.h>
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#include <asm/io.h>
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+#include <asm/mach_desc.h>
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+#include <asm/mcip.h>
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#define AXS_MB_CGU 0xE0010000
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#define AXS_MB_CREG 0xE0011000
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@@ -29,14 +31,6 @@
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#define AXC001_CREG 0xF0001000
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#define AXC001_GPIO_INTC 0xF0003000
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-#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
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-#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
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-#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
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-#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
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-
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-#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
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-#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
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-
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static void __init axs10x_enable_gpio_intc_wire(void)
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{
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/*
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@@ -83,6 +77,22 @@ static void __init axs10x_enable_gpio_intc_wire(void)
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iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
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}
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+static inline void __init
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+write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
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+{
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+ unsigned int loops = 128 * 1024, ctr;
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+
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+ iowrite32(value, reg);
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+
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+ ctr = loops;
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+ while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
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+ cpu_relax();
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+
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+ ctr = loops;
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+ while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
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+ cpu_relax();
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+}
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+
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static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
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{
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union ver {
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@@ -118,6 +128,16 @@ static void __init axs10x_early_init(void)
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axs10x_print_board_ver(CREG_MB_VER, mb);
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}
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+#ifdef CONFIG_AXS101
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+
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+#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
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+#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
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+#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
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+#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
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+
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+#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
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+#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
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+
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/*
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* Set up System Memory Map for ARC cpu / peripherals controllers
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*
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@@ -287,6 +307,145 @@ static void __init axs101_early_init(void)
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axs10x_early_init();
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}
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+#endif /* CONFIG_AXS101 */
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+
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+#ifdef CONFIG_AXS103
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+
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+#define AXC003_CGU 0xF0000000
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+#define AXC003_CREG 0xF0001000
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+#define AXC003_MST_AXI_TUNNEL 0
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+#define AXC003_MST_HS38 1
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+
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+#define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
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+#define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480)
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+#define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494)
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+
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+
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+union pll_reg {
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+ struct {
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+#ifdef CONFIG_CPU_BIG_ENDIAN
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+ unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
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+#else
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+ unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
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+#endif
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+ };
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+ unsigned int val;
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+};
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+
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+static unsigned int __init axs103_get_freq(void)
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+{
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+ union pll_reg idiv, fbdiv, odiv;
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+ unsigned int f = 33333333;
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+
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+ idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
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+ fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
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+ odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
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+
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+ if (idiv.bypass != 1)
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+ f = f / (idiv.low + idiv.high);
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+
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+ if (fbdiv.bypass != 1)
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+ f = f * (fbdiv.low + fbdiv.high);
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+
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+ if (odiv.bypass != 1)
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+ f = f / (odiv.low + odiv.high);
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+
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+ f = (f + 500000) / 1000000; /* Rounding */
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+ return f;
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+}
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+
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+static inline unsigned int __init encode_div(unsigned int id, int upd)
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+{
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+ union pll_reg div;
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+
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+ div.val = 0;
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+
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+ div.noupd = !upd;
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+ div.bypass = id == 1 ? 1 : 0;
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+ div.edge = (id%2 == 0) ? 0 : 1; /* 0 = rising */
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+ div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
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+ div.high = id >> 1;
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+
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+ return div.val;
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+}
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+
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+noinline static void __init
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+axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
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+{
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+ write_cgu_reg(encode_div(id, 0),
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+ (void __iomem *)AXC003_CGU + 0x80 + 0,
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+ (void __iomem *)AXC003_CGU + 0x110);
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+
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+ write_cgu_reg(encode_div(fd, 0),
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+ (void __iomem *)AXC003_CGU + 0x80 + 4,
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+ (void __iomem *)AXC003_CGU + 0x110);
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+
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+ write_cgu_reg(encode_div(od, 1),
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+ (void __iomem *)AXC003_CGU + 0x80 + 8,
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+ (void __iomem *)AXC003_CGU + 0x110);
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+}
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+
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+static void __init axs103_early_init(void)
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+{
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+ switch (arc_get_core_freq()/1000000) {
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+ case 33:
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+ axs103_set_freq(1, 1, 1);
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+ break;
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+ case 50:
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+ axs103_set_freq(1, 30, 20);
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+ break;
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+ case 75:
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+ axs103_set_freq(2, 45, 10);
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+ break;
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+ case 90:
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+ axs103_set_freq(2, 54, 10);
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+ break;
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+ case 100:
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+ axs103_set_freq(1, 30, 10);
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+ break;
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+ case 125:
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+ axs103_set_freq(2, 45, 6);
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+ break;
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+ default:
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+ /*
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+ * In this case, core_frequency derived from
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+ * DT "clock-frequency" might not match with board value.
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+ * Hence update it to match the board value.
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+ */
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+ arc_set_core_freq(axs103_get_freq() * 1000000);
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+ break;
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+ }
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+
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+ pr_info("Freq is %dMHz\n", axs103_get_freq());
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+
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+ /* Memory maps already config in pre-bootloader */
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+
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+ /* set GPIO mux to UART */
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+ iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
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+
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+ iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
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+ (void __iomem *) CREG_CPU_TUN_IO_CTRL);
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+
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+ /* Set up the AXS_MB interrupt system.*/
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+ iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
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+ + (AXC003_MST_HS38 << 2)));
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+
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+ /* connect ICTL - Main Board with GPIO line */
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+ iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
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+
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+ axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
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+
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+ axs10x_early_init();
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+
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+#ifdef CONFIG_ARC_MCIP
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+ /* No Hardware init, but filling the smp ops callbacks */
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+ mcip_init_early_smp();
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+#endif
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+}
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+#endif
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+
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+#ifdef CONFIG_AXS101
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+
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static const char *axs101_compat[] __initconst = {
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"snps,axs101",
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NULL,
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@@ -296,3 +455,22 @@ MACHINE_START(AXS101, "axs101")
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.dt_compat = axs101_compat,
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.init_early = axs101_early_init,
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MACHINE_END
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+
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+#endif /* CONFIG_AXS101 */
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+
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+#ifdef CONFIG_AXS103
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+
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+static const char *axs103_compat[] __initconst = {
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+ "snps,axs103",
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+ NULL,
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+};
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+
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+MACHINE_START(AXS103, "axs103")
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+ .dt_compat = axs103_compat,
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+ .init_early = axs103_early_init,
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+#ifdef CONFIG_ARC_MCIP
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+ .init_smp = mcip_init_smp,
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+#endif
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+MACHINE_END
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+
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+#endif /* CONFIG_AXS103 */
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Vineet Gupta