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@@ -69,6 +69,27 @@
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};
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};
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+ /*
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+ * This INTC is actually connected to DW APB GPIO
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+ * which acts as a wire between MB INTC and CPU INTC.
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+ * GPIO INTC is configured in platform init code
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+ * and here we mimic direct connection from MB INTC to
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+ * CPU INTC, thus we set "interrupts = <7>" instead of
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+ * "interrupts = <12>"
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+ *
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+ * This intc actually resides on MB, but we move it here to
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+ * avoid duplicating the MB dtsi file given that IRQ from
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+ * this intc to cpu intc are different for axs101 and axs103
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+ */
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+ mb_intc: dw-apb-ictl@0xe0012000 {
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+ #interrupt-cells = <1>;
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+ compatible = "snps,dw-apb-ictl";
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+ reg = < 0xe0012000 0x200 >;
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+ interrupt-controller;
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+ interrupt-parent = <&cpu_intc>;
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+ interrupts = < 7 >;
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+ };
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+
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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