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@@ -269,6 +269,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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return 0;
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}
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+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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+{
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+ /* power up core phy and enable ref clock */
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+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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+ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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+ /*
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+ * the async reset input need ref clock to sync internally,
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+ * when the ref clock comes after reset, internal synced
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+ * reset time is too short, cannot meet the requirement.
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+ * add one ~10us delay here.
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+ */
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+ udelay(10);
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+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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+ return 0;
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+}
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+
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static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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@@ -292,18 +309,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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goto err_pcie;
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}
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- /* power up core phy and enable ref clock */
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- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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- /*
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- * the async reset input need ref clock to sync internally,
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- * when the ref clock comes after reset, internal synced
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- * reset time is too short, cannot meet the requirement.
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- * add one ~10us delay here.
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- */
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- udelay(10);
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- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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+ ret = imx6_pcie_enable_ref_clk(imx6_pcie);
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+ if (ret) {
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+ dev_err(pp->dev, "unable to enable pcie ref clock\n");
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+ goto err_ref_clk;
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+ }
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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@@ -316,6 +326,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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}
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return 0;
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+err_ref_clk:
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+ clk_disable_unprepare(imx6_pcie->pcie);
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err_pcie:
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clk_disable_unprepare(imx6_pcie->pcie_bus);
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err_pcie_bus:
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