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@@ -148,7 +148,7 @@ static struct pistachio_clocksource pcs_gpt = {
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},
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},
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};
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};
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-static void __init pistachio_clksrc_of_init(struct device_node *node)
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+static int __init pistachio_clksrc_of_init(struct device_node *node)
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{
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{
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struct clk *sys_clk, *fast_clk;
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struct clk *sys_clk, *fast_clk;
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struct regmap *periph_regs;
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struct regmap *periph_regs;
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@@ -158,45 +158,45 @@ static void __init pistachio_clksrc_of_init(struct device_node *node)
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pcs_gpt.base = of_iomap(node, 0);
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pcs_gpt.base = of_iomap(node, 0);
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if (!pcs_gpt.base) {
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if (!pcs_gpt.base) {
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pr_err("cannot iomap\n");
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pr_err("cannot iomap\n");
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- return;
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+ return -ENXIO;
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}
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}
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periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
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periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
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if (IS_ERR(periph_regs)) {
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if (IS_ERR(periph_regs)) {
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pr_err("cannot get peripheral regmap (%ld)\n",
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pr_err("cannot get peripheral regmap (%ld)\n",
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PTR_ERR(periph_regs));
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PTR_ERR(periph_regs));
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- return;
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+ return PTR_ERR(periph_regs);
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}
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}
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/* Switch to using the fast counter clock */
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/* Switch to using the fast counter clock */
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ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
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ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
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0xf, 0x0);
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0xf, 0x0);
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if (ret)
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if (ret)
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- return;
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+ return ret;
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sys_clk = of_clk_get_by_name(node, "sys");
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sys_clk = of_clk_get_by_name(node, "sys");
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if (IS_ERR(sys_clk)) {
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if (IS_ERR(sys_clk)) {
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pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
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pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
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- return;
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+ return PTR_ERR(sys_clk);
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}
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}
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fast_clk = of_clk_get_by_name(node, "fast");
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fast_clk = of_clk_get_by_name(node, "fast");
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if (IS_ERR(fast_clk)) {
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if (IS_ERR(fast_clk)) {
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pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
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pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
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- return;
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+ return PTR_ERR(fast_clk);
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}
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}
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ret = clk_prepare_enable(sys_clk);
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ret = clk_prepare_enable(sys_clk);
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if (ret < 0) {
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if (ret < 0) {
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pr_err("failed to enable clock (%d)\n", ret);
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pr_err("failed to enable clock (%d)\n", ret);
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- return;
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+ return ret;
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}
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}
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ret = clk_prepare_enable(fast_clk);
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ret = clk_prepare_enable(fast_clk);
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if (ret < 0) {
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if (ret < 0) {
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pr_err("failed to enable clock (%d)\n", ret);
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pr_err("failed to enable clock (%d)\n", ret);
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clk_disable_unprepare(sys_clk);
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clk_disable_unprepare(sys_clk);
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- return;
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+ return ret;
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}
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}
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rate = clk_get_rate(fast_clk);
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rate = clk_get_rate(fast_clk);
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@@ -212,7 +212,7 @@ static void __init pistachio_clksrc_of_init(struct device_node *node)
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raw_spin_lock_init(&pcs_gpt.lock);
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raw_spin_lock_init(&pcs_gpt.lock);
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sched_clock_register(pistachio_read_sched_clock, 32, rate);
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sched_clock_register(pistachio_read_sched_clock, 32, rate);
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- clocksource_register_hz(&pcs_gpt.cs, rate);
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+ return clocksource_register_hz(&pcs_gpt.cs, rate);
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}
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}
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-CLOCKSOURCE_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
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+CLOCKSOURCE_OF_DECLARE_RET(pistachio_gptimer, "img,pistachio-gptimer",
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pistachio_clksrc_of_init);
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pistachio_clksrc_of_init);
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