|
@@ -104,25 +104,36 @@ static struct irqaction orion_clkevt_irq = {
|
|
|
.handler = orion_clkevt_irq_handler,
|
|
|
};
|
|
|
|
|
|
-static void __init orion_timer_init(struct device_node *np)
|
|
|
+static int __init orion_timer_init(struct device_node *np)
|
|
|
{
|
|
|
struct clk *clk;
|
|
|
- int irq;
|
|
|
+ int irq, ret;
|
|
|
|
|
|
/* timer registers are shared with watchdog timer */
|
|
|
timer_base = of_iomap(np, 0);
|
|
|
- if (!timer_base)
|
|
|
- panic("%s: unable to map resource\n", np->name);
|
|
|
+ if (!timer_base) {
|
|
|
+ pr_err("%s: unable to map resource\n", np->name);
|
|
|
+ return -ENXIO;
|
|
|
+ }
|
|
|
|
|
|
clk = of_clk_get(np, 0);
|
|
|
- if (IS_ERR(clk))
|
|
|
- panic("%s: unable to get clk\n", np->name);
|
|
|
- clk_prepare_enable(clk);
|
|
|
+ if (IS_ERR(clk)) {
|
|
|
+ pr_err("%s: unable to get clk\n", np->name);
|
|
|
+ return PTR_ERR(clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = clk_prepare_enable(clk);
|
|
|
+ if (ret) {
|
|
|
+ pr_err("Failed to prepare clock");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
/* we are only interested in timer1 irq */
|
|
|
irq = irq_of_parse_and_map(np, 1);
|
|
|
- if (irq <= 0)
|
|
|
- panic("%s: unable to parse timer1 irq\n", np->name);
|
|
|
+ if (irq <= 0) {
|
|
|
+ pr_err("%s: unable to parse timer1 irq\n", np->name);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
|
|
|
/* setup timer0 as free-running clocksource */
|
|
|
writel(~0, timer_base + TIMER0_VAL);
|
|
@@ -130,19 +141,30 @@ static void __init orion_timer_init(struct device_node *np)
|
|
|
atomic_io_modify(timer_base + TIMER_CTRL,
|
|
|
TIMER0_RELOAD_EN | TIMER0_EN,
|
|
|
TIMER0_RELOAD_EN | TIMER0_EN);
|
|
|
- clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
|
|
|
- clk_get_rate(clk), 300, 32,
|
|
|
- clocksource_mmio_readl_down);
|
|
|
+
|
|
|
+ ret = clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
|
|
|
+ clk_get_rate(clk), 300, 32,
|
|
|
+ clocksource_mmio_readl_down);
|
|
|
+ if (ret) {
|
|
|
+ pr_err("Failed to initialize mmio timer");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk));
|
|
|
|
|
|
/* setup timer1 as clockevent timer */
|
|
|
- if (setup_irq(irq, &orion_clkevt_irq))
|
|
|
- panic("%s: unable to setup irq\n", np->name);
|
|
|
+ ret = setup_irq(irq, &orion_clkevt_irq);
|
|
|
+ if (ret) {
|
|
|
+ pr_err("%s: unable to setup irq\n", np->name);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ;
|
|
|
orion_clkevt.cpumask = cpumask_of(0);
|
|
|
orion_clkevt.irq = irq;
|
|
|
clockevents_config_and_register(&orion_clkevt, clk_get_rate(clk),
|
|
|
ORION_ONESHOT_MIN, ORION_ONESHOT_MAX);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
-CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);
|
|
|
+CLOCKSOURCE_OF_DECLARE_RET(orion_timer, "marvell,orion-timer", orion_timer_init);
|