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@@ -1808,43 +1808,6 @@ int cxl_slot_is_switched(struct pci_dev *dev)
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return (depth > CXL_MAX_PCIEX_PARENT);
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}
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-bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
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-{
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- if (!cpu_has_feature(CPU_FTR_HVMODE))
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- return false;
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-
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- if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
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- /*
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- * CAPP DMA mode is technically supported on regular P8, but
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- * will EEH if the card attempts to access memory < 4GB, which
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- * we cannot realistically avoid. We might be able to work
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- * around the issue, but until then return unsupported:
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- */
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- return false;
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- }
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-
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- if (cxl_slot_is_switched(dev))
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- return false;
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-
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- /*
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- * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
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- * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
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- * served basis, which is racy to check from here. If we need to
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- * support this in future we might need to consider having this
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- * function effectively reserve it ahead of time.
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- *
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- * Currently, the only user of this API is the Mellanox CX4, which is
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- * only supported on P8NVL due to the above mentioned limitation of
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- * CAPP DMA mode and therefore does not need to worry about this. If the
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- * issue with CAPP DMA mode is later worked around on P8 we might need
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- * to revisit this.
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- */
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-
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- return true;
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-}
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-EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
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-
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-
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static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct cxl *adapter;
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