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@@ -32,6 +32,11 @@
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/* Static data */
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+static void omap44xx_prm_read_pending_irqs(unsigned long *events);
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+static void omap44xx_prm_ocp_barrier(void);
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+static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
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+static void omap44xx_prm_restore_irqen(u32 *saved_mask);
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+
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static const struct omap_prcm_irq omap4_prcm_irqs[] = {
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OMAP_PRCM_IRQ("io", 9, 1),
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};
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@@ -207,7 +212,7 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
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* MPU IRQs, and store the result into the two u32s pointed to by @events.
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* No return value.
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*/
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-void omap44xx_prm_read_pending_irqs(unsigned long *events)
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+static void omap44xx_prm_read_pending_irqs(unsigned long *events)
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{
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events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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@@ -224,7 +229,7 @@ void omap44xx_prm_read_pending_irqs(unsigned long *events)
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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-void omap44xx_prm_ocp_barrier(void)
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+static void omap44xx_prm_ocp_barrier(void)
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{
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_REVISION_PRM_OFFSET);
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@@ -241,7 +246,7 @@ void omap44xx_prm_ocp_barrier(void)
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* interrupts reaches the PRM before returning; otherwise, spurious
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* interrupts might occur. No return value.
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*/
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-void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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+static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] =
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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@@ -270,7 +275,7 @@ void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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* No OCP barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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-void omap44xx_prm_restore_irqen(u32 *saved_mask)
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+static void omap44xx_prm_restore_irqen(u32 *saved_mask)
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{
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omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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