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@@ -30,6 +30,11 @@
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#include "cm3xxx.h"
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#include "cm-regbits-34xx.h"
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+static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
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+static void omap3xxx_prm_ocp_barrier(void);
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+static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
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+static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
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+
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static const struct omap_prcm_irq omap3_prcm_irqs[] = {
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OMAP_PRCM_IRQ("wkup", 0, 0),
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OMAP_PRCM_IRQ("io", 9, 1),
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@@ -147,7 +152,7 @@ void omap3xxx_prm_dpll3_reset(void)
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* MPU IRQs, and store the result into the u32 pointed to by @events.
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* No return value.
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*/
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-void omap3xxx_prm_read_pending_irqs(unsigned long *events)
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+static void omap3xxx_prm_read_pending_irqs(unsigned long *events)
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{
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u32 mask, st;
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@@ -166,7 +171,7 @@ void omap3xxx_prm_read_pending_irqs(unsigned long *events)
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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-void omap3xxx_prm_ocp_barrier(void)
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+static void omap3xxx_prm_ocp_barrier(void)
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{
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
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}
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@@ -182,7 +187,7 @@ void omap3xxx_prm_ocp_barrier(void)
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* returning; otherwise, spurious interrupts might occur. No return
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* value.
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*/
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-void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
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+static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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@@ -202,7 +207,7 @@ void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
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* barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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-void omap3xxx_prm_restore_irqen(u32 *saved_mask)
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+static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
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{
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omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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