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@@ -1165,6 +1165,7 @@ mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
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#define MLXSW_MAX_SYSTEM_PORT_ID 0x2502
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#define MLXSW_MAX_SYSTEM_PORT_ID 0x2502
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#define MLXSW_MAX_VLAN_GROUPS_ID 0x2906
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#define MLXSW_MAX_VLAN_GROUPS_ID 0x2906
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#define MLXSW_MAX_REGIONS_ID 0x2901
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#define MLXSW_MAX_REGIONS_ID 0x2901
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+#define MLXSW_MAX_RIF_ID 0x2C02
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#define MLXSW_RESOURCES_QUERY_MAX_QUERIES 100
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#define MLXSW_RESOURCES_QUERY_MAX_QUERIES 100
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#define MLXSW_RESOURCES_PER_QUERY 32
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#define MLXSW_RESOURCES_PER_QUERY 32
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@@ -1212,6 +1213,10 @@ static void mlxsw_pci_resources_query_parse(int id, u64 val,
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resources->max_regions = val;
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resources->max_regions = val;
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resources->max_regions_valid = 1;
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resources->max_regions_valid = 1;
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break;
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break;
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+ case MLXSW_MAX_RIF_ID:
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+ resources->max_rif = val;
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+ resources->max_rif_valid = 1;
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+ break;
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default:
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default:
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break;
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break;
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}
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}
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