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@@ -12,6 +12,7 @@
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#define __ASM_GENERIC_IO_H
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#include <asm/page.h> /* I/O is all done through memory accesses */
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+#include <linux/string.h> /* for memset() and memcpy() */
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#include <linux/types.h>
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#ifdef CONFIG_GENERIC_IOMAP
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@@ -24,260 +25,654 @@
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#define mmiowb() do {} while (0)
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#endif
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-/*****************************************************************************/
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/*
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- * readX/writeX() are used to access memory mapped devices. On some
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- * architectures the memory mapped IO stuff needs to be accessed
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- * differently. On the simple architectures, we just read/write the
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- * memory location directly.
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+ * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
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+ *
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+ * On some architectures memory mapped IO needs to be accessed differently.
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+ * On the simple architectures, we just read/write the memory location
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+ * directly.
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*/
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+
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#ifndef __raw_readb
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+#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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- return *(const volatile u8 __force *) addr;
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+ return *(const volatile u8 __force *)addr;
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}
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#endif
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#ifndef __raw_readw
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+#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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- return *(const volatile u16 __force *) addr;
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+ return *(const volatile u16 __force *)addr;
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}
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#endif
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#ifndef __raw_readl
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+#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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- return *(const volatile u32 __force *) addr;
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+ return *(const volatile u32 __force *)addr;
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}
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#endif
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-#define readb __raw_readb
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-
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-#define readw readw
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-static inline u16 readw(const volatile void __iomem *addr)
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-{
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- return __le16_to_cpu(__raw_readw(addr));
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-}
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-
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-#define readl readl
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-static inline u32 readl(const volatile void __iomem *addr)
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+#ifdef CONFIG_64BIT
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+#ifndef __raw_readq
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+#define __raw_readq __raw_readq
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+static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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- return __le32_to_cpu(__raw_readl(addr));
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+ return *(const volatile u64 __force *)addr;
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}
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+#endif
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+#endif /* CONFIG_64BIT */
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#ifndef __raw_writeb
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-static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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+#define __raw_writeb __raw_writeb
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+static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
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{
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- *(volatile u8 __force *) addr = b;
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+ *(volatile u8 __force *)addr = value;
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}
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#endif
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#ifndef __raw_writew
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-static inline void __raw_writew(u16 b, volatile void __iomem *addr)
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+#define __raw_writew __raw_writew
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+static inline void __raw_writew(u16 value, volatile void __iomem *addr)
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{
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- *(volatile u16 __force *) addr = b;
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+ *(volatile u16 __force *)addr = value;
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}
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#endif
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#ifndef __raw_writel
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-static inline void __raw_writel(u32 b, volatile void __iomem *addr)
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+#define __raw_writel __raw_writel
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+static inline void __raw_writel(u32 value, volatile void __iomem *addr)
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{
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- *(volatile u32 __force *) addr = b;
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+ *(volatile u32 __force *)addr = value;
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}
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#endif
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-#define writeb __raw_writeb
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-#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
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-#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
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-
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#ifdef CONFIG_64BIT
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-#ifndef __raw_readq
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-static inline u64 __raw_readq(const volatile void __iomem *addr)
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+#ifndef __raw_writeq
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+#define __raw_writeq __raw_writeq
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+static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
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{
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- return *(const volatile u64 __force *) addr;
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+ *(volatile u64 __force *)addr = value;
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}
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#endif
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+#endif /* CONFIG_64BIT */
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-#define readq readq
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-static inline u64 readq(const volatile void __iomem *addr)
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-{
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- return __le64_to_cpu(__raw_readq(addr));
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-}
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+/*
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+ * {read,write}{b,w,l,q}() access little endian memory and return result in
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+ * native endianness.
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+ */
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-#ifndef __raw_writeq
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-static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
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+#ifndef readb
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+#define readb readb
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+static inline u8 readb(const volatile void __iomem *addr)
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{
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- *(volatile u64 __force *) addr = b;
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+ return __raw_readb(addr);
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}
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#endif
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-#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
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-#endif /* CONFIG_64BIT */
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-
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-#ifndef PCI_IOBASE
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-#define PCI_IOBASE ((void __iomem *) 0)
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+#ifndef readw
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+#define readw readw
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+static inline u16 readw(const volatile void __iomem *addr)
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+{
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+ return __le16_to_cpu(__raw_readw(addr));
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+}
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#endif
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-/*****************************************************************************/
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-/*
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- * traditional input/output functions
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- */
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-
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-static inline u8 inb(unsigned long addr)
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+#ifndef readl
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+#define readl readl
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+static inline u32 readl(const volatile void __iomem *addr)
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{
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- return readb(addr + PCI_IOBASE);
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+ return __le32_to_cpu(__raw_readl(addr));
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}
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+#endif
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-static inline u16 inw(unsigned long addr)
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+#ifdef CONFIG_64BIT
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+#ifndef readq
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+#define readq readq
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+static inline u64 readq(const volatile void __iomem *addr)
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{
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- return readw(addr + PCI_IOBASE);
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+ return __le64_to_cpu(__raw_readq(addr));
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}
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+#endif
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+#endif /* CONFIG_64BIT */
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-static inline u32 inl(unsigned long addr)
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+#ifndef writeb
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+#define writeb writeb
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+static inline void writeb(u8 value, volatile void __iomem *addr)
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{
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- return readl(addr + PCI_IOBASE);
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+ __raw_writeb(value, addr);
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}
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+#endif
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-static inline void outb(u8 b, unsigned long addr)
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+#ifndef writew
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+#define writew writew
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+static inline void writew(u16 value, volatile void __iomem *addr)
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{
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- writeb(b, addr + PCI_IOBASE);
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+ __raw_writew(cpu_to_le16(value), addr);
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}
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+#endif
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-static inline void outw(u16 b, unsigned long addr)
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+#ifndef writel
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+#define writel writel
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+static inline void writel(u32 value, volatile void __iomem *addr)
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{
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- writew(b, addr + PCI_IOBASE);
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+ __raw_writel(__cpu_to_le32(value), addr);
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}
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+#endif
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-static inline void outl(u32 b, unsigned long addr)
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+#ifdef CONFIG_64BIT
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+#ifndef writeq
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+#define writeq writeq
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+static inline void writeq(u64 value, volatile void __iomem *addr)
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{
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- writel(b, addr + PCI_IOBASE);
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+ __raw_writeq(__cpu_to_le64(value), addr);
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}
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+#endif
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+#endif /* CONFIG_64BIT */
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-#define inb_p(addr) inb(addr)
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-#define inw_p(addr) inw(addr)
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-#define inl_p(addr) inl(addr)
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-#define outb_p(x, addr) outb((x), (addr))
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-#define outw_p(x, addr) outw((x), (addr))
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-#define outl_p(x, addr) outl((x), (addr))
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-
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-#ifndef insb
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-static inline void insb(unsigned long addr, void *buffer, int count)
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+/*
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+ * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
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+ * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
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+ */
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+#ifndef readsb
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+#define readsb readsb
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+static inline void readsb(const volatile void __iomem *addr, void *buffer,
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+ unsigned int count)
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{
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if (count) {
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u8 *buf = buffer;
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+
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do {
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- u8 x = __raw_readb(addr + PCI_IOBASE);
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+ u8 x = __raw_readb(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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-#ifndef insw
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-static inline void insw(unsigned long addr, void *buffer, int count)
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+#ifndef readsw
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+#define readsw readsw
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+static inline void readsw(const volatile void __iomem *addr, void *buffer,
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+ unsigned int count)
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{
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if (count) {
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u16 *buf = buffer;
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+
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do {
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- u16 x = __raw_readw(addr + PCI_IOBASE);
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+ u16 x = __raw_readw(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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-#ifndef insl
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-static inline void insl(unsigned long addr, void *buffer, int count)
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+#ifndef readsl
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+#define readsl readsl
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+static inline void readsl(const volatile void __iomem *addr, void *buffer,
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+ unsigned int count)
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{
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if (count) {
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u32 *buf = buffer;
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+
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do {
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- u32 x = __raw_readl(addr + PCI_IOBASE);
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+ u32 x = __raw_readl(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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-#ifndef outsb
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-static inline void outsb(unsigned long addr, const void *buffer, int count)
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+#ifdef CONFIG_64BIT
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+#ifndef readsq
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+#define readsq readsq
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+static inline void readsq(const volatile void __iomem *addr, void *buffer,
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+ unsigned int count)
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+{
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+ if (count) {
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+ u64 *buf = buffer;
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+
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+ do {
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+ u64 x = __raw_readq(addr);
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+ *buf++ = x;
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+ } while (--count);
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+ }
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+}
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+#endif
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+#endif /* CONFIG_64BIT */
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+
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+#ifndef writesb
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+#define writesb writesb
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+static inline void writesb(volatile void __iomem *addr, const void *buffer,
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+ unsigned int count)
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{
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if (count) {
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const u8 *buf = buffer;
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+
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do {
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- __raw_writeb(*buf++, addr + PCI_IOBASE);
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+ __raw_writeb(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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-#ifndef outsw
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-static inline void outsw(unsigned long addr, const void *buffer, int count)
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+#ifndef writesw
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+#define writesw writesw
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+static inline void writesw(volatile void __iomem *addr, const void *buffer,
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+ unsigned int count)
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{
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if (count) {
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const u16 *buf = buffer;
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+
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do {
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- __raw_writew(*buf++, addr + PCI_IOBASE);
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+ __raw_writew(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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-#ifndef outsl
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-static inline void outsl(unsigned long addr, const void *buffer, int count)
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+#ifndef writesl
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+#define writesl writesl
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+static inline void writesl(volatile void __iomem *addr, const void *buffer,
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+ unsigned int count)
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{
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if (count) {
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const u32 *buf = buffer;
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+
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do {
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- __raw_writel(*buf++, addr + PCI_IOBASE);
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+ __raw_writel(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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-#ifndef CONFIG_GENERIC_IOMAP
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-#define ioread8(addr) readb(addr)
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-#define ioread16(addr) readw(addr)
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-#define ioread16be(addr) __be16_to_cpu(__raw_readw(addr))
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-#define ioread32(addr) readl(addr)
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-#define ioread32be(addr) __be32_to_cpu(__raw_readl(addr))
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-
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-#define iowrite8(v, addr) writeb((v), (addr))
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-#define iowrite16(v, addr) writew((v), (addr))
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-#define iowrite16be(v, addr) __raw_writew(__cpu_to_be16(v), addr)
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-#define iowrite32(v, addr) writel((v), (addr))
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-#define iowrite32be(v, addr) __raw_writel(__cpu_to_be32(v), addr)
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-
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-#define ioread8_rep(p, dst, count) \
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- insb((unsigned long) (p), (dst), (count))
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-#define ioread16_rep(p, dst, count) \
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- insw((unsigned long) (p), (dst), (count))
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-#define ioread32_rep(p, dst, count) \
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- insl((unsigned long) (p), (dst), (count))
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-
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-#define iowrite8_rep(p, src, count) \
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- outsb((unsigned long) (p), (src), (count))
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-#define iowrite16_rep(p, src, count) \
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- outsw((unsigned long) (p), (src), (count))
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-#define iowrite32_rep(p, src, count) \
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- outsl((unsigned long) (p), (src), (count))
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-#endif /* CONFIG_GENERIC_IOMAP */
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+#ifdef CONFIG_64BIT
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+#ifndef writesq
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+#define writesq writesq
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+static inline void writesq(volatile void __iomem *addr, const void *buffer,
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+ unsigned int count)
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+{
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+ if (count) {
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+ const u64 *buf = buffer;
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+
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+ do {
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+ __raw_writeq(*buf++, addr);
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+ } while (--count);
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+ }
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+}
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+#endif
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+#endif /* CONFIG_64BIT */
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+
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+#ifndef PCI_IOBASE
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+#define PCI_IOBASE ((void __iomem *)0)
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+#endif
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#ifndef IO_SPACE_LIMIT
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#define IO_SPACE_LIMIT 0xffff
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#endif
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+/*
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+ * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
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+ * implemented on hardware that needs an additional delay for I/O accesses to
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+ * take effect.
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+ */
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+
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+#ifndef inb
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+#define inb inb
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+static inline u8 inb(unsigned long addr)
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+{
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+ return readb(PCI_IOBASE + addr);
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+}
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+#endif
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+
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|
|
+#ifndef inw
|
|
|
+#define inw inw
|
|
|
+static inline u16 inw(unsigned long addr)
|
|
|
+{
|
|
|
+ return readw(PCI_IOBASE + addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef inl
|
|
|
+#define inl inl
|
|
|
+static inline u32 inl(unsigned long addr)
|
|
|
+{
|
|
|
+ return readl(PCI_IOBASE + addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outb
|
|
|
+#define outb outb
|
|
|
+static inline void outb(u8 value, unsigned long addr)
|
|
|
+{
|
|
|
+ writeb(value, PCI_IOBASE + addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outw
|
|
|
+#define outw outw
|
|
|
+static inline void outw(u16 value, unsigned long addr)
|
|
|
+{
|
|
|
+ writew(value, PCI_IOBASE + addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outl
|
|
|
+#define outl outl
|
|
|
+static inline void outl(u32 value, unsigned long addr)
|
|
|
+{
|
|
|
+ writel(value, PCI_IOBASE + addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef inb_p
|
|
|
+#define inb_p inb_p
|
|
|
+static inline u8 inb_p(unsigned long addr)
|
|
|
+{
|
|
|
+ return inb(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef inw_p
|
|
|
+#define inw_p inw_p
|
|
|
+static inline u16 inw_p(unsigned long addr)
|
|
|
+{
|
|
|
+ return inw(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef inl_p
|
|
|
+#define inl_p inl_p
|
|
|
+static inline u32 inl_p(unsigned long addr)
|
|
|
+{
|
|
|
+ return inl(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outb_p
|
|
|
+#define outb_p outb_p
|
|
|
+static inline void outb_p(u8 value, unsigned long addr)
|
|
|
+{
|
|
|
+ outb(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outw_p
|
|
|
+#define outw_p outw_p
|
|
|
+static inline void outw_p(u16 value, unsigned long addr)
|
|
|
+{
|
|
|
+ outw(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outl_p
|
|
|
+#define outl_p outl_p
|
|
|
+static inline void outl_p(u32 value, unsigned long addr)
|
|
|
+{
|
|
|
+ outl(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+/*
|
|
|
+ * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
|
|
|
+ * single I/O port multiple times.
|
|
|
+ */
|
|
|
+
|
|
|
+#ifndef insb
|
|
|
+#define insb insb
|
|
|
+static inline void insb(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ readsb(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef insw
|
|
|
+#define insw insw
|
|
|
+static inline void insw(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ readsw(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef insl
|
|
|
+#define insl insl
|
|
|
+static inline void insl(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ readsl(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsb
|
|
|
+#define outsb outsb
|
|
|
+static inline void outsb(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesb(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsw
|
|
|
+#define outsw outsw
|
|
|
+static inline void outsw(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesw(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsl
|
|
|
+#define outsl outsl
|
|
|
+static inline void outsl(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesl(PCI_IOBASE + addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef insb_p
|
|
|
+#define insb_p insb_p
|
|
|
+static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ insb(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef insw_p
|
|
|
+#define insw_p insw_p
|
|
|
+static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ insw(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef insl_p
|
|
|
+#define insl_p insl_p
|
|
|
+static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ insl(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsb_p
|
|
|
+#define outsb_p outsb_p
|
|
|
+static inline void outsb_p(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ outsb(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsw_p
|
|
|
+#define outsw_p outsw_p
|
|
|
+static inline void outsw_p(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ outsw(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef outsl_p
|
|
|
+#define outsl_p outsl_p
|
|
|
+static inline void outsl_p(unsigned long addr, const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ outsl(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef CONFIG_GENERIC_IOMAP
|
|
|
+#ifndef ioread8
|
|
|
+#define ioread8 ioread8
|
|
|
+static inline u8 ioread8(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ return readb(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread16
|
|
|
+#define ioread16 ioread16
|
|
|
+static inline u16 ioread16(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ return readw(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread32
|
|
|
+#define ioread32 ioread32
|
|
|
+static inline u32 ioread32(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ return readl(addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite8
|
|
|
+#define iowrite8 iowrite8
|
|
|
+static inline void iowrite8(u8 value, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ writeb(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite16
|
|
|
+#define iowrite16 iowrite16
|
|
|
+static inline void iowrite16(u16 value, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ writew(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite32
|
|
|
+#define iowrite32 iowrite32
|
|
|
+static inline void iowrite32(u32 value, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ writel(value, addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread16be
|
|
|
+#define ioread16be ioread16be
|
|
|
+static inline u16 ioread16be(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ return __be16_to_cpu(__raw_readw(addr));
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread32be
|
|
|
+#define ioread32be ioread32be
|
|
|
+static inline u32 ioread32be(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ return __be32_to_cpu(__raw_readl(addr));
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite16be
|
|
|
+#define iowrite16be iowrite16be
|
|
|
+static inline void iowrite16be(u16 value, void volatile __iomem *addr)
|
|
|
+{
|
|
|
+ __raw_writew(__cpu_to_be16(value), addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite32be
|
|
|
+#define iowrite32be iowrite32be
|
|
|
+static inline void iowrite32be(u32 value, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ __raw_writel(__cpu_to_be32(value), addr);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread8_rep
|
|
|
+#define ioread8_rep ioread8_rep
|
|
|
+static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ readsb(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread16_rep
|
|
|
+#define ioread16_rep ioread16_rep
|
|
|
+static inline void ioread16_rep(const volatile void __iomem *addr,
|
|
|
+ void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ readsw(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ioread32_rep
|
|
|
+#define ioread32_rep ioread32_rep
|
|
|
+static inline void ioread32_rep(const volatile void __iomem *addr,
|
|
|
+ void *buffer, unsigned int count)
|
|
|
+{
|
|
|
+ readsl(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite8_rep
|
|
|
+#define iowrite8_rep iowrite8_rep
|
|
|
+static inline void iowrite8_rep(volatile void __iomem *addr,
|
|
|
+ const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesb(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite16_rep
|
|
|
+#define iowrite16_rep iowrite16_rep
|
|
|
+static inline void iowrite16_rep(volatile void __iomem *addr,
|
|
|
+ const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesw(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef iowrite32_rep
|
|
|
+#define iowrite32_rep iowrite32_rep
|
|
|
+static inline void iowrite32_rep(volatile void __iomem *addr,
|
|
|
+ const void *buffer,
|
|
|
+ unsigned int count)
|
|
|
+{
|
|
|
+ writesl(addr, buffer, count);
|
|
|
+}
|
|
|
+#endif
|
|
|
+#endif /* CONFIG_GENERIC_IOMAP */
|
|
|
+
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
#include <linux/vmalloc.h>
|
|
|
-#define __io_virt(x) ((void __force *) (x))
|
|
|
+#define __io_virt(x) ((void __force *)(x))
|
|
|
|
|
|
#ifndef CONFIG_GENERIC_IOMAP
|
|
|
struct pci_dev;
|
|
|
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
|
|
|
|
|
|
#ifndef pci_iounmap
|
|
|
+#define pci_iounmap pci_iounmap
|
|
|
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
|
|
|
{
|
|
|
}
|
|
|
@@ -289,11 +684,15 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
|
|
|
* These are pretty trivial
|
|
|
*/
|
|
|
#ifndef virt_to_phys
|
|
|
+#define virt_to_phys virt_to_phys
|
|
|
static inline unsigned long virt_to_phys(volatile void *address)
|
|
|
{
|
|
|
return __pa((unsigned long)address);
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#ifndef phys_to_virt
|
|
|
+#define phys_to_virt phys_to_virt
|
|
|
static inline void *phys_to_virt(unsigned long address)
|
|
|
{
|
|
|
return __va(address);
|
|
|
@@ -306,37 +705,65 @@ static inline void *phys_to_virt(unsigned long address)
|
|
|
* This implementation is for the no-MMU case only... if you have an MMU
|
|
|
* you'll need to provide your own definitions.
|
|
|
*/
|
|
|
+
|
|
|
#ifndef CONFIG_MMU
|
|
|
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
|
|
|
+#ifndef ioremap
|
|
|
+#define ioremap ioremap
|
|
|
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
|
|
|
{
|
|
|
- return (void __iomem*) (unsigned long)offset;
|
|
|
+ return (void __iomem *)(unsigned long)offset;
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
-#define __ioremap(offset, size, flags) ioremap(offset, size)
|
|
|
+#ifndef __ioremap
|
|
|
+#define __ioremap __ioremap
|
|
|
+static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
|
|
|
+ unsigned long flags)
|
|
|
+{
|
|
|
+ return ioremap(offset, size);
|
|
|
+}
|
|
|
+#endif
|
|
|
|
|
|
#ifndef ioremap_nocache
|
|
|
-#define ioremap_nocache ioremap
|
|
|
+#define ioremap_nocache ioremap_nocache
|
|
|
+static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
|
|
|
+{
|
|
|
+ return ioremap(offset, size);
|
|
|
+}
|
|
|
#endif
|
|
|
|
|
|
#ifndef ioremap_wc
|
|
|
-#define ioremap_wc ioremap_nocache
|
|
|
+#define ioremap_wc ioremap_wc
|
|
|
+static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
|
|
|
+{
|
|
|
+ return ioremap_nocache(offset, size);
|
|
|
+}
|
|
|
#endif
|
|
|
|
|
|
+#ifndef iounmap
|
|
|
+#define iounmap iounmap
|
|
|
static inline void iounmap(void __iomem *addr)
|
|
|
{
|
|
|
}
|
|
|
+#endif
|
|
|
#endif /* CONFIG_MMU */
|
|
|
|
|
|
#ifdef CONFIG_HAS_IOPORT_MAP
|
|
|
#ifndef CONFIG_GENERIC_IOMAP
|
|
|
+#ifndef ioport_map
|
|
|
+#define ioport_map ioport_map
|
|
|
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
|
|
{
|
|
|
return PCI_IOBASE + (port & IO_SPACE_LIMIT);
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#ifndef ioport_unmap
|
|
|
+#define ioport_unmap ioport_unmap
|
|
|
static inline void ioport_unmap(void __iomem *p)
|
|
|
{
|
|
|
}
|
|
|
+#endif
|
|
|
#else /* CONFIG_GENERIC_IOMAP */
|
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
|
|
|
extern void ioport_unmap(void __iomem *p);
|
|
|
@@ -344,35 +771,68 @@ extern void ioport_unmap(void __iomem *p);
|
|
|
#endif /* CONFIG_HAS_IOPORT_MAP */
|
|
|
|
|
|
#ifndef xlate_dev_kmem_ptr
|
|
|
-#define xlate_dev_kmem_ptr(p) p
|
|
|
+#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
|
|
|
+static inline void *xlate_dev_kmem_ptr(void *addr)
|
|
|
+{
|
|
|
+ return addr;
|
|
|
+}
|
|
|
#endif
|
|
|
+
|
|
|
#ifndef xlate_dev_mem_ptr
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-#define xlate_dev_mem_ptr(p) __va(p)
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+#define xlate_dev_mem_ptr xlate_dev_mem_ptr
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+static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
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+{
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+ return __va(addr);
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+}
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+#endif
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+
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+#ifndef unxlate_dev_mem_ptr
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+#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
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+static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
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+{
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+}
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#endif
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#ifdef CONFIG_VIRT_TO_BUS
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#ifndef virt_to_bus
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-static inline unsigned long virt_to_bus(volatile void *address)
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+static inline unsigned long virt_to_bus(void *address)
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{
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- return ((unsigned long) address);
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+ return (unsigned long)address;
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}
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static inline void *bus_to_virt(unsigned long address)
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{
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- return (void *) address;
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+ return (void *)address;
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}
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#endif
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#endif
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#ifndef memset_io
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-#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
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+#define memset_io memset_io
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+static inline void memset_io(volatile void __iomem *addr, int value,
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+ size_t size)
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+{
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+ memset(__io_virt(addr), value, size);
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+}
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#endif
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#ifndef memcpy_fromio
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-#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
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+#define memcpy_fromio memcpy_fromio
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+static inline void memcpy_fromio(void *buffer,
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+ const volatile void __iomem *addr,
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+ size_t size)
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+{
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+ memcpy(buffer, __io_virt(addr), size);
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+}
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#endif
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+
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#ifndef memcpy_toio
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-#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
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+#define memcpy_toio memcpy_toio
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+static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
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+ size_t size)
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+{
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+ memcpy(__io_virt(addr), buffer, size);
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+}
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#endif
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#endif /* __KERNEL__ */
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Arnd Bergmann