|
@@ -228,6 +228,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
|
|
|
if (!(reg16 & PCI_EXP_LNKSTA_SLC))
|
|
|
same_clock = 0;
|
|
|
|
|
|
+ /* Port might be already in common clock mode */
|
|
|
+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
|
|
|
+ if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
|
|
|
+ bool consistent = true;
|
|
|
+
|
|
|
+ list_for_each_entry(child, &linkbus->devices, bus_list) {
|
|
|
+ pcie_capability_read_word(child, PCI_EXP_LNKCTL,
|
|
|
+ ®16);
|
|
|
+ if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
|
|
|
+ consistent = false;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ if (consistent)
|
|
|
+ return;
|
|
|
+ pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
|
|
|
+ }
|
|
|
+
|
|
|
/* Configure downstream component, all functions */
|
|
|
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
|
|
pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
|
|
@@ -322,7 +340,7 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
|
|
|
|
|
|
static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
|
|
|
{
|
|
|
- u64 threshold_ns = threshold_us * 1000;
|
|
|
+ u32 threshold_ns = threshold_us * 1000;
|
|
|
|
|
|
/* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
|
|
|
if (threshold_ns < 32) {
|