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@@ -0,0 +1,314 @@
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+/*
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+ * LTC2632 Digital to analog convertors spi driver
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+ *
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+ * Copyright 2017 Maxime Roussin-Bélanger
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+ *
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+ * Licensed under the GPL-2.
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/spi/spi.h>
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+#include <linux/module.h>
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+#include <linux/iio/iio.h>
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+
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+#define LTC2632_DAC_CHANNELS 2
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+
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+#define LTC2632_ADDR_DAC0 0x0
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+#define LTC2632_ADDR_DAC1 0x1
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+
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+#define LTC2632_CMD_WRITE_INPUT_N 0x0
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+#define LTC2632_CMD_UPDATE_DAC_N 0x1
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+#define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
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+#define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N 0x3
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+#define LTC2632_CMD_POWERDOWN_DAC_N 0x4
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+#define LTC2632_CMD_POWERDOWN_CHIP 0x5
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+#define LTC2632_CMD_INTERNAL_REFER 0x6
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+#define LTC2632_CMD_EXTERNAL_REFER 0x7
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+
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+/**
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+ * struct ltc2632_chip_info - chip specific information
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+ * @channels: channel spec for the DAC
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+ * @vref_mv: reference voltage
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+ */
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+struct ltc2632_chip_info {
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+ const struct iio_chan_spec *channels;
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+ const int vref_mv;
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+};
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+
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+/**
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+ * struct ltc2632_state - driver instance specific data
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+ * @spi_dev: pointer to the spi_device struct
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+ * @powerdown_cache_mask used to show current channel powerdown state
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+ */
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+struct ltc2632_state {
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+ struct spi_device *spi_dev;
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+ unsigned int powerdown_cache_mask;
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+};
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+
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+enum ltc2632_supported_device_ids {
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+ ID_LTC2632L12,
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+ ID_LTC2632L10,
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+ ID_LTC2632L8,
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+ ID_LTC2632H12,
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+ ID_LTC2632H10,
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+ ID_LTC2632H8,
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+};
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+
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+static int ltc2632_spi_write(struct spi_device *spi,
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+ u8 cmd, u8 addr, u16 val, u8 shift)
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+{
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+ u32 data;
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+ u8 msg[3];
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+
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+ /*
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+ * The input shift register is 24 bits wide.
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+ * The next four are the command bits, C3 to C0,
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+ * followed by the 4-bit DAC address, A3 to A0, and then the
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+ * 12-, 10-, 8-bit data-word. The data-word comprises the 12-,
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+ * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits.
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+ */
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+ data = (cmd << 20) | (addr << 16) | (val << shift);
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+ msg[0] = data >> 16;
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+ msg[1] = data >> 8;
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+ msg[2] = data;
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+
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+ return spi_write(spi, msg, sizeof(msg));
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+}
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+
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+static int ltc2632_read_raw(struct iio_dev *indio_dev,
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+ struct iio_chan_spec const *chan,
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+ int *val,
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+ int *val2,
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+ long m)
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+{
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+ struct ltc2632_chip_info *chip_info;
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+
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+ const struct ltc2632_state *st = iio_priv(indio_dev);
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+ const struct spi_device_id *spi_dev_id = spi_get_device_id(st->spi_dev);
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+
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+ chip_info = (struct ltc2632_chip_info *)spi_dev_id->driver_data;
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+
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+ switch (m) {
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+ case IIO_CHAN_INFO_SCALE:
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+ *val = chip_info->vref_mv;
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+ *val2 = chan->scan_type.realbits;
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+ return IIO_VAL_FRACTIONAL_LOG2;
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+ }
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+ return -EINVAL;
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+}
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+
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+static int ltc2632_write_raw(struct iio_dev *indio_dev,
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+ struct iio_chan_spec const *chan,
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+ int val,
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+ int val2,
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+ long mask)
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+{
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+ struct ltc2632_state *st = iio_priv(indio_dev);
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+
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+ switch (mask) {
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+ case IIO_CHAN_INFO_RAW:
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+ if (val >= (1 << chan->scan_type.realbits) || val < 0)
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+ return -EINVAL;
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+
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+ return ltc2632_spi_write(st->spi_dev,
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+ LTC2632_CMD_WRITE_INPUT_N_UPDATE_N,
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+ chan->address, val,
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+ chan->scan_type.shift);
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev,
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+ uintptr_t private,
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+ const struct iio_chan_spec *chan,
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+ char *buf)
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+{
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+ struct ltc2632_state *st = iio_priv(indio_dev);
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+
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+ return sprintf(buf, "%d\n",
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+ !!(st->powerdown_cache_mask & (1 << chan->channel)));
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+}
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+
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+static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev,
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+ uintptr_t private,
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+ const struct iio_chan_spec *chan,
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+ const char *buf,
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+ size_t len)
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+{
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+ bool pwr_down;
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+ int ret;
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+ struct ltc2632_state *st = iio_priv(indio_dev);
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+
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+ ret = strtobool(buf, &pwr_down);
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+ if (ret)
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+ return ret;
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+
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+ if (pwr_down)
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+ st->powerdown_cache_mask |= (1 << chan->channel);
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+ else
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+ st->powerdown_cache_mask &= ~(1 << chan->channel);
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+
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+ ret = ltc2632_spi_write(st->spi_dev,
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+ LTC2632_CMD_POWERDOWN_DAC_N,
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+ chan->channel, 0, 0);
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+
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+ return ret ? ret : len;
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+}
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+
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+static const struct iio_info ltc2632_info = {
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+ .write_raw = ltc2632_write_raw,
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+ .read_raw = ltc2632_read_raw,
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+ .driver_module = THIS_MODULE,
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+};
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+
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+static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = {
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+ {
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+ .name = "powerdown",
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+ .read = ltc2632_read_dac_powerdown,
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+ .write = ltc2632_write_dac_powerdown,
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+ .shared = IIO_SEPARATE,
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+ },
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+ { },
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+};
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+
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+#define LTC2632_CHANNEL(_chan, _bits) { \
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+ .type = IIO_VOLTAGE, \
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+ .indexed = 1, \
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+ .output = 1, \
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+ .channel = (_chan), \
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+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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+ .address = (_chan), \
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+ .scan_type = { \
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+ .realbits = (_bits), \
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+ .shift = 16 - (_bits), \
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+ }, \
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+ .ext_info = ltc2632_ext_info, \
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+}
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+
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+#define DECLARE_LTC2632_CHANNELS(_name, _bits) \
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+ const struct iio_chan_spec _name ## _channels[] = { \
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+ LTC2632_CHANNEL(0, _bits), \
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+ LTC2632_CHANNEL(1, _bits), \
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+ }
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+
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+static DECLARE_LTC2632_CHANNELS(ltc2632l12, 12);
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+static DECLARE_LTC2632_CHANNELS(ltc2632l10, 10);
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+static DECLARE_LTC2632_CHANNELS(ltc2632l8, 8);
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+
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+static DECLARE_LTC2632_CHANNELS(ltc2632h12, 12);
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+static DECLARE_LTC2632_CHANNELS(ltc2632h10, 10);
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+static DECLARE_LTC2632_CHANNELS(ltc2632h8, 8);
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+
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+static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = {
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+ [ID_LTC2632L12] = {
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+ .channels = ltc2632l12_channels,
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+ .vref_mv = 2500,
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+ },
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+ [ID_LTC2632L10] = {
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+ .channels = ltc2632l10_channels,
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+ .vref_mv = 2500,
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+ },
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+ [ID_LTC2632L8] = {
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+ .channels = ltc2632l8_channels,
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+ .vref_mv = 2500,
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+ },
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+ [ID_LTC2632H12] = {
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+ .channels = ltc2632h12_channels,
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+ .vref_mv = 4096,
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+ },
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+ [ID_LTC2632H10] = {
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+ .channels = ltc2632h10_channels,
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+ .vref_mv = 4096,
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+ },
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+ [ID_LTC2632H8] = {
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+ .channels = ltc2632h8_channels,
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+ .vref_mv = 4096,
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+ },
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+};
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+
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+static int ltc2632_probe(struct spi_device *spi)
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+{
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+ struct ltc2632_state *st;
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+ struct iio_dev *indio_dev;
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+ struct ltc2632_chip_info *chip_info;
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+ int ret;
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+
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+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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+ if (!indio_dev)
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+ return -ENOMEM;
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+
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+ st = iio_priv(indio_dev);
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+
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+ spi_set_drvdata(spi, indio_dev);
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+ st->spi_dev = spi;
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+
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+ chip_info = (struct ltc2632_chip_info *)
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+ spi_get_device_id(spi)->driver_data;
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+
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+ indio_dev->dev.parent = &spi->dev;
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+ indio_dev->name = dev_of_node(&spi->dev) ? dev_of_node(&spi->dev)->name
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+ : spi_get_device_id(spi)->name;
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+ indio_dev->info = <c2632_info;
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+ indio_dev->modes = INDIO_DIRECT_MODE;
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+ indio_dev->channels = chip_info->channels;
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+ indio_dev->num_channels = LTC2632_DAC_CHANNELS;
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+
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+ ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER, 0, 0, 0);
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+ if (ret) {
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+ dev_err(&spi->dev,
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+ "Set internal reference command failed, %d\n", ret);
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+ return ret;
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+ }
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+
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+ return devm_iio_device_register(&spi->dev, indio_dev);
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+}
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+
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+static const struct spi_device_id ltc2632_id[] = {
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+ { "ltc2632-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L12] },
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+ { "ltc2632-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L10] },
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+ { "ltc2632-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L8] },
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+ { "ltc2632-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H12] },
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+ { "ltc2632-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H10] },
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+ { "ltc2632-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H8] },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(spi, ltc2632_id);
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+
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+static struct spi_driver ltc2632_driver = {
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+ .driver = {
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+ .name = "ltc2632",
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+ },
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+ .probe = ltc2632_probe,
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+ .id_table = ltc2632_id,
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+};
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+module_spi_driver(ltc2632_driver);
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+
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+static const struct of_device_id ltc2632_of_match[] = {
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+ {
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+ .compatible = "lltc,ltc2632-l12",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632L12]
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+ }, {
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+ .compatible = "lltc,ltc2632-l10",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632L10]
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+ }, {
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+ .compatible = "lltc,ltc2632-l8",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632L8]
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+ }, {
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+ .compatible = "lltc,ltc2632-h12",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632H12]
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+ }, {
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+ .compatible = "lltc,ltc2632-h10",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632H10]
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+ }, {
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+ .compatible = "lltc,ltc2632-h8",
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+ .data = <c2632_chip_info_tbl[ID_LTC2632H8]
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+ },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, ltc2632_of_match);
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+
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+MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>");
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+MODULE_DESCRIPTION("LTC2632 DAC SPI driver");
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+MODULE_LICENSE("GPL v2");
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