ocelot_board.c 7.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi Ocelot Switch driver
  4. *
  5. * Copyright (c) 2017 Microsemi Corporation
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/module.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/skbuff.h>
  13. #include "ocelot.h"
  14. static int ocelot_parse_ifh(u32 *ifh, struct frame_info *info)
  15. {
  16. int i;
  17. u8 llen, wlen;
  18. /* The IFH is in network order, switch to CPU order */
  19. for (i = 0; i < IFH_LEN; i++)
  20. ifh[i] = ntohl((__force __be32)ifh[i]);
  21. wlen = (ifh[1] >> 7) & 0xff;
  22. llen = (ifh[1] >> 15) & 0x3f;
  23. info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  24. info->port = (ifh[2] & GENMASK(14, 11)) >> 11;
  25. info->cpuq = (ifh[3] & GENMASK(27, 20)) >> 20;
  26. info->tag_type = (ifh[3] & BIT(16)) >> 16;
  27. info->vid = ifh[3] & GENMASK(11, 0);
  28. return 0;
  29. }
  30. static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  31. u32 *rval)
  32. {
  33. u32 val;
  34. u32 bytes_valid;
  35. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  36. if (val == XTR_NOT_READY) {
  37. if (ifh)
  38. return -EIO;
  39. do {
  40. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  41. } while (val == XTR_NOT_READY);
  42. }
  43. switch (val) {
  44. case XTR_ABORT:
  45. return -EIO;
  46. case XTR_EOF_0:
  47. case XTR_EOF_1:
  48. case XTR_EOF_2:
  49. case XTR_EOF_3:
  50. case XTR_PRUNED:
  51. bytes_valid = XTR_VALID_BYTES(val);
  52. val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  53. if (val == XTR_ESCAPE)
  54. *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  55. else
  56. *rval = val;
  57. return bytes_valid;
  58. case XTR_ESCAPE:
  59. *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  60. return 4;
  61. default:
  62. *rval = val;
  63. return 4;
  64. }
  65. }
  66. static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  67. {
  68. struct ocelot *ocelot = arg;
  69. int i = 0, grp = 0;
  70. int err = 0;
  71. if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  72. return IRQ_NONE;
  73. do {
  74. struct sk_buff *skb;
  75. struct net_device *dev;
  76. u32 *buf;
  77. int sz, len, buf_len;
  78. u32 ifh[4];
  79. u32 val;
  80. struct frame_info info;
  81. for (i = 0; i < IFH_LEN; i++) {
  82. err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
  83. if (err != 4)
  84. break;
  85. }
  86. if (err != 4)
  87. break;
  88. ocelot_parse_ifh(ifh, &info);
  89. dev = ocelot->ports[info.port]->dev;
  90. skb = netdev_alloc_skb(dev, info.len);
  91. if (unlikely(!skb)) {
  92. netdev_err(dev, "Unable to allocate sk_buff\n");
  93. err = -ENOMEM;
  94. break;
  95. }
  96. buf_len = info.len - ETH_FCS_LEN;
  97. buf = (u32 *)skb_put(skb, buf_len);
  98. len = 0;
  99. do {
  100. sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
  101. *buf++ = val;
  102. len += sz;
  103. } while (len < buf_len);
  104. /* Read the FCS and discard it */
  105. sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
  106. /* Update the statistics if part of the FCS was read before */
  107. len -= ETH_FCS_LEN - sz;
  108. if (sz < 0) {
  109. err = sz;
  110. break;
  111. }
  112. /* Everything we see on an interface that is in the HW bridge
  113. * has already been forwarded.
  114. */
  115. if (ocelot->bridge_mask & BIT(info.port))
  116. skb->offload_fwd_mark = 1;
  117. skb->protocol = eth_type_trans(skb, dev);
  118. netif_rx(skb);
  119. dev->stats.rx_bytes += len;
  120. dev->stats.rx_packets++;
  121. } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
  122. if (err)
  123. while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
  124. ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  125. return IRQ_HANDLED;
  126. }
  127. static const struct of_device_id mscc_ocelot_match[] = {
  128. { .compatible = "mscc,vsc7514-switch" },
  129. { }
  130. };
  131. MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
  132. static int mscc_ocelot_probe(struct platform_device *pdev)
  133. {
  134. int err, irq;
  135. unsigned int i;
  136. struct device_node *np = pdev->dev.of_node;
  137. struct device_node *ports, *portnp;
  138. struct ocelot *ocelot;
  139. u32 val;
  140. struct {
  141. enum ocelot_target id;
  142. char *name;
  143. } res[] = {
  144. { SYS, "sys" },
  145. { REW, "rew" },
  146. { QSYS, "qsys" },
  147. { ANA, "ana" },
  148. { QS, "qs" },
  149. { HSIO, "hsio" },
  150. };
  151. if (!np && !pdev->dev.platform_data)
  152. return -ENODEV;
  153. ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
  154. if (!ocelot)
  155. return -ENOMEM;
  156. platform_set_drvdata(pdev, ocelot);
  157. ocelot->dev = &pdev->dev;
  158. for (i = 0; i < ARRAY_SIZE(res); i++) {
  159. struct regmap *target;
  160. target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
  161. if (IS_ERR(target))
  162. return PTR_ERR(target);
  163. ocelot->targets[res[i].id] = target;
  164. }
  165. err = ocelot_chip_init(ocelot);
  166. if (err)
  167. return err;
  168. irq = platform_get_irq_byname(pdev, "xtr");
  169. if (irq < 0)
  170. return -ENODEV;
  171. err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  172. ocelot_xtr_irq_handler, IRQF_ONESHOT,
  173. "frame extraction", ocelot);
  174. if (err)
  175. return err;
  176. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
  177. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
  178. do {
  179. msleep(1);
  180. regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
  181. &val);
  182. } while (val);
  183. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
  184. regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
  185. ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
  186. ports = of_get_child_by_name(np, "ethernet-ports");
  187. if (!ports) {
  188. dev_err(&pdev->dev, "no ethernet-ports child node found\n");
  189. return -ENODEV;
  190. }
  191. ocelot->num_phys_ports = of_get_child_count(ports);
  192. ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
  193. sizeof(struct ocelot_port *), GFP_KERNEL);
  194. INIT_LIST_HEAD(&ocelot->multicast);
  195. ocelot_init(ocelot);
  196. ocelot_rmw(ocelot, HSIO_HW_CFG_DEV1G_4_MODE |
  197. HSIO_HW_CFG_DEV1G_6_MODE |
  198. HSIO_HW_CFG_DEV1G_9_MODE,
  199. HSIO_HW_CFG_DEV1G_4_MODE |
  200. HSIO_HW_CFG_DEV1G_6_MODE |
  201. HSIO_HW_CFG_DEV1G_9_MODE,
  202. HSIO_HW_CFG);
  203. for_each_available_child_of_node(ports, portnp) {
  204. struct device_node *phy_node;
  205. struct phy_device *phy;
  206. struct resource *res;
  207. void __iomem *regs;
  208. char res_name[8];
  209. u32 port;
  210. if (of_property_read_u32(portnp, "reg", &port))
  211. continue;
  212. snprintf(res_name, sizeof(res_name), "port%d", port);
  213. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  214. res_name);
  215. regs = devm_ioremap_resource(&pdev->dev, res);
  216. if (IS_ERR(regs))
  217. continue;
  218. phy_node = of_parse_phandle(portnp, "phy-handle", 0);
  219. if (!phy_node)
  220. continue;
  221. phy = of_phy_find_device(phy_node);
  222. if (!phy)
  223. continue;
  224. err = ocelot_probe_port(ocelot, port, regs, phy);
  225. if (err) {
  226. dev_err(&pdev->dev, "failed to probe ports\n");
  227. goto err_probe_ports;
  228. }
  229. }
  230. register_netdevice_notifier(&ocelot_netdevice_nb);
  231. dev_info(&pdev->dev, "Ocelot switch probed\n");
  232. return 0;
  233. err_probe_ports:
  234. return err;
  235. }
  236. static int mscc_ocelot_remove(struct platform_device *pdev)
  237. {
  238. struct ocelot *ocelot = platform_get_drvdata(pdev);
  239. ocelot_deinit(ocelot);
  240. unregister_netdevice_notifier(&ocelot_netdevice_nb);
  241. return 0;
  242. }
  243. static struct platform_driver mscc_ocelot_driver = {
  244. .probe = mscc_ocelot_probe,
  245. .remove = mscc_ocelot_remove,
  246. .driver = {
  247. .name = "ocelot-switch",
  248. .of_match_table = mscc_ocelot_match,
  249. },
  250. };
  251. module_platform_driver(mscc_ocelot_driver);
  252. MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
  253. MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
  254. MODULE_LICENSE("Dual MIT/GPL");