intel_hdmi_audio.c 57 KB

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  1. /*
  2. * intel_hdmi_audio.c - Intel HDMI audio driver
  3. *
  4. * Copyright (C) 2016 Intel Corp
  5. * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
  6. * Ramesh Babu K V <ramesh.babu@intel.com>
  7. * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
  8. * Jerome Anand <jerome.anand@intel.com>
  9. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21. * ALSA driver for Intel HDMI audio
  22. */
  23. #include <linux/platform_device.h>
  24. #include <linux/io.h>
  25. #include <linux/slab.h>
  26. #include <linux/module.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/acpi.h>
  29. #include <asm/cacheflush.h>
  30. #include <sound/pcm.h>
  31. #include <sound/core.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/initval.h>
  34. #include <sound/control.h>
  35. #include <sound/initval.h>
  36. #include <drm/intel_lpe_audio.h>
  37. #include "intel_hdmi_audio.h"
  38. /*standard module options for ALSA. This module supports only one card*/
  39. static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
  40. static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
  41. module_param_named(index, hdmi_card_index, int, 0444);
  42. MODULE_PARM_DESC(index,
  43. "Index value for INTEL Intel HDMI Audio controller.");
  44. module_param_named(id, hdmi_card_id, charp, 0444);
  45. MODULE_PARM_DESC(id,
  46. "ID string for INTEL Intel HDMI Audio controller.");
  47. /*
  48. * ELD SA bits in the CEA Speaker Allocation data block
  49. */
  50. static const int eld_speaker_allocation_bits[] = {
  51. [0] = FL | FR,
  52. [1] = LFE,
  53. [2] = FC,
  54. [3] = RL | RR,
  55. [4] = RC,
  56. [5] = FLC | FRC,
  57. [6] = RLC | RRC,
  58. /* the following are not defined in ELD yet */
  59. [7] = 0,
  60. };
  61. /*
  62. * This is an ordered list!
  63. *
  64. * The preceding ones have better chances to be selected by
  65. * hdmi_channel_allocation().
  66. */
  67. static struct cea_channel_speaker_allocation channel_allocations[] = {
  68. /* channel: 7 6 5 4 3 2 1 0 */
  69. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  70. /* 2.1 */
  71. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  72. /* Dolby Surround */
  73. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  74. /* surround40 */
  75. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  76. /* surround41 */
  77. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  78. /* surround50 */
  79. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  80. /* surround51 */
  81. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  82. /* 6.1 */
  83. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  84. /* surround71 */
  85. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  86. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  87. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  88. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  89. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  90. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  91. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  92. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  93. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  94. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  95. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  96. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  97. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  98. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  99. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  100. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  101. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  102. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  103. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  104. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  105. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  106. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  107. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  108. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  109. };
  110. static const struct channel_map_table map_tables[] = {
  111. { SNDRV_CHMAP_FL, 0x00, FL },
  112. { SNDRV_CHMAP_FR, 0x01, FR },
  113. { SNDRV_CHMAP_RL, 0x04, RL },
  114. { SNDRV_CHMAP_RR, 0x05, RR },
  115. { SNDRV_CHMAP_LFE, 0x02, LFE },
  116. { SNDRV_CHMAP_FC, 0x03, FC },
  117. { SNDRV_CHMAP_RLC, 0x06, RLC },
  118. { SNDRV_CHMAP_RRC, 0x07, RRC },
  119. {} /* terminator */
  120. };
  121. /* hardware capability structure */
  122. static const struct snd_pcm_hardware snd_intel_hadstream = {
  123. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  124. SNDRV_PCM_INFO_DOUBLE |
  125. SNDRV_PCM_INFO_MMAP|
  126. SNDRV_PCM_INFO_MMAP_VALID |
  127. SNDRV_PCM_INFO_BATCH),
  128. .formats = (SNDRV_PCM_FMTBIT_S24 |
  129. SNDRV_PCM_FMTBIT_U24),
  130. .rates = SNDRV_PCM_RATE_32000 |
  131. SNDRV_PCM_RATE_44100 |
  132. SNDRV_PCM_RATE_48000 |
  133. SNDRV_PCM_RATE_88200 |
  134. SNDRV_PCM_RATE_96000 |
  135. SNDRV_PCM_RATE_176400 |
  136. SNDRV_PCM_RATE_192000,
  137. .rate_min = HAD_MIN_RATE,
  138. .rate_max = HAD_MAX_RATE,
  139. .channels_min = HAD_MIN_CHANNEL,
  140. .channels_max = HAD_MAX_CHANNEL,
  141. .buffer_bytes_max = HAD_MAX_BUFFER,
  142. .period_bytes_min = HAD_MIN_PERIOD_BYTES,
  143. .period_bytes_max = HAD_MAX_PERIOD_BYTES,
  144. .periods_min = HAD_MIN_PERIODS,
  145. .periods_max = HAD_MAX_PERIODS,
  146. .fifo_size = HAD_FIFO_SIZE,
  147. };
  148. /* Register access functions */
  149. static inline void
  150. mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
  151. {
  152. *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
  153. }
  154. static inline void
  155. mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
  156. {
  157. iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
  158. }
  159. static int had_read_register(struct snd_intelhad *intelhaddata,
  160. u32 offset, u32 *data)
  161. {
  162. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  163. return -ENODEV;
  164. mid_hdmi_audio_read(intelhaddata, offset, data);
  165. return 0;
  166. }
  167. static void fixup_dp_config(struct snd_intelhad *intelhaddata,
  168. u32 offset, u32 *data)
  169. {
  170. if (intelhaddata->dp_output) {
  171. if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
  172. *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
  173. }
  174. }
  175. static int had_write_register(struct snd_intelhad *intelhaddata,
  176. u32 offset, u32 data)
  177. {
  178. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  179. return -ENODEV;
  180. fixup_dp_config(intelhaddata, offset, &data);
  181. mid_hdmi_audio_write(intelhaddata, offset, data);
  182. return 0;
  183. }
  184. static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
  185. u32 data, u32 mask)
  186. {
  187. u32 val_tmp;
  188. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  189. return -ENODEV;
  190. mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
  191. val_tmp &= ~mask;
  192. val_tmp |= (data & mask);
  193. fixup_dp_config(intelhaddata, offset, &val_tmp);
  194. mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
  195. return 0;
  196. }
  197. /*
  198. * function to read-modify AUD_CONFIG register on VLV2.
  199. * The had_read_modify() function should not directly be used on VLV2 for
  200. * updating AUD_CONFIG register.
  201. * This is because:
  202. * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
  203. * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
  204. * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
  205. * register. This field should be 1xy binary for configuration with 6 or
  206. * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
  207. * causes the "channels" field to be updated as 0xy binary resulting in
  208. * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
  209. * appropriate value when doing read-modify of AUD_CONFIG register.
  210. *
  211. * @substream: the current substream or NULL if no active substream
  212. * @data : data to be written
  213. * @mask : mask
  214. *
  215. */
  216. static int had_read_modify_aud_config_v2(struct snd_intelhad *intelhaddata,
  217. u32 data, u32 mask)
  218. {
  219. struct snd_pcm_substream *substream;
  220. union aud_cfg cfg_val = {.cfg_regval = 0};
  221. u8 channels;
  222. /*
  223. * If substream is NULL, there is no active stream.
  224. * In this case just set channels to 2
  225. */
  226. substream = intelhaddata->stream_info.had_substream;
  227. if (substream && substream->runtime)
  228. channels = substream->runtime->channels;
  229. else
  230. channels = 2;
  231. cfg_val.cfg_regx.num_ch = channels - 2;
  232. data = data | cfg_val.cfg_regval;
  233. mask = mask | AUD_CONFIG_CH_MASK;
  234. dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n",
  235. __func__, data, mask);
  236. return had_read_modify(intelhaddata, AUD_CONFIG, data, mask);
  237. }
  238. static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
  239. {
  240. u32 status_reg;
  241. if (enable) {
  242. mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
  243. status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
  244. mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg);
  245. mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
  246. }
  247. }
  248. static void snd_intelhad_enable_audio(struct snd_intelhad *intelhaddata,
  249. bool enable)
  250. {
  251. had_read_modify_aud_config_v2(intelhaddata, enable ? BIT(0) : 0,
  252. BIT(0));
  253. }
  254. static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
  255. u8 reset)
  256. {
  257. had_write_register(intelhaddata, AUD_HDMI_STATUS, reset);
  258. }
  259. /*
  260. * initialize audio channel status registers
  261. * This function is called in the prepare callback
  262. */
  263. static int had_prog_status_reg(struct snd_pcm_substream *substream,
  264. struct snd_intelhad *intelhaddata)
  265. {
  266. union aud_cfg cfg_val = {.cfg_regval = 0};
  267. union aud_ch_status_0 ch_stat0 = {.status_0_regval = 0};
  268. union aud_ch_status_1 ch_stat1 = {.status_1_regval = 0};
  269. int format;
  270. ch_stat0.status_0_regx.lpcm_id = (intelhaddata->aes_bits &
  271. IEC958_AES0_NONAUDIO) >> 1;
  272. ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
  273. IEC958_AES3_CON_CLOCK) >> 4;
  274. cfg_val.cfg_regx.val_bit = ch_stat0.status_0_regx.lpcm_id;
  275. switch (substream->runtime->rate) {
  276. case AUD_SAMPLE_RATE_32:
  277. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_32KHZ;
  278. break;
  279. case AUD_SAMPLE_RATE_44_1:
  280. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_44KHZ;
  281. break;
  282. case AUD_SAMPLE_RATE_48:
  283. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_48KHZ;
  284. break;
  285. case AUD_SAMPLE_RATE_88_2:
  286. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_88KHZ;
  287. break;
  288. case AUD_SAMPLE_RATE_96:
  289. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_96KHZ;
  290. break;
  291. case AUD_SAMPLE_RATE_176_4:
  292. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_176KHZ;
  293. break;
  294. case AUD_SAMPLE_RATE_192:
  295. ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_192KHZ;
  296. break;
  297. default:
  298. /* control should never come here */
  299. return -EINVAL;
  300. }
  301. had_write_register(intelhaddata,
  302. AUD_CH_STATUS_0, ch_stat0.status_0_regval);
  303. format = substream->runtime->format;
  304. if (format == SNDRV_PCM_FORMAT_S16_LE) {
  305. ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_20;
  306. ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_16BITS;
  307. } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
  308. ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_24;
  309. ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_24BITS;
  310. } else {
  311. ch_stat1.status_1_regx.max_wrd_len = 0;
  312. ch_stat1.status_1_regx.wrd_len = 0;
  313. }
  314. had_write_register(intelhaddata,
  315. AUD_CH_STATUS_1, ch_stat1.status_1_regval);
  316. return 0;
  317. }
  318. /*
  319. * function to initialize audio
  320. * registers and buffer confgiuration registers
  321. * This function is called in the prepare callback
  322. */
  323. static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
  324. struct snd_intelhad *intelhaddata)
  325. {
  326. union aud_cfg cfg_val = {.cfg_regval = 0};
  327. union aud_buf_config buf_cfg = {.buf_cfgval = 0};
  328. u8 channels;
  329. had_prog_status_reg(substream, intelhaddata);
  330. buf_cfg.buf_cfg_regx.audio_fifo_watermark = FIFO_THRESHOLD;
  331. buf_cfg.buf_cfg_regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
  332. buf_cfg.buf_cfg_regx.aud_delay = 0;
  333. had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
  334. channels = substream->runtime->channels;
  335. cfg_val.cfg_regx.num_ch = channels - 2;
  336. if (channels <= 2)
  337. cfg_val.cfg_regx.layout = LAYOUT0;
  338. else
  339. cfg_val.cfg_regx.layout = LAYOUT1;
  340. cfg_val.cfg_regx.val_bit = 1;
  341. had_write_register(intelhaddata, AUD_CONFIG, cfg_val.cfg_regval);
  342. return 0;
  343. }
  344. /*
  345. * Compute derived values in channel_allocations[].
  346. */
  347. static void init_channel_allocations(void)
  348. {
  349. int i, j;
  350. struct cea_channel_speaker_allocation *p;
  351. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  352. p = channel_allocations + i;
  353. p->channels = 0;
  354. p->spk_mask = 0;
  355. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  356. if (p->speakers[j]) {
  357. p->channels++;
  358. p->spk_mask |= p->speakers[j];
  359. }
  360. }
  361. }
  362. /*
  363. * The transformation takes two steps:
  364. *
  365. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  366. * spk_mask => (channel_allocations[]) => ai->CA
  367. *
  368. * TODO: it could select the wrong CA from multiple candidates.
  369. */
  370. static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata,
  371. int channels)
  372. {
  373. int i;
  374. int ca = 0;
  375. int spk_mask = 0;
  376. /*
  377. * CA defaults to 0 for basic stereo audio
  378. */
  379. if (channels <= 2)
  380. return 0;
  381. /*
  382. * expand ELD's speaker allocation mask
  383. *
  384. * ELD tells the speaker mask in a compact(paired) form,
  385. * expand ELD's notions to match the ones used by Audio InfoFrame.
  386. */
  387. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  388. if (intelhaddata->eld.speaker_allocation_block & (1 << i))
  389. spk_mask |= eld_speaker_allocation_bits[i];
  390. }
  391. /* search for the first working match in the CA table */
  392. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  393. if (channels == channel_allocations[i].channels &&
  394. (spk_mask & channel_allocations[i].spk_mask) ==
  395. channel_allocations[i].spk_mask) {
  396. ca = channel_allocations[i].ca_index;
  397. break;
  398. }
  399. }
  400. dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
  401. return ca;
  402. }
  403. /* from speaker bit mask to ALSA API channel position */
  404. static int spk_to_chmap(int spk)
  405. {
  406. const struct channel_map_table *t = map_tables;
  407. for (; t->map; t++) {
  408. if (t->spk_mask == spk)
  409. return t->map;
  410. }
  411. return 0;
  412. }
  413. static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
  414. {
  415. int i, c;
  416. int spk_mask = 0;
  417. struct snd_pcm_chmap_elem *chmap;
  418. u8 eld_high, eld_high_mask = 0xF0;
  419. u8 high_msb;
  420. chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
  421. if (!chmap) {
  422. intelhaddata->chmap->chmap = NULL;
  423. return;
  424. }
  425. dev_dbg(intelhaddata->dev, "eld.speaker_allocation_block = %x\n",
  426. intelhaddata->eld.speaker_allocation_block);
  427. /* WA: Fix the max channel supported to 8 */
  428. /*
  429. * Sink may support more than 8 channels, if eld_high has more than
  430. * one bit set. SOC supports max 8 channels.
  431. * Refer eld_speaker_allocation_bits, for sink speaker allocation
  432. */
  433. /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
  434. eld_high = intelhaddata->eld.speaker_allocation_block & eld_high_mask;
  435. if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
  436. /* eld_high & (eld_high-1): if more than 1 bit set */
  437. /* 0x1F: 7 channels */
  438. for (i = 1; i < 4; i++) {
  439. high_msb = eld_high & (0x80 >> i);
  440. if (high_msb) {
  441. intelhaddata->eld.speaker_allocation_block &=
  442. high_msb | 0xF;
  443. break;
  444. }
  445. }
  446. }
  447. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  448. if (intelhaddata->eld.speaker_allocation_block & (1 << i))
  449. spk_mask |= eld_speaker_allocation_bits[i];
  450. }
  451. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  452. if (spk_mask == channel_allocations[i].spk_mask) {
  453. for (c = 0; c < channel_allocations[i].channels; c++) {
  454. chmap->map[c] = spk_to_chmap(
  455. channel_allocations[i].speakers[
  456. (MAX_SPEAKERS - 1) - c]);
  457. }
  458. chmap->channels = channel_allocations[i].channels;
  459. intelhaddata->chmap->chmap = chmap;
  460. break;
  461. }
  462. }
  463. if (i >= ARRAY_SIZE(channel_allocations)) {
  464. intelhaddata->chmap->chmap = NULL;
  465. kfree(chmap);
  466. }
  467. }
  468. /*
  469. * ALSA API channel-map control callbacks
  470. */
  471. static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  472. struct snd_ctl_elem_info *uinfo)
  473. {
  474. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  475. struct snd_intelhad *intelhaddata = info->private_data;
  476. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  477. return -ENODEV;
  478. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  479. uinfo->count = HAD_MAX_CHANNEL;
  480. uinfo->value.integer.min = 0;
  481. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  482. return 0;
  483. }
  484. static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  485. struct snd_ctl_elem_value *ucontrol)
  486. {
  487. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  488. struct snd_intelhad *intelhaddata = info->private_data;
  489. int i;
  490. const struct snd_pcm_chmap_elem *chmap;
  491. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  492. return -ENODEV;
  493. mutex_lock(&intelhaddata->mutex);
  494. if (!intelhaddata->chmap->chmap) {
  495. mutex_unlock(&intelhaddata->mutex);
  496. return -ENODATA;
  497. }
  498. chmap = intelhaddata->chmap->chmap;
  499. for (i = 0; i < chmap->channels; i++)
  500. ucontrol->value.integer.value[i] = chmap->map[i];
  501. mutex_unlock(&intelhaddata->mutex);
  502. return 0;
  503. }
  504. static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
  505. struct snd_pcm *pcm)
  506. {
  507. int err;
  508. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  509. NULL, 0, (unsigned long)intelhaddata,
  510. &intelhaddata->chmap);
  511. if (err < 0)
  512. return err;
  513. intelhaddata->chmap->private_data = intelhaddata;
  514. intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
  515. intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
  516. intelhaddata->chmap->chmap = NULL;
  517. return 0;
  518. }
  519. /*
  520. * snd_intelhad_prog_dip - to initialize Data Island Packets registers
  521. *
  522. * @substream:substream for which the prepare function is called
  523. * @intelhaddata:substream private data
  524. *
  525. * This function is called in the prepare callback
  526. */
  527. static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream,
  528. struct snd_intelhad *intelhaddata)
  529. {
  530. int i;
  531. union aud_ctrl_st ctrl_state = {.ctrl_val = 0};
  532. union aud_info_frame2 frame2 = {.fr2_val = 0};
  533. union aud_info_frame3 frame3 = {.fr3_val = 0};
  534. u8 checksum = 0;
  535. u32 info_frame;
  536. int channels;
  537. channels = substream->runtime->channels;
  538. had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
  539. if (intelhaddata->dp_output) {
  540. info_frame = DP_INFO_FRAME_WORD1;
  541. frame2.fr2_val = 1;
  542. } else {
  543. info_frame = HDMI_INFO_FRAME_WORD1;
  544. frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
  545. frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
  546. intelhaddata, channels);
  547. /* Calculte the byte wide checksum for all valid DIP words */
  548. for (i = 0; i < BYTES_PER_WORD; i++)
  549. checksum += (info_frame >> i*BITS_PER_BYTE) & MASK_BYTE0;
  550. for (i = 0; i < BYTES_PER_WORD; i++)
  551. checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
  552. for (i = 0; i < BYTES_PER_WORD; i++)
  553. checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
  554. frame2.fr2_regx.chksum = -(checksum);
  555. }
  556. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
  557. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.fr2_val);
  558. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.fr3_val);
  559. /* program remaining DIP words with zero */
  560. for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
  561. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
  562. ctrl_state.ctrl_regx.dip_freq = 1;
  563. ctrl_state.ctrl_regx.dip_en_sta = 1;
  564. had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
  565. }
  566. /*
  567. * snd_intelhad_prog_buffer - programs buffer address and length registers
  568. * @substream:substream for which the prepare function is called
  569. * @intelhaddata:substream private data
  570. *
  571. * This function programs ring buffer address and length into registers.
  572. */
  573. static int snd_intelhad_prog_buffer(struct snd_intelhad *intelhaddata,
  574. int start, int end)
  575. {
  576. u32 ring_buf_addr, ring_buf_size, period_bytes;
  577. u8 i, num_periods;
  578. struct snd_pcm_substream *substream;
  579. substream = intelhaddata->stream_info.had_substream;
  580. if (WARN_ON(!substream))
  581. return 0;
  582. ring_buf_addr = substream->runtime->dma_addr;
  583. ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
  584. intelhaddata->stream_info.ring_buf_size = ring_buf_size;
  585. period_bytes = frames_to_bytes(substream->runtime,
  586. substream->runtime->period_size);
  587. num_periods = substream->runtime->periods;
  588. /*
  589. * buffer addr should be 64 byte aligned, period bytes
  590. * will be used to calculate addr offset
  591. */
  592. period_bytes &= ~0x3F;
  593. /* Hardware supports MAX_PERIODS buffers */
  594. if (end >= HAD_MAX_PERIODS)
  595. return -EINVAL;
  596. for (i = start; i <= end; i++) {
  597. /* Program the buf registers with addr and len */
  598. intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
  599. (i * period_bytes);
  600. if (i < num_periods-1)
  601. intelhaddata->buf_info[i].buf_size = period_bytes;
  602. else
  603. intelhaddata->buf_info[i].buf_size = ring_buf_size -
  604. (i * period_bytes);
  605. had_write_register(intelhaddata,
  606. AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
  607. intelhaddata->buf_info[i].buf_addr |
  608. BIT(0) | BIT(1));
  609. had_write_register(intelhaddata,
  610. AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
  611. period_bytes);
  612. intelhaddata->buf_info[i].is_valid = true;
  613. }
  614. dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n",
  615. __func__, start, end,
  616. intelhaddata->buf_info[start].buf_addr,
  617. intelhaddata->buf_info[start].buf_size);
  618. intelhaddata->valid_buf_cnt = num_periods;
  619. return 0;
  620. }
  621. static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
  622. {
  623. int i, retval = 0;
  624. u32 len[4];
  625. for (i = 0; i < 4 ; i++) {
  626. had_read_register(intelhaddata,
  627. AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
  628. &len[i]);
  629. if (!len[i])
  630. retval++;
  631. }
  632. if (retval != 1) {
  633. for (i = 0; i < 4 ; i++)
  634. dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n",
  635. i, len[i]);
  636. }
  637. return retval;
  638. }
  639. static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
  640. {
  641. u32 maud_val;
  642. /* Select maud according to DP 1.2 spec */
  643. if (link_rate == DP_2_7_GHZ) {
  644. switch (aud_samp_freq) {
  645. case AUD_SAMPLE_RATE_32:
  646. maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
  647. break;
  648. case AUD_SAMPLE_RATE_44_1:
  649. maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
  650. break;
  651. case AUD_SAMPLE_RATE_48:
  652. maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
  653. break;
  654. case AUD_SAMPLE_RATE_88_2:
  655. maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
  656. break;
  657. case AUD_SAMPLE_RATE_96:
  658. maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
  659. break;
  660. case AUD_SAMPLE_RATE_176_4:
  661. maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
  662. break;
  663. case HAD_MAX_RATE:
  664. maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
  665. break;
  666. default:
  667. maud_val = -EINVAL;
  668. break;
  669. }
  670. } else if (link_rate == DP_1_62_GHZ) {
  671. switch (aud_samp_freq) {
  672. case AUD_SAMPLE_RATE_32:
  673. maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
  674. break;
  675. case AUD_SAMPLE_RATE_44_1:
  676. maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
  677. break;
  678. case AUD_SAMPLE_RATE_48:
  679. maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
  680. break;
  681. case AUD_SAMPLE_RATE_88_2:
  682. maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
  683. break;
  684. case AUD_SAMPLE_RATE_96:
  685. maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
  686. break;
  687. case AUD_SAMPLE_RATE_176_4:
  688. maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
  689. break;
  690. case HAD_MAX_RATE:
  691. maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
  692. break;
  693. default:
  694. maud_val = -EINVAL;
  695. break;
  696. }
  697. } else
  698. maud_val = -EINVAL;
  699. return maud_val;
  700. }
  701. /*
  702. * snd_intelhad_prog_cts - Program HDMI audio CTS value
  703. *
  704. * @aud_samp_freq: sampling frequency of audio data
  705. * @tmds: sampling frequency of the display data
  706. * @n_param: N value, depends on aud_samp_freq
  707. * @intelhaddata:substream private data
  708. *
  709. * Program CTS register based on the audio and display sampling frequency
  710. */
  711. static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds,
  712. u32 link_rate, u32 n_param,
  713. struct snd_intelhad *intelhaddata)
  714. {
  715. u32 cts_val;
  716. u64 dividend, divisor;
  717. if (intelhaddata->dp_output) {
  718. /* Substitute cts_val with Maud according to DP 1.2 spec*/
  719. cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
  720. } else {
  721. /* Calculate CTS according to HDMI 1.3a spec*/
  722. dividend = (u64)tmds * n_param*1000;
  723. divisor = 128 * aud_samp_freq;
  724. cts_val = div64_u64(dividend, divisor);
  725. }
  726. dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
  727. tmds, n_param, cts_val);
  728. had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
  729. }
  730. static int had_calculate_n_value(u32 aud_samp_freq)
  731. {
  732. int n_val;
  733. /* Select N according to HDMI 1.3a spec*/
  734. switch (aud_samp_freq) {
  735. case AUD_SAMPLE_RATE_32:
  736. n_val = 4096;
  737. break;
  738. case AUD_SAMPLE_RATE_44_1:
  739. n_val = 6272;
  740. break;
  741. case AUD_SAMPLE_RATE_48:
  742. n_val = 6144;
  743. break;
  744. case AUD_SAMPLE_RATE_88_2:
  745. n_val = 12544;
  746. break;
  747. case AUD_SAMPLE_RATE_96:
  748. n_val = 12288;
  749. break;
  750. case AUD_SAMPLE_RATE_176_4:
  751. n_val = 25088;
  752. break;
  753. case HAD_MAX_RATE:
  754. n_val = 24576;
  755. break;
  756. default:
  757. n_val = -EINVAL;
  758. break;
  759. }
  760. return n_val;
  761. }
  762. /*
  763. * snd_intelhad_prog_n - Program HDMI audio N value
  764. *
  765. * @aud_samp_freq: sampling frequency of audio data
  766. * @n_param: N value, depends on aud_samp_freq
  767. * @intelhaddata:substream private data
  768. *
  769. * This function is called in the prepare callback.
  770. * It programs based on the audio and display sampling frequency
  771. */
  772. static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param,
  773. struct snd_intelhad *intelhaddata)
  774. {
  775. int n_val;
  776. if (intelhaddata->dp_output) {
  777. /*
  778. * According to DP specs, Maud and Naud values hold
  779. * a relationship, which is stated as:
  780. * Maud/Naud = 512 * fs / f_LS_Clk
  781. * where, fs is the sampling frequency of the audio stream
  782. * and Naud is 32768 for Async clock.
  783. */
  784. n_val = DP_NAUD_VAL;
  785. } else
  786. n_val = had_calculate_n_value(aud_samp_freq);
  787. if (n_val < 0)
  788. return n_val;
  789. had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
  790. *n_param = n_val;
  791. return 0;
  792. }
  793. static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
  794. {
  795. u32 hdmi_status = 0, i = 0;
  796. /* Handle Underrun interrupt within Audio Unit */
  797. had_write_register(intelhaddata, AUD_CONFIG, 0);
  798. /* Reset buffer pointers */
  799. had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
  800. had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
  801. /*
  802. * The interrupt status 'sticky' bits might not be cleared by
  803. * setting '1' to that bit once...
  804. */
  805. do { /* clear bit30, 31 AUD_HDMI_STATUS */
  806. had_read_register(intelhaddata, AUD_HDMI_STATUS,
  807. &hdmi_status);
  808. dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
  809. if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
  810. i++;
  811. had_write_register(intelhaddata,
  812. AUD_HDMI_STATUS, hdmi_status);
  813. } else
  814. break;
  815. } while (i < MAX_CNT);
  816. if (i >= MAX_CNT)
  817. dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
  818. }
  819. /*
  820. * snd_intelhad_open - stream initializations are done here
  821. * @substream:substream for which the stream function is called
  822. *
  823. * This function is called whenever a PCM stream is opened
  824. */
  825. static int snd_intelhad_open(struct snd_pcm_substream *substream)
  826. {
  827. struct snd_intelhad *intelhaddata;
  828. struct snd_pcm_runtime *runtime;
  829. struct had_stream_data *had_stream;
  830. int retval;
  831. intelhaddata = snd_pcm_substream_chip(substream);
  832. had_stream = &intelhaddata->stream_data;
  833. runtime = substream->runtime;
  834. intelhaddata->underrun_count = 0;
  835. pm_runtime_get(intelhaddata->dev);
  836. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  837. dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
  838. __func__);
  839. retval = -ENODEV;
  840. goto error;
  841. }
  842. /* set the runtime hw parameter with local snd_pcm_hardware struct */
  843. runtime->hw = snd_intel_hadstream;
  844. retval = snd_pcm_hw_constraint_integer(runtime,
  845. SNDRV_PCM_HW_PARAM_PERIODS);
  846. if (retval < 0)
  847. goto error;
  848. /* Make sure, that the period size is always aligned
  849. * 64byte boundary
  850. */
  851. retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
  852. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
  853. if (retval < 0) {
  854. dev_dbg(intelhaddata->dev, "%s:step_size=64 failed,err=%d\n",
  855. __func__, retval);
  856. goto error;
  857. }
  858. return retval;
  859. error:
  860. pm_runtime_put(intelhaddata->dev);
  861. return retval;
  862. }
  863. /*
  864. * had_period_elapsed - updates the hardware pointer status
  865. * @had_substream: substream for which the stream function is called
  866. */
  867. static void had_period_elapsed(struct snd_pcm_substream *substream)
  868. {
  869. if (!substream || !substream->runtime)
  870. return;
  871. snd_pcm_period_elapsed(substream);
  872. }
  873. /*
  874. * snd_intelhad_close - to free parameteres when stream is stopped
  875. * @substream: substream for which the function is called
  876. *
  877. * This function is called by ALSA framework when stream is stopped
  878. */
  879. static int snd_intelhad_close(struct snd_pcm_substream *substream)
  880. {
  881. struct snd_intelhad *intelhaddata;
  882. intelhaddata = snd_pcm_substream_chip(substream);
  883. intelhaddata->stream_info.buffer_rendered = 0;
  884. intelhaddata->stream_info.buffer_ptr = 0;
  885. intelhaddata->stream_info.str_id = 0;
  886. intelhaddata->stream_info.had_substream = NULL;
  887. /* Check if following drv_status modification is required - VA */
  888. if (intelhaddata->drv_status != HAD_DRV_DISCONNECTED) {
  889. intelhaddata->drv_status = HAD_DRV_CONNECTED;
  890. dev_dbg(intelhaddata->dev,
  891. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
  892. __func__, __LINE__);
  893. }
  894. pm_runtime_put(intelhaddata->dev);
  895. return 0;
  896. }
  897. /*
  898. * snd_intelhad_hw_params - to setup the hardware parameters
  899. * like allocating the buffers
  900. * @substream: substream for which the function is called
  901. * @hw_params: hardware parameters
  902. *
  903. * This function is called by ALSA framework when hardware params are set
  904. */
  905. static int snd_intelhad_hw_params(struct snd_pcm_substream *substream,
  906. struct snd_pcm_hw_params *hw_params)
  907. {
  908. struct snd_intelhad *intelhaddata;
  909. unsigned long addr;
  910. int pages, buf_size, retval;
  911. if (!hw_params)
  912. return -EINVAL;
  913. intelhaddata = snd_pcm_substream_chip(substream);
  914. buf_size = params_buffer_bytes(hw_params);
  915. retval = snd_pcm_lib_malloc_pages(substream, buf_size);
  916. if (retval < 0)
  917. return retval;
  918. dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
  919. __func__, buf_size);
  920. /* mark the pages as uncached region */
  921. addr = (unsigned long) substream->runtime->dma_area;
  922. pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
  923. retval = set_memory_uc(addr, pages);
  924. if (retval) {
  925. dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
  926. retval);
  927. return retval;
  928. }
  929. memset(substream->runtime->dma_area, 0, buf_size);
  930. return retval;
  931. }
  932. /*
  933. * snd_intelhad_hw_free - to release the resources allocated during
  934. * hardware params setup
  935. * @substream: substream for which the function is called
  936. *
  937. * This function is called by ALSA framework before close callback.
  938. */
  939. static int snd_intelhad_hw_free(struct snd_pcm_substream *substream)
  940. {
  941. unsigned long addr;
  942. u32 pages;
  943. /* mark back the pages as cached/writeback region before the free */
  944. if (substream->runtime->dma_area != NULL) {
  945. addr = (unsigned long) substream->runtime->dma_area;
  946. pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
  947. PAGE_SIZE;
  948. set_memory_wb(addr, pages);
  949. return snd_pcm_lib_free_pages(substream);
  950. }
  951. return 0;
  952. }
  953. /*
  954. * snd_intelhad_pcm_trigger - stream activities are handled here
  955. * @substream: substream for which the stream function is called
  956. * @cmd: the stream commamd thats requested from upper layer
  957. *
  958. * This function is called whenever an a stream activity is invoked
  959. */
  960. static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream,
  961. int cmd)
  962. {
  963. int retval = 0;
  964. struct snd_intelhad *intelhaddata;
  965. struct had_stream_data *had_stream;
  966. intelhaddata = snd_pcm_substream_chip(substream);
  967. had_stream = &intelhaddata->stream_data;
  968. switch (cmd) {
  969. case SNDRV_PCM_TRIGGER_START:
  970. /* Disable local INTRs till register prgmng is done */
  971. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  972. dev_dbg(intelhaddata->dev,
  973. "_START: HDMI cable plugged-out\n");
  974. retval = -ENODEV;
  975. break;
  976. }
  977. had_stream->stream_type = HAD_RUNNING_STREAM;
  978. /* Enable Audio */
  979. snd_intelhad_enable_audio_int(intelhaddata, true);
  980. snd_intelhad_enable_audio(intelhaddata, true);
  981. break;
  982. case SNDRV_PCM_TRIGGER_STOP:
  983. spin_lock(&intelhaddata->had_spinlock);
  984. intelhaddata->stream_info.str_id = 0;
  985. intelhaddata->curr_buf = 0;
  986. /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
  987. had_stream->stream_type = HAD_INIT;
  988. spin_unlock(&intelhaddata->had_spinlock);
  989. /* Disable Audio */
  990. snd_intelhad_enable_audio_int(intelhaddata, false);
  991. snd_intelhad_enable_audio(intelhaddata, false);
  992. /* Reset buffer pointers */
  993. snd_intelhad_reset_audio(intelhaddata, 1);
  994. snd_intelhad_reset_audio(intelhaddata, 0);
  995. snd_intelhad_enable_audio_int(intelhaddata, false);
  996. break;
  997. default:
  998. retval = -EINVAL;
  999. }
  1000. return retval;
  1001. }
  1002. /*
  1003. * snd_intelhad_pcm_prepare - internal preparation before starting a stream
  1004. * @substream: substream for which the function is called
  1005. *
  1006. * This function is called when a stream is started for internal preparation.
  1007. */
  1008. static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
  1009. {
  1010. int retval;
  1011. u32 disp_samp_freq, n_param;
  1012. u32 link_rate = 0;
  1013. struct snd_intelhad *intelhaddata;
  1014. struct snd_pcm_runtime *runtime;
  1015. struct had_stream_data *had_stream;
  1016. intelhaddata = snd_pcm_substream_chip(substream);
  1017. runtime = substream->runtime;
  1018. had_stream = &intelhaddata->stream_data;
  1019. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1020. dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
  1021. __func__);
  1022. retval = -ENODEV;
  1023. goto prep_end;
  1024. }
  1025. dev_dbg(intelhaddata->dev, "period_size=%d\n",
  1026. (int)frames_to_bytes(runtime, runtime->period_size));
  1027. dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
  1028. dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
  1029. (int)snd_pcm_lib_buffer_bytes(substream));
  1030. dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
  1031. dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
  1032. if (intelhaddata->stream_info.str_id) {
  1033. dev_dbg(intelhaddata->dev,
  1034. "_prepare is called for existing str_id#%d\n",
  1035. intelhaddata->stream_info.str_id);
  1036. retval = snd_intelhad_pcm_trigger(substream,
  1037. SNDRV_PCM_TRIGGER_STOP);
  1038. return retval;
  1039. }
  1040. intelhaddata->stream_info.had_substream = substream;
  1041. intelhaddata->stream_info.buffer_ptr = 0;
  1042. intelhaddata->stream_info.buffer_rendered = 0;
  1043. intelhaddata->stream_info.sfreq = substream->runtime->rate;
  1044. /* Get N value in KHz */
  1045. disp_samp_freq = intelhaddata->tmds_clock_speed;
  1046. retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
  1047. intelhaddata);
  1048. if (retval) {
  1049. dev_err(intelhaddata->dev,
  1050. "programming N value failed %#x\n", retval);
  1051. goto prep_end;
  1052. }
  1053. if (intelhaddata->dp_output)
  1054. link_rate = intelhaddata->link_rate;
  1055. snd_intelhad_prog_cts(substream->runtime->rate,
  1056. disp_samp_freq, link_rate,
  1057. n_param, intelhaddata);
  1058. snd_intelhad_prog_dip(substream, intelhaddata);
  1059. retval = snd_intelhad_audio_ctrl(substream, intelhaddata);
  1060. /* Prog buffer address */
  1061. retval = snd_intelhad_prog_buffer(intelhaddata,
  1062. HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
  1063. /*
  1064. * Program channel mapping in following order:
  1065. * FL, FR, C, LFE, RL, RR
  1066. */
  1067. had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
  1068. prep_end:
  1069. return retval;
  1070. }
  1071. /*
  1072. * snd_intelhad_pcm_pointer- to send the current buffer pointerprocessed by hw
  1073. * @substream: substream for which the function is called
  1074. *
  1075. * This function is called by ALSA framework to get the current hw buffer ptr
  1076. * when a period is elapsed
  1077. */
  1078. static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
  1079. struct snd_pcm_substream *substream)
  1080. {
  1081. struct snd_intelhad *intelhaddata;
  1082. u32 bytes_rendered = 0;
  1083. u32 t;
  1084. int buf_id;
  1085. intelhaddata = snd_pcm_substream_chip(substream);
  1086. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
  1087. return SNDRV_PCM_POS_XRUN;
  1088. /* Use a hw register to calculate sub-period position reports.
  1089. * This makes PulseAudio happier.
  1090. */
  1091. buf_id = intelhaddata->curr_buf % 4;
  1092. had_read_register(intelhaddata,
  1093. AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
  1094. if ((t == 0) || (t == ((u32)-1L))) {
  1095. intelhaddata->underrun_count++;
  1096. dev_dbg(intelhaddata->dev,
  1097. "discovered buffer done for buf %d, count = %d\n",
  1098. buf_id, intelhaddata->underrun_count);
  1099. if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
  1100. dev_dbg(intelhaddata->dev,
  1101. "assume audio_codec_reset, underrun = %d - do xrun\n",
  1102. intelhaddata->underrun_count);
  1103. intelhaddata->underrun_count = 0;
  1104. return SNDRV_PCM_POS_XRUN;
  1105. }
  1106. } else {
  1107. /* Reset Counter */
  1108. intelhaddata->underrun_count = 0;
  1109. }
  1110. t = intelhaddata->buf_info[buf_id].buf_size - t;
  1111. if (intelhaddata->stream_info.buffer_rendered)
  1112. div_u64_rem(intelhaddata->stream_info.buffer_rendered,
  1113. intelhaddata->stream_info.ring_buf_size,
  1114. &(bytes_rendered));
  1115. intelhaddata->stream_info.buffer_ptr = bytes_to_frames(
  1116. substream->runtime,
  1117. bytes_rendered + t);
  1118. return intelhaddata->stream_info.buffer_ptr;
  1119. }
  1120. /*
  1121. * snd_intelhad_pcm_mmap- mmaps a kernel buffer to user space for copying data
  1122. * @substream: substream for which the function is called
  1123. * @vma: struct instance of memory VMM memory area
  1124. *
  1125. * This function is called by OS when a user space component
  1126. * tries to get mmap memory from driver
  1127. */
  1128. static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream,
  1129. struct vm_area_struct *vma)
  1130. {
  1131. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1132. return remap_pfn_range(vma, vma->vm_start,
  1133. substream->dma_buffer.addr >> PAGE_SHIFT,
  1134. vma->vm_end - vma->vm_start, vma->vm_page_prot);
  1135. }
  1136. /* process mode change of the running stream; called in mutex */
  1137. static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata)
  1138. {
  1139. struct snd_pcm_substream *substream;
  1140. int retval = 0;
  1141. u32 disp_samp_freq, n_param;
  1142. u32 link_rate = 0;
  1143. substream = intelhaddata->stream_info.had_substream;
  1144. if (!substream || !substream->runtime)
  1145. return 0;
  1146. /* Disable Audio */
  1147. snd_intelhad_enable_audio(intelhaddata, false);
  1148. /* Update CTS value */
  1149. disp_samp_freq = intelhaddata->tmds_clock_speed;
  1150. retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
  1151. intelhaddata);
  1152. if (retval) {
  1153. dev_err(intelhaddata->dev,
  1154. "programming N value failed %#x\n", retval);
  1155. goto out;
  1156. }
  1157. if (intelhaddata->dp_output)
  1158. link_rate = intelhaddata->link_rate;
  1159. snd_intelhad_prog_cts(substream->runtime->rate,
  1160. disp_samp_freq, link_rate,
  1161. n_param, intelhaddata);
  1162. /* Enable Audio */
  1163. snd_intelhad_enable_audio(intelhaddata, true);
  1164. out:
  1165. return retval;
  1166. }
  1167. /*
  1168. * hdmi_lpe_audio_suspend - power management suspend function
  1169. * @pdev: platform device
  1170. *
  1171. * This function is called to suspend the hdmi audio.
  1172. */
  1173. static int hdmi_lpe_audio_suspend(struct platform_device *pdev,
  1174. pm_message_t state)
  1175. {
  1176. struct had_stream_data *had_stream;
  1177. struct snd_pcm_substream *substream;
  1178. struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
  1179. had_stream = &intelhaddata->stream_data;
  1180. substream = intelhaddata->stream_info.had_substream;
  1181. if (!pm_runtime_status_suspended(intelhaddata->dev)) {
  1182. dev_err(intelhaddata->dev, "audio stream is active\n");
  1183. return -EAGAIN;
  1184. }
  1185. spin_lock_irq(&intelhaddata->had_spinlock);
  1186. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1187. spin_unlock_irq(&intelhaddata->had_spinlock);
  1188. dev_dbg(intelhaddata->dev, "had not connected\n");
  1189. return 0;
  1190. }
  1191. if (intelhaddata->drv_status == HAD_DRV_SUSPENDED) {
  1192. spin_unlock_irq(&intelhaddata->had_spinlock);
  1193. dev_dbg(intelhaddata->dev, "had already suspended\n");
  1194. return 0;
  1195. }
  1196. intelhaddata->drv_status = HAD_DRV_SUSPENDED;
  1197. dev_dbg(intelhaddata->dev,
  1198. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_SUSPENDED\n",
  1199. __func__, __LINE__);
  1200. spin_unlock_irq(&intelhaddata->had_spinlock);
  1201. snd_intelhad_enable_audio_int(intelhaddata, false);
  1202. return 0;
  1203. }
  1204. /*
  1205. * hdmi_lpe_audio_resume - power management resume function
  1206. * @pdev: platform device
  1207. *
  1208. * This function is called to resume the hdmi audio.
  1209. */
  1210. static int hdmi_lpe_audio_resume(struct platform_device *pdev)
  1211. {
  1212. struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
  1213. spin_lock_irq(&intelhaddata->had_spinlock);
  1214. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1215. spin_unlock_irq(&intelhaddata->had_spinlock);
  1216. dev_dbg(intelhaddata->dev, "had not connected\n");
  1217. return 0;
  1218. }
  1219. if (intelhaddata->drv_status != HAD_DRV_SUSPENDED) {
  1220. spin_unlock_irq(&intelhaddata->had_spinlock);
  1221. dev_dbg(intelhaddata->dev, "had is not in suspended state\n");
  1222. return 0;
  1223. }
  1224. intelhaddata->drv_status = HAD_DRV_CONNECTED;
  1225. dev_dbg(intelhaddata->dev,
  1226. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
  1227. __func__, __LINE__);
  1228. spin_unlock_irq(&intelhaddata->had_spinlock);
  1229. snd_intelhad_enable_audio_int(intelhaddata, true);
  1230. return 0;
  1231. }
  1232. static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata,
  1233. enum intel_had_aud_buf_type buf_id)
  1234. {
  1235. int i, intr_count = 0;
  1236. enum intel_had_aud_buf_type buff_done;
  1237. u32 buf_size, buf_addr;
  1238. struct had_stream_data *had_stream;
  1239. had_stream = &intelhaddata->stream_data;
  1240. buff_done = buf_id;
  1241. intr_count = snd_intelhad_read_len(intelhaddata);
  1242. if (intr_count > 1) {
  1243. /* In case of active playback */
  1244. dev_err(intelhaddata->dev,
  1245. "Driver detected %d missed buffer done interrupt(s)\n",
  1246. (intr_count - 1));
  1247. if (intr_count > 3)
  1248. return intr_count;
  1249. buf_id += (intr_count - 1);
  1250. /* Reprogram registers*/
  1251. for (i = buff_done; i < buf_id; i++) {
  1252. int j = i % 4;
  1253. buf_size = intelhaddata->buf_info[j].buf_size;
  1254. buf_addr = intelhaddata->buf_info[j].buf_addr;
  1255. had_write_register(intelhaddata,
  1256. AUD_BUF_A_LENGTH +
  1257. (j * HAD_REG_WIDTH), buf_size);
  1258. had_write_register(intelhaddata,
  1259. AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH),
  1260. (buf_addr | BIT(0) | BIT(1)));
  1261. }
  1262. buf_id = buf_id % 4;
  1263. intelhaddata->buff_done = buf_id;
  1264. }
  1265. return intr_count;
  1266. }
  1267. /* called from irq handler */
  1268. static int had_process_buffer_done(struct snd_intelhad *intelhaddata)
  1269. {
  1270. u32 len = 1;
  1271. enum intel_had_aud_buf_type buf_id;
  1272. enum intel_had_aud_buf_type buff_done;
  1273. struct pcm_stream_info *stream;
  1274. u32 buf_size;
  1275. struct had_stream_data *had_stream;
  1276. int intr_count;
  1277. enum had_status_stream stream_type;
  1278. unsigned long flags;
  1279. had_stream = &intelhaddata->stream_data;
  1280. stream = &intelhaddata->stream_info;
  1281. intr_count = 1;
  1282. spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
  1283. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1284. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  1285. dev_dbg(intelhaddata->dev,
  1286. "%s:Device already disconnected\n", __func__);
  1287. return 0;
  1288. }
  1289. buf_id = intelhaddata->curr_buf;
  1290. intelhaddata->buff_done = buf_id;
  1291. buff_done = intelhaddata->buff_done;
  1292. buf_size = intelhaddata->buf_info[buf_id].buf_size;
  1293. stream_type = had_stream->stream_type;
  1294. /* Every debug statement has an implication
  1295. * of ~5msec. Thus, avoid having >3 debug statements
  1296. * for each buffer_done handling.
  1297. */
  1298. /* Check for any intr_miss in case of active playback */
  1299. if (had_stream->stream_type == HAD_RUNNING_STREAM) {
  1300. intr_count = had_chk_intrmiss(intelhaddata, buf_id);
  1301. if (!intr_count || (intr_count > 3)) {
  1302. spin_unlock_irqrestore(&intelhaddata->had_spinlock,
  1303. flags);
  1304. dev_err(intelhaddata->dev,
  1305. "HAD SW state in non-recoverable mode\n");
  1306. return 0;
  1307. }
  1308. buf_id += (intr_count - 1);
  1309. buf_id = buf_id % 4;
  1310. }
  1311. intelhaddata->buf_info[buf_id].is_valid = true;
  1312. if (intelhaddata->valid_buf_cnt-1 == buf_id) {
  1313. if (had_stream->stream_type >= HAD_RUNNING_STREAM)
  1314. intelhaddata->curr_buf = HAD_BUF_TYPE_A;
  1315. } else
  1316. intelhaddata->curr_buf = buf_id + 1;
  1317. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  1318. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1319. dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n");
  1320. return 0;
  1321. }
  1322. /* Reprogram the registers with addr and length */
  1323. had_write_register(intelhaddata,
  1324. AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
  1325. buf_size);
  1326. had_write_register(intelhaddata,
  1327. AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH),
  1328. intelhaddata->buf_info[buf_id].buf_addr |
  1329. BIT(0) | BIT(1));
  1330. had_read_register(intelhaddata,
  1331. AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
  1332. &len);
  1333. dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id);
  1334. /* In case of actual data,
  1335. * report buffer_done to above ALSA layer
  1336. */
  1337. buf_size = intelhaddata->buf_info[buf_id].buf_size;
  1338. if (stream_type >= HAD_RUNNING_STREAM) {
  1339. intelhaddata->stream_info.buffer_rendered +=
  1340. (intr_count * buf_size);
  1341. had_period_elapsed(stream->had_substream);
  1342. }
  1343. return 0;
  1344. }
  1345. /* called from irq handler */
  1346. static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
  1347. {
  1348. enum intel_had_aud_buf_type buf_id;
  1349. struct pcm_stream_info *stream;
  1350. struct had_stream_data *had_stream;
  1351. enum had_status_stream stream_type;
  1352. unsigned long flags;
  1353. int drv_status;
  1354. had_stream = &intelhaddata->stream_data;
  1355. stream = &intelhaddata->stream_info;
  1356. spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
  1357. buf_id = intelhaddata->curr_buf;
  1358. stream_type = had_stream->stream_type;
  1359. intelhaddata->buff_done = buf_id;
  1360. drv_status = intelhaddata->drv_status;
  1361. if (stream_type == HAD_RUNNING_STREAM)
  1362. intelhaddata->curr_buf = HAD_BUF_TYPE_A;
  1363. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  1364. dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_type=%d\n",
  1365. __func__, buf_id, stream_type);
  1366. snd_intelhad_handle_underrun(intelhaddata);
  1367. if (drv_status == HAD_DRV_DISCONNECTED) {
  1368. dev_dbg(intelhaddata->dev,
  1369. "%s:Device already disconnected\n", __func__);
  1370. return 0;
  1371. }
  1372. if (stream_type == HAD_RUNNING_STREAM) {
  1373. /* Report UNDERRUN error to above layers */
  1374. snd_pcm_stop_xrun(stream->had_substream);
  1375. }
  1376. return 0;
  1377. }
  1378. /* process hot plug, called from wq with mutex locked */
  1379. static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
  1380. {
  1381. enum intel_had_aud_buf_type buf_id;
  1382. struct snd_pcm_substream *substream;
  1383. struct had_stream_data *had_stream;
  1384. substream = intelhaddata->stream_info.had_substream;
  1385. had_stream = &intelhaddata->stream_data;
  1386. spin_lock_irq(&intelhaddata->had_spinlock);
  1387. if (intelhaddata->drv_status == HAD_DRV_CONNECTED) {
  1388. dev_dbg(intelhaddata->dev, "Device already connected\n");
  1389. spin_unlock_irq(&intelhaddata->had_spinlock);
  1390. return;
  1391. }
  1392. buf_id = intelhaddata->curr_buf;
  1393. intelhaddata->buff_done = buf_id;
  1394. intelhaddata->drv_status = HAD_DRV_CONNECTED;
  1395. dev_dbg(intelhaddata->dev,
  1396. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
  1397. __func__, __LINE__);
  1398. spin_unlock_irq(&intelhaddata->had_spinlock);
  1399. dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n",
  1400. buf_id);
  1401. /* Safety check */
  1402. if (substream) {
  1403. dev_dbg(intelhaddata->dev,
  1404. "Force to stop the active stream by disconnection\n");
  1405. /* Set runtime->state to hw_params done */
  1406. snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
  1407. }
  1408. had_build_channel_allocation_map(intelhaddata);
  1409. }
  1410. /* process hot unplug, called from wq with mutex locked */
  1411. static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
  1412. {
  1413. enum intel_had_aud_buf_type buf_id;
  1414. struct had_stream_data *had_stream;
  1415. had_stream = &intelhaddata->stream_data;
  1416. buf_id = intelhaddata->curr_buf;
  1417. spin_lock_irq(&intelhaddata->had_spinlock);
  1418. if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
  1419. dev_dbg(intelhaddata->dev, "Device already disconnected\n");
  1420. spin_unlock_irq(&intelhaddata->had_spinlock);
  1421. return;
  1422. }
  1423. /* Disable Audio */
  1424. snd_intelhad_enable_audio_int(intelhaddata, false);
  1425. snd_intelhad_enable_audio(intelhaddata, false);
  1426. intelhaddata->drv_status = HAD_DRV_DISCONNECTED;
  1427. dev_dbg(intelhaddata->dev,
  1428. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
  1429. __func__, __LINE__);
  1430. /* Report to above ALSA layer */
  1431. if (intelhaddata->stream_info.had_substream != NULL) {
  1432. spin_unlock_irq(&intelhaddata->had_spinlock);
  1433. snd_pcm_stop(intelhaddata->stream_info.had_substream,
  1434. SNDRV_PCM_STATE_SETUP);
  1435. spin_lock_irq(&intelhaddata->had_spinlock);
  1436. }
  1437. had_stream->stream_type = HAD_INIT;
  1438. spin_unlock_irq(&intelhaddata->had_spinlock);
  1439. kfree(intelhaddata->chmap->chmap);
  1440. intelhaddata->chmap->chmap = NULL;
  1441. }
  1442. /* PCM operations structure and the calls back for the same */
  1443. static struct snd_pcm_ops snd_intelhad_playback_ops = {
  1444. .open = snd_intelhad_open,
  1445. .close = snd_intelhad_close,
  1446. .ioctl = snd_pcm_lib_ioctl,
  1447. .hw_params = snd_intelhad_hw_params,
  1448. .hw_free = snd_intelhad_hw_free,
  1449. .prepare = snd_intelhad_pcm_prepare,
  1450. .trigger = snd_intelhad_pcm_trigger,
  1451. .pointer = snd_intelhad_pcm_pointer,
  1452. .mmap = snd_intelhad_pcm_mmap,
  1453. };
  1454. static int had_iec958_info(struct snd_kcontrol *kcontrol,
  1455. struct snd_ctl_elem_info *uinfo)
  1456. {
  1457. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1458. uinfo->count = 1;
  1459. return 0;
  1460. }
  1461. static int had_iec958_get(struct snd_kcontrol *kcontrol,
  1462. struct snd_ctl_elem_value *ucontrol)
  1463. {
  1464. struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
  1465. mutex_lock(&intelhaddata->mutex);
  1466. ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
  1467. ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
  1468. ucontrol->value.iec958.status[2] =
  1469. (intelhaddata->aes_bits >> 16) & 0xff;
  1470. ucontrol->value.iec958.status[3] =
  1471. (intelhaddata->aes_bits >> 24) & 0xff;
  1472. mutex_unlock(&intelhaddata->mutex);
  1473. return 0;
  1474. }
  1475. static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
  1476. struct snd_ctl_elem_value *ucontrol)
  1477. {
  1478. ucontrol->value.iec958.status[0] = 0xff;
  1479. ucontrol->value.iec958.status[1] = 0xff;
  1480. ucontrol->value.iec958.status[2] = 0xff;
  1481. ucontrol->value.iec958.status[3] = 0xff;
  1482. return 0;
  1483. }
  1484. static int had_iec958_put(struct snd_kcontrol *kcontrol,
  1485. struct snd_ctl_elem_value *ucontrol)
  1486. {
  1487. unsigned int val;
  1488. struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
  1489. int changed = 0;
  1490. val = (ucontrol->value.iec958.status[0] << 0) |
  1491. (ucontrol->value.iec958.status[1] << 8) |
  1492. (ucontrol->value.iec958.status[2] << 16) |
  1493. (ucontrol->value.iec958.status[3] << 24);
  1494. mutex_lock(&intelhaddata->mutex);
  1495. if (intelhaddata->aes_bits != val) {
  1496. intelhaddata->aes_bits = val;
  1497. changed = 1;
  1498. }
  1499. mutex_unlock(&intelhaddata->mutex);
  1500. return changed;
  1501. }
  1502. static struct snd_kcontrol_new had_control_iec958_mask = {
  1503. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1504. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1505. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
  1506. .info = had_iec958_info, /* shared */
  1507. .get = had_iec958_mask_get,
  1508. };
  1509. static struct snd_kcontrol_new had_control_iec958 = {
  1510. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1511. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1512. .info = had_iec958_info,
  1513. .get = had_iec958_get,
  1514. .put = had_iec958_put
  1515. };
  1516. static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
  1517. {
  1518. struct snd_intelhad *ctx = dev_id;
  1519. u32 audio_stat, audio_reg;
  1520. audio_reg = AUD_HDMI_STATUS;
  1521. mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
  1522. if (audio_stat & HDMI_AUDIO_UNDERRUN) {
  1523. mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
  1524. had_process_buffer_underrun(ctx);
  1525. }
  1526. if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
  1527. mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
  1528. had_process_buffer_done(ctx);
  1529. }
  1530. return IRQ_HANDLED;
  1531. }
  1532. static void notify_audio_lpe(struct platform_device *pdev)
  1533. {
  1534. struct snd_intelhad *ctx = platform_get_drvdata(pdev);
  1535. schedule_work(&ctx->hdmi_audio_wq);
  1536. }
  1537. static void had_audio_wq(struct work_struct *work)
  1538. {
  1539. struct snd_intelhad *ctx =
  1540. container_of(work, struct snd_intelhad, hdmi_audio_wq);
  1541. struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
  1542. mutex_lock(&ctx->mutex);
  1543. if (!pdata->hdmi_connected) {
  1544. dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
  1545. __func__);
  1546. had_process_hot_unplug(ctx);
  1547. } else {
  1548. struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
  1549. dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
  1550. __func__, eld->port_id, pdata->tmds_clock_speed);
  1551. switch (eld->pipe_id) {
  1552. case 0:
  1553. ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
  1554. break;
  1555. case 1:
  1556. ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
  1557. break;
  1558. case 2:
  1559. ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
  1560. break;
  1561. default:
  1562. dev_dbg(ctx->dev, "Invalid pipe %d\n",
  1563. eld->pipe_id);
  1564. break;
  1565. }
  1566. memcpy(&ctx->eld, eld->eld_data, sizeof(ctx->eld));
  1567. ctx->dp_output = pdata->dp_output;
  1568. ctx->tmds_clock_speed = pdata->tmds_clock_speed;
  1569. ctx->link_rate = pdata->link_rate;
  1570. had_process_hot_plug(ctx);
  1571. /* Process mode change if stream is active */
  1572. if (ctx->stream_data.stream_type == HAD_RUNNING_STREAM)
  1573. hdmi_audio_mode_change(ctx);
  1574. }
  1575. mutex_unlock(&ctx->mutex);
  1576. }
  1577. /* release resources */
  1578. static void hdmi_lpe_audio_free(struct snd_card *card)
  1579. {
  1580. struct snd_intelhad *ctx = card->private_data;
  1581. cancel_work_sync(&ctx->hdmi_audio_wq);
  1582. if (ctx->mmio_start)
  1583. iounmap(ctx->mmio_start);
  1584. if (ctx->irq >= 0)
  1585. free_irq(ctx->irq, ctx);
  1586. }
  1587. /*
  1588. * hdmi_lpe_audio_probe - start bridge with i915
  1589. *
  1590. * This function is called when the i915 driver creates the
  1591. * hdmi-lpe-audio platform device.
  1592. */
  1593. static int hdmi_lpe_audio_probe(struct platform_device *pdev)
  1594. {
  1595. struct snd_card *card;
  1596. struct snd_intelhad *ctx;
  1597. struct snd_pcm *pcm;
  1598. struct intel_hdmi_lpe_audio_pdata *pdata;
  1599. int irq;
  1600. struct resource *res_mmio;
  1601. int ret;
  1602. dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask);
  1603. pdata = pdev->dev.platform_data;
  1604. if (!pdata) {
  1605. dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
  1606. return -EINVAL;
  1607. }
  1608. /* get resources */
  1609. irq = platform_get_irq(pdev, 0);
  1610. if (irq < 0) {
  1611. dev_err(&pdev->dev, "Could not get irq resource\n");
  1612. return -ENODEV;
  1613. }
  1614. res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1615. if (!res_mmio) {
  1616. dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
  1617. return -ENXIO;
  1618. }
  1619. /* create a card instance with ALSA framework */
  1620. ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
  1621. THIS_MODULE, sizeof(*ctx), &card);
  1622. if (ret)
  1623. return ret;
  1624. ctx = card->private_data;
  1625. spin_lock_init(&ctx->had_spinlock);
  1626. mutex_init(&ctx->mutex);
  1627. ctx->drv_status = HAD_DRV_DISCONNECTED;
  1628. ctx->dev = &pdev->dev;
  1629. ctx->card = card;
  1630. ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
  1631. strcpy(card->driver, INTEL_HAD);
  1632. strcpy(card->shortname, INTEL_HAD);
  1633. ctx->irq = -1;
  1634. ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
  1635. INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
  1636. card->private_free = hdmi_lpe_audio_free;
  1637. /* assume pipe A as default */
  1638. ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
  1639. platform_set_drvdata(pdev, ctx);
  1640. dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
  1641. __func__, (unsigned int)res_mmio->start,
  1642. (unsigned int)res_mmio->end);
  1643. ctx->mmio_start = ioremap_nocache(res_mmio->start,
  1644. (size_t)(resource_size(res_mmio)));
  1645. if (!ctx->mmio_start) {
  1646. dev_err(&pdev->dev, "Could not get ioremap\n");
  1647. ret = -EACCES;
  1648. goto err;
  1649. }
  1650. /* setup interrupt handler */
  1651. ret = request_irq(irq, display_pipe_interrupt_handler, 0,
  1652. pdev->name, ctx);
  1653. if (ret < 0) {
  1654. dev_err(&pdev->dev, "request_irq failed\n");
  1655. goto err;
  1656. }
  1657. ctx->irq = irq;
  1658. ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
  1659. MAX_CAP_STREAMS, &pcm);
  1660. if (ret)
  1661. goto err;
  1662. /* setup private data which can be retrieved when required */
  1663. pcm->private_data = ctx;
  1664. pcm->info_flags = 0;
  1665. strncpy(pcm->name, card->shortname, strlen(card->shortname));
  1666. /* setup the ops for playabck */
  1667. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1668. &snd_intelhad_playback_ops);
  1669. /* allocate dma pages for ALSA stream operations
  1670. * memory allocated is based on size, not max value
  1671. * thus using same argument for max & size
  1672. */
  1673. snd_pcm_lib_preallocate_pages_for_all(pcm,
  1674. SNDRV_DMA_TYPE_DEV, NULL,
  1675. HAD_MAX_BUFFER, HAD_MAX_BUFFER);
  1676. /* IEC958 controls */
  1677. ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958_mask, ctx));
  1678. if (ret < 0)
  1679. goto err;
  1680. ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958, ctx));
  1681. if (ret < 0)
  1682. goto err;
  1683. init_channel_allocations();
  1684. /* Register channel map controls */
  1685. ret = had_register_chmap_ctls(ctx, pcm);
  1686. if (ret < 0)
  1687. goto err;
  1688. ret = snd_card_register(card);
  1689. if (ret)
  1690. goto err;
  1691. spin_lock_irq(&pdata->lpe_audio_slock);
  1692. pdata->notify_audio_lpe = notify_audio_lpe;
  1693. pdata->notify_pending = false;
  1694. spin_unlock_irq(&pdata->lpe_audio_slock);
  1695. pm_runtime_set_active(&pdev->dev);
  1696. pm_runtime_enable(&pdev->dev);
  1697. dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
  1698. schedule_work(&ctx->hdmi_audio_wq);
  1699. return 0;
  1700. err:
  1701. snd_card_free(card);
  1702. return ret;
  1703. }
  1704. /*
  1705. * hdmi_lpe_audio_remove - stop bridge with i915
  1706. *
  1707. * This function is called when the platform device is destroyed.
  1708. */
  1709. static int hdmi_lpe_audio_remove(struct platform_device *pdev)
  1710. {
  1711. struct snd_intelhad *ctx = platform_get_drvdata(pdev);
  1712. if (ctx->drv_status != HAD_DRV_DISCONNECTED)
  1713. snd_intelhad_enable_audio_int(ctx, false);
  1714. snd_card_free(ctx->card);
  1715. return 0;
  1716. }
  1717. static struct platform_driver hdmi_lpe_audio_driver = {
  1718. .driver = {
  1719. .name = "hdmi-lpe-audio",
  1720. },
  1721. .probe = hdmi_lpe_audio_probe,
  1722. .remove = hdmi_lpe_audio_remove,
  1723. .suspend = hdmi_lpe_audio_suspend,
  1724. .resume = hdmi_lpe_audio_resume
  1725. };
  1726. module_platform_driver(hdmi_lpe_audio_driver);
  1727. MODULE_ALIAS("platform:hdmi_lpe_audio");
  1728. MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
  1729. MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
  1730. MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
  1731. MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
  1732. MODULE_DESCRIPTION("Intel HDMI Audio driver");
  1733. MODULE_LICENSE("GPL v2");
  1734. MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");