jz4740_wdt.c 6.0 KB

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  1. /*
  2. * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
  3. * JZ4740 Watchdog driver
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * You should have received a copy of the GNU General Public License along
  11. * with this program; if not, write to the Free Software Foundation, Inc.,
  12. * 675 Mass Ave, Cambridge, MA 02139, USA.
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/types.h>
  18. #include <linux/kernel.h>
  19. #include <linux/watchdog.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/device.h>
  23. #include <linux/clk.h>
  24. #include <linux/slab.h>
  25. #include <linux/err.h>
  26. #include <asm/mach-jz4740/timer.h>
  27. #define JZ_REG_WDT_TIMER_DATA 0x0
  28. #define JZ_REG_WDT_COUNTER_ENABLE 0x4
  29. #define JZ_REG_WDT_TIMER_COUNTER 0x8
  30. #define JZ_REG_WDT_TIMER_CONTROL 0xC
  31. #define JZ_WDT_CLOCK_PCLK 0x1
  32. #define JZ_WDT_CLOCK_RTC 0x2
  33. #define JZ_WDT_CLOCK_EXT 0x4
  34. #define JZ_WDT_CLOCK_DIV_SHIFT 3
  35. #define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
  36. #define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
  37. #define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
  38. #define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
  39. #define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
  40. #define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
  41. #define DEFAULT_HEARTBEAT 5
  42. #define MAX_HEARTBEAT 2048
  43. static bool nowayout = WATCHDOG_NOWAYOUT;
  44. module_param(nowayout, bool, 0);
  45. MODULE_PARM_DESC(nowayout,
  46. "Watchdog cannot be stopped once started (default="
  47. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  48. static unsigned int heartbeat = DEFAULT_HEARTBEAT;
  49. module_param(heartbeat, uint, 0);
  50. MODULE_PARM_DESC(heartbeat,
  51. "Watchdog heartbeat period in seconds from 1 to "
  52. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  53. __MODULE_STRING(DEFAULT_HEARTBEAT));
  54. struct jz4740_wdt_drvdata {
  55. struct watchdog_device wdt;
  56. void __iomem *base;
  57. struct clk *rtc_clk;
  58. };
  59. static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
  60. {
  61. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  62. writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
  63. return 0;
  64. }
  65. static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
  66. unsigned int new_timeout)
  67. {
  68. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  69. unsigned int rtc_clk_rate;
  70. unsigned int timeout_value;
  71. unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
  72. rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
  73. timeout_value = rtc_clk_rate * new_timeout;
  74. while (timeout_value > 0xffff) {
  75. if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
  76. /* Requested timeout too high;
  77. * use highest possible value. */
  78. timeout_value = 0xffff;
  79. break;
  80. }
  81. timeout_value >>= 2;
  82. clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
  83. }
  84. writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  85. writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
  86. writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
  87. writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
  88. writew(clock_div | JZ_WDT_CLOCK_RTC,
  89. drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
  90. writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  91. wdt_dev->timeout = new_timeout;
  92. return 0;
  93. }
  94. static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
  95. {
  96. jz4740_timer_enable_watchdog();
  97. jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
  98. return 0;
  99. }
  100. static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
  101. {
  102. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  103. jz4740_timer_disable_watchdog();
  104. writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  105. return 0;
  106. }
  107. static const struct watchdog_info jz4740_wdt_info = {
  108. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  109. .identity = "jz4740 Watchdog",
  110. };
  111. static const struct watchdog_ops jz4740_wdt_ops = {
  112. .owner = THIS_MODULE,
  113. .start = jz4740_wdt_start,
  114. .stop = jz4740_wdt_stop,
  115. .ping = jz4740_wdt_ping,
  116. .set_timeout = jz4740_wdt_set_timeout,
  117. };
  118. static int jz4740_wdt_probe(struct platform_device *pdev)
  119. {
  120. struct jz4740_wdt_drvdata *drvdata;
  121. struct watchdog_device *jz4740_wdt;
  122. struct resource *res;
  123. int ret;
  124. drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
  125. GFP_KERNEL);
  126. if (!drvdata) {
  127. dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
  128. return -ENOMEM;
  129. }
  130. if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
  131. heartbeat = DEFAULT_HEARTBEAT;
  132. jz4740_wdt = &drvdata->wdt;
  133. jz4740_wdt->info = &jz4740_wdt_info;
  134. jz4740_wdt->ops = &jz4740_wdt_ops;
  135. jz4740_wdt->timeout = heartbeat;
  136. jz4740_wdt->min_timeout = 1;
  137. jz4740_wdt->max_timeout = MAX_HEARTBEAT;
  138. watchdog_set_nowayout(jz4740_wdt, nowayout);
  139. watchdog_set_drvdata(jz4740_wdt, drvdata);
  140. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  141. drvdata->base = devm_ioremap_resource(&pdev->dev, res);
  142. if (IS_ERR(drvdata->base)) {
  143. ret = PTR_ERR(drvdata->base);
  144. goto err_out;
  145. }
  146. drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
  147. if (IS_ERR(drvdata->rtc_clk)) {
  148. dev_err(&pdev->dev, "cannot find RTC clock\n");
  149. ret = PTR_ERR(drvdata->rtc_clk);
  150. goto err_out;
  151. }
  152. ret = watchdog_register_device(&drvdata->wdt);
  153. if (ret < 0)
  154. goto err_disable_clk;
  155. platform_set_drvdata(pdev, drvdata);
  156. return 0;
  157. err_disable_clk:
  158. clk_put(drvdata->rtc_clk);
  159. err_out:
  160. return ret;
  161. }
  162. static int jz4740_wdt_remove(struct platform_device *pdev)
  163. {
  164. struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
  165. jz4740_wdt_stop(&drvdata->wdt);
  166. watchdog_unregister_device(&drvdata->wdt);
  167. clk_put(drvdata->rtc_clk);
  168. return 0;
  169. }
  170. static struct platform_driver jz4740_wdt_driver = {
  171. .probe = jz4740_wdt_probe,
  172. .remove = jz4740_wdt_remove,
  173. .driver = {
  174. .name = "jz4740-wdt",
  175. },
  176. };
  177. module_platform_driver(jz4740_wdt_driver);
  178. MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
  179. MODULE_DESCRIPTION("jz4740 Watchdog Driver");
  180. MODULE_LICENSE("GPL");
  181. MODULE_ALIAS("platform:jz4740-wdt");