virtgpu_vq.c 26 KB

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  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Authors:
  6. * Dave Airlie <airlied@redhat.com>
  7. * Gerd Hoffmann <kraxel@redhat.com>
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a
  10. * copy of this software and associated documentation files (the "Software"),
  11. * to deal in the Software without restriction, including without limitation
  12. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13. * and/or sell copies of the Software, and to permit persons to whom the
  14. * Software is furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the next
  17. * paragraph) shall be included in all copies or substantial portions of the
  18. * Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  26. * OTHER DEALINGS IN THE SOFTWARE.
  27. */
  28. #include <drm/drmP.h>
  29. #include "virtgpu_drv.h"
  30. #include <linux/virtio.h>
  31. #include <linux/virtio_config.h>
  32. #include <linux/virtio_ring.h>
  33. #define MAX_INLINE_CMD_SIZE 96
  34. #define MAX_INLINE_RESP_SIZE 24
  35. #define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
  36. + MAX_INLINE_CMD_SIZE \
  37. + MAX_INLINE_RESP_SIZE)
  38. void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
  39. uint32_t *resid)
  40. {
  41. int handle;
  42. idr_preload(GFP_KERNEL);
  43. spin_lock(&vgdev->resource_idr_lock);
  44. handle = idr_alloc(&vgdev->resource_idr, NULL, 1, 0, GFP_NOWAIT);
  45. spin_unlock(&vgdev->resource_idr_lock);
  46. idr_preload_end();
  47. *resid = handle;
  48. }
  49. void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id)
  50. {
  51. spin_lock(&vgdev->resource_idr_lock);
  52. idr_remove(&vgdev->resource_idr, id);
  53. spin_unlock(&vgdev->resource_idr_lock);
  54. }
  55. void virtio_gpu_ctrl_ack(struct virtqueue *vq)
  56. {
  57. struct drm_device *dev = vq->vdev->priv;
  58. struct virtio_gpu_device *vgdev = dev->dev_private;
  59. schedule_work(&vgdev->ctrlq.dequeue_work);
  60. }
  61. void virtio_gpu_cursor_ack(struct virtqueue *vq)
  62. {
  63. struct drm_device *dev = vq->vdev->priv;
  64. struct virtio_gpu_device *vgdev = dev->dev_private;
  65. schedule_work(&vgdev->cursorq.dequeue_work);
  66. }
  67. int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
  68. {
  69. struct virtio_gpu_vbuffer *vbuf;
  70. int i, size, count = 16;
  71. void *ptr;
  72. INIT_LIST_HEAD(&vgdev->free_vbufs);
  73. spin_lock_init(&vgdev->free_vbufs_lock);
  74. count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
  75. count += virtqueue_get_vring_size(vgdev->cursorq.vq);
  76. size = count * VBUFFER_SIZE;
  77. DRM_INFO("virtio vbuffers: %d bufs, %zdB each, %dkB total.\n",
  78. count, VBUFFER_SIZE, size / 1024);
  79. vgdev->vbufs = kzalloc(size, GFP_KERNEL);
  80. if (!vgdev->vbufs)
  81. return -ENOMEM;
  82. for (i = 0, ptr = vgdev->vbufs;
  83. i < count;
  84. i++, ptr += VBUFFER_SIZE) {
  85. vbuf = ptr;
  86. list_add(&vbuf->list, &vgdev->free_vbufs);
  87. }
  88. return 0;
  89. }
  90. void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
  91. {
  92. struct virtio_gpu_vbuffer *vbuf;
  93. int i, count = 0;
  94. count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
  95. count += virtqueue_get_vring_size(vgdev->cursorq.vq);
  96. spin_lock(&vgdev->free_vbufs_lock);
  97. for (i = 0; i < count; i++) {
  98. if (WARN_ON(list_empty(&vgdev->free_vbufs))) {
  99. spin_unlock(&vgdev->free_vbufs_lock);
  100. return;
  101. }
  102. vbuf = list_first_entry(&vgdev->free_vbufs,
  103. struct virtio_gpu_vbuffer, list);
  104. list_del(&vbuf->list);
  105. }
  106. spin_unlock(&vgdev->free_vbufs_lock);
  107. kfree(vgdev->vbufs);
  108. }
  109. static struct virtio_gpu_vbuffer*
  110. virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
  111. int size, int resp_size, void *resp_buf,
  112. virtio_gpu_resp_cb resp_cb)
  113. {
  114. struct virtio_gpu_vbuffer *vbuf;
  115. spin_lock(&vgdev->free_vbufs_lock);
  116. BUG_ON(list_empty(&vgdev->free_vbufs));
  117. vbuf = list_first_entry(&vgdev->free_vbufs,
  118. struct virtio_gpu_vbuffer, list);
  119. list_del(&vbuf->list);
  120. spin_unlock(&vgdev->free_vbufs_lock);
  121. memset(vbuf, 0, VBUFFER_SIZE);
  122. BUG_ON(size > MAX_INLINE_CMD_SIZE);
  123. vbuf->buf = (void *)vbuf + sizeof(*vbuf);
  124. vbuf->size = size;
  125. vbuf->resp_cb = resp_cb;
  126. vbuf->resp_size = resp_size;
  127. if (resp_size <= MAX_INLINE_RESP_SIZE)
  128. vbuf->resp_buf = (void *)vbuf->buf + size;
  129. else
  130. vbuf->resp_buf = resp_buf;
  131. BUG_ON(!vbuf->resp_buf);
  132. return vbuf;
  133. }
  134. static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
  135. struct virtio_gpu_vbuffer **vbuffer_p,
  136. int size)
  137. {
  138. struct virtio_gpu_vbuffer *vbuf;
  139. vbuf = virtio_gpu_get_vbuf(vgdev, size,
  140. sizeof(struct virtio_gpu_ctrl_hdr),
  141. NULL, NULL);
  142. if (IS_ERR(vbuf)) {
  143. *vbuffer_p = NULL;
  144. return ERR_CAST(vbuf);
  145. }
  146. *vbuffer_p = vbuf;
  147. return vbuf->buf;
  148. }
  149. static struct virtio_gpu_update_cursor*
  150. virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
  151. struct virtio_gpu_vbuffer **vbuffer_p)
  152. {
  153. struct virtio_gpu_vbuffer *vbuf;
  154. vbuf = virtio_gpu_get_vbuf
  155. (vgdev, sizeof(struct virtio_gpu_update_cursor),
  156. 0, NULL, NULL);
  157. if (IS_ERR(vbuf)) {
  158. *vbuffer_p = NULL;
  159. return ERR_CAST(vbuf);
  160. }
  161. *vbuffer_p = vbuf;
  162. return (struct virtio_gpu_update_cursor *)vbuf->buf;
  163. }
  164. static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
  165. virtio_gpu_resp_cb cb,
  166. struct virtio_gpu_vbuffer **vbuffer_p,
  167. int cmd_size, int resp_size,
  168. void *resp_buf)
  169. {
  170. struct virtio_gpu_vbuffer *vbuf;
  171. vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
  172. resp_size, resp_buf, cb);
  173. if (IS_ERR(vbuf)) {
  174. *vbuffer_p = NULL;
  175. return ERR_CAST(vbuf);
  176. }
  177. *vbuffer_p = vbuf;
  178. return (struct virtio_gpu_command *)vbuf->buf;
  179. }
  180. static void free_vbuf(struct virtio_gpu_device *vgdev,
  181. struct virtio_gpu_vbuffer *vbuf)
  182. {
  183. if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
  184. kfree(vbuf->resp_buf);
  185. kfree(vbuf->data_buf);
  186. spin_lock(&vgdev->free_vbufs_lock);
  187. list_add(&vbuf->list, &vgdev->free_vbufs);
  188. spin_unlock(&vgdev->free_vbufs_lock);
  189. }
  190. static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
  191. {
  192. struct virtio_gpu_vbuffer *vbuf;
  193. unsigned int len;
  194. int freed = 0;
  195. while ((vbuf = virtqueue_get_buf(vq, &len))) {
  196. list_add_tail(&vbuf->list, reclaim_list);
  197. freed++;
  198. }
  199. if (freed == 0)
  200. DRM_DEBUG("Huh? zero vbufs reclaimed");
  201. }
  202. void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
  203. {
  204. struct virtio_gpu_device *vgdev =
  205. container_of(work, struct virtio_gpu_device,
  206. ctrlq.dequeue_work);
  207. struct list_head reclaim_list;
  208. struct virtio_gpu_vbuffer *entry, *tmp;
  209. struct virtio_gpu_ctrl_hdr *resp;
  210. u64 fence_id = 0;
  211. INIT_LIST_HEAD(&reclaim_list);
  212. spin_lock(&vgdev->ctrlq.qlock);
  213. do {
  214. virtqueue_disable_cb(vgdev->ctrlq.vq);
  215. reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
  216. } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
  217. spin_unlock(&vgdev->ctrlq.qlock);
  218. list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
  219. resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
  220. if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA))
  221. DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
  222. if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
  223. u64 f = le64_to_cpu(resp->fence_id);
  224. if (fence_id > f) {
  225. DRM_ERROR("%s: Oops: fence %llx -> %llx\n",
  226. __func__, fence_id, f);
  227. } else {
  228. fence_id = f;
  229. }
  230. }
  231. if (entry->resp_cb)
  232. entry->resp_cb(vgdev, entry);
  233. list_del(&entry->list);
  234. free_vbuf(vgdev, entry);
  235. }
  236. wake_up(&vgdev->ctrlq.ack_queue);
  237. if (fence_id)
  238. virtio_gpu_fence_event_process(vgdev, fence_id);
  239. }
  240. void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
  241. {
  242. struct virtio_gpu_device *vgdev =
  243. container_of(work, struct virtio_gpu_device,
  244. cursorq.dequeue_work);
  245. struct list_head reclaim_list;
  246. struct virtio_gpu_vbuffer *entry, *tmp;
  247. INIT_LIST_HEAD(&reclaim_list);
  248. spin_lock(&vgdev->cursorq.qlock);
  249. do {
  250. virtqueue_disable_cb(vgdev->cursorq.vq);
  251. reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
  252. } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
  253. spin_unlock(&vgdev->cursorq.qlock);
  254. list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
  255. list_del(&entry->list);
  256. free_vbuf(vgdev, entry);
  257. }
  258. wake_up(&vgdev->cursorq.ack_queue);
  259. }
  260. static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev,
  261. struct virtio_gpu_vbuffer *vbuf)
  262. {
  263. struct virtqueue *vq = vgdev->ctrlq.vq;
  264. struct scatterlist *sgs[3], vcmd, vout, vresp;
  265. int outcnt = 0, incnt = 0;
  266. int ret;
  267. if (!vgdev->vqs_ready)
  268. return -ENODEV;
  269. sg_init_one(&vcmd, vbuf->buf, vbuf->size);
  270. sgs[outcnt+incnt] = &vcmd;
  271. outcnt++;
  272. if (vbuf->data_size) {
  273. sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
  274. sgs[outcnt + incnt] = &vout;
  275. outcnt++;
  276. }
  277. if (vbuf->resp_size) {
  278. sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
  279. sgs[outcnt + incnt] = &vresp;
  280. incnt++;
  281. }
  282. retry:
  283. ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
  284. if (ret == -ENOSPC) {
  285. spin_unlock(&vgdev->ctrlq.qlock);
  286. wait_event(vgdev->ctrlq.ack_queue, vq->num_free);
  287. spin_lock(&vgdev->ctrlq.qlock);
  288. goto retry;
  289. } else {
  290. virtqueue_kick(vq);
  291. }
  292. if (!ret)
  293. ret = vq->num_free;
  294. return ret;
  295. }
  296. static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
  297. struct virtio_gpu_vbuffer *vbuf)
  298. {
  299. int rc;
  300. spin_lock(&vgdev->ctrlq.qlock);
  301. rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
  302. spin_unlock(&vgdev->ctrlq.qlock);
  303. return rc;
  304. }
  305. static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
  306. struct virtio_gpu_vbuffer *vbuf,
  307. struct virtio_gpu_ctrl_hdr *hdr,
  308. struct virtio_gpu_fence **fence)
  309. {
  310. struct virtqueue *vq = vgdev->ctrlq.vq;
  311. int rc;
  312. again:
  313. spin_lock(&vgdev->ctrlq.qlock);
  314. /*
  315. * Make sure we have enouth space in the virtqueue. If not
  316. * wait here until we have.
  317. *
  318. * Without that virtio_gpu_queue_ctrl_buffer_nolock might have
  319. * to wait for free space, which can result in fence ids being
  320. * submitted out-of-order.
  321. */
  322. if (vq->num_free < 3) {
  323. spin_unlock(&vgdev->ctrlq.qlock);
  324. wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3);
  325. goto again;
  326. }
  327. if (fence)
  328. virtio_gpu_fence_emit(vgdev, hdr, fence);
  329. rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
  330. spin_unlock(&vgdev->ctrlq.qlock);
  331. return rc;
  332. }
  333. static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
  334. struct virtio_gpu_vbuffer *vbuf)
  335. {
  336. struct virtqueue *vq = vgdev->cursorq.vq;
  337. struct scatterlist *sgs[1], ccmd;
  338. int ret;
  339. int outcnt;
  340. if (!vgdev->vqs_ready)
  341. return -ENODEV;
  342. sg_init_one(&ccmd, vbuf->buf, vbuf->size);
  343. sgs[0] = &ccmd;
  344. outcnt = 1;
  345. spin_lock(&vgdev->cursorq.qlock);
  346. retry:
  347. ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
  348. if (ret == -ENOSPC) {
  349. spin_unlock(&vgdev->cursorq.qlock);
  350. wait_event(vgdev->cursorq.ack_queue, vq->num_free);
  351. spin_lock(&vgdev->cursorq.qlock);
  352. goto retry;
  353. } else {
  354. virtqueue_kick(vq);
  355. }
  356. spin_unlock(&vgdev->cursorq.qlock);
  357. if (!ret)
  358. ret = vq->num_free;
  359. return ret;
  360. }
  361. /* just create gem objects for userspace and long lived objects,
  362. just use dma_alloced pages for the queue objects? */
  363. /* create a basic resource */
  364. void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
  365. uint32_t resource_id,
  366. uint32_t format,
  367. uint32_t width,
  368. uint32_t height)
  369. {
  370. struct virtio_gpu_resource_create_2d *cmd_p;
  371. struct virtio_gpu_vbuffer *vbuf;
  372. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  373. memset(cmd_p, 0, sizeof(*cmd_p));
  374. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
  375. cmd_p->resource_id = cpu_to_le32(resource_id);
  376. cmd_p->format = cpu_to_le32(format);
  377. cmd_p->width = cpu_to_le32(width);
  378. cmd_p->height = cpu_to_le32(height);
  379. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  380. }
  381. void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
  382. uint32_t resource_id)
  383. {
  384. struct virtio_gpu_resource_unref *cmd_p;
  385. struct virtio_gpu_vbuffer *vbuf;
  386. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  387. memset(cmd_p, 0, sizeof(*cmd_p));
  388. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
  389. cmd_p->resource_id = cpu_to_le32(resource_id);
  390. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  391. }
  392. void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev,
  393. uint32_t resource_id)
  394. {
  395. struct virtio_gpu_resource_detach_backing *cmd_p;
  396. struct virtio_gpu_vbuffer *vbuf;
  397. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  398. memset(cmd_p, 0, sizeof(*cmd_p));
  399. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
  400. cmd_p->resource_id = cpu_to_le32(resource_id);
  401. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  402. }
  403. void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
  404. uint32_t scanout_id, uint32_t resource_id,
  405. uint32_t width, uint32_t height,
  406. uint32_t x, uint32_t y)
  407. {
  408. struct virtio_gpu_set_scanout *cmd_p;
  409. struct virtio_gpu_vbuffer *vbuf;
  410. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  411. memset(cmd_p, 0, sizeof(*cmd_p));
  412. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
  413. cmd_p->resource_id = cpu_to_le32(resource_id);
  414. cmd_p->scanout_id = cpu_to_le32(scanout_id);
  415. cmd_p->r.width = cpu_to_le32(width);
  416. cmd_p->r.height = cpu_to_le32(height);
  417. cmd_p->r.x = cpu_to_le32(x);
  418. cmd_p->r.y = cpu_to_le32(y);
  419. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  420. }
  421. void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
  422. uint32_t resource_id,
  423. uint32_t x, uint32_t y,
  424. uint32_t width, uint32_t height)
  425. {
  426. struct virtio_gpu_resource_flush *cmd_p;
  427. struct virtio_gpu_vbuffer *vbuf;
  428. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  429. memset(cmd_p, 0, sizeof(*cmd_p));
  430. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
  431. cmd_p->resource_id = cpu_to_le32(resource_id);
  432. cmd_p->r.width = cpu_to_le32(width);
  433. cmd_p->r.height = cpu_to_le32(height);
  434. cmd_p->r.x = cpu_to_le32(x);
  435. cmd_p->r.y = cpu_to_le32(y);
  436. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  437. }
  438. void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
  439. uint32_t resource_id, uint64_t offset,
  440. __le32 width, __le32 height,
  441. __le32 x, __le32 y,
  442. struct virtio_gpu_fence **fence)
  443. {
  444. struct virtio_gpu_transfer_to_host_2d *cmd_p;
  445. struct virtio_gpu_vbuffer *vbuf;
  446. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  447. memset(cmd_p, 0, sizeof(*cmd_p));
  448. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
  449. cmd_p->resource_id = cpu_to_le32(resource_id);
  450. cmd_p->offset = cpu_to_le64(offset);
  451. cmd_p->r.width = width;
  452. cmd_p->r.height = height;
  453. cmd_p->r.x = x;
  454. cmd_p->r.y = y;
  455. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  456. }
  457. static void
  458. virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
  459. uint32_t resource_id,
  460. struct virtio_gpu_mem_entry *ents,
  461. uint32_t nents,
  462. struct virtio_gpu_fence **fence)
  463. {
  464. struct virtio_gpu_resource_attach_backing *cmd_p;
  465. struct virtio_gpu_vbuffer *vbuf;
  466. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  467. memset(cmd_p, 0, sizeof(*cmd_p));
  468. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
  469. cmd_p->resource_id = cpu_to_le32(resource_id);
  470. cmd_p->nr_entries = cpu_to_le32(nents);
  471. vbuf->data_buf = ents;
  472. vbuf->data_size = sizeof(*ents) * nents;
  473. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  474. }
  475. static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
  476. struct virtio_gpu_vbuffer *vbuf)
  477. {
  478. struct virtio_gpu_resp_display_info *resp =
  479. (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
  480. int i;
  481. spin_lock(&vgdev->display_info_lock);
  482. for (i = 0; i < vgdev->num_scanouts; i++) {
  483. vgdev->outputs[i].info = resp->pmodes[i];
  484. if (resp->pmodes[i].enabled) {
  485. DRM_DEBUG("output %d: %dx%d+%d+%d", i,
  486. le32_to_cpu(resp->pmodes[i].r.width),
  487. le32_to_cpu(resp->pmodes[i].r.height),
  488. le32_to_cpu(resp->pmodes[i].r.x),
  489. le32_to_cpu(resp->pmodes[i].r.y));
  490. } else {
  491. DRM_DEBUG("output %d: disabled", i);
  492. }
  493. }
  494. vgdev->display_info_pending = false;
  495. spin_unlock(&vgdev->display_info_lock);
  496. wake_up(&vgdev->resp_wq);
  497. if (!drm_helper_hpd_irq_event(vgdev->ddev))
  498. drm_kms_helper_hotplug_event(vgdev->ddev);
  499. }
  500. static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
  501. struct virtio_gpu_vbuffer *vbuf)
  502. {
  503. struct virtio_gpu_get_capset_info *cmd =
  504. (struct virtio_gpu_get_capset_info *)vbuf->buf;
  505. struct virtio_gpu_resp_capset_info *resp =
  506. (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
  507. int i = le32_to_cpu(cmd->capset_index);
  508. spin_lock(&vgdev->display_info_lock);
  509. vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
  510. vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
  511. vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
  512. spin_unlock(&vgdev->display_info_lock);
  513. wake_up(&vgdev->resp_wq);
  514. }
  515. static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
  516. struct virtio_gpu_vbuffer *vbuf)
  517. {
  518. struct virtio_gpu_get_capset *cmd =
  519. (struct virtio_gpu_get_capset *)vbuf->buf;
  520. struct virtio_gpu_resp_capset *resp =
  521. (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
  522. struct virtio_gpu_drv_cap_cache *cache_ent;
  523. spin_lock(&vgdev->display_info_lock);
  524. list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
  525. if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
  526. cache_ent->id == le32_to_cpu(cmd->capset_id)) {
  527. memcpy(cache_ent->caps_cache, resp->capset_data,
  528. cache_ent->size);
  529. atomic_set(&cache_ent->is_valid, 1);
  530. break;
  531. }
  532. }
  533. spin_unlock(&vgdev->display_info_lock);
  534. wake_up(&vgdev->resp_wq);
  535. }
  536. int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
  537. {
  538. struct virtio_gpu_ctrl_hdr *cmd_p;
  539. struct virtio_gpu_vbuffer *vbuf;
  540. void *resp_buf;
  541. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
  542. GFP_KERNEL);
  543. if (!resp_buf)
  544. return -ENOMEM;
  545. cmd_p = virtio_gpu_alloc_cmd_resp
  546. (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
  547. sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
  548. resp_buf);
  549. memset(cmd_p, 0, sizeof(*cmd_p));
  550. vgdev->display_info_pending = true;
  551. cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
  552. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  553. return 0;
  554. }
  555. int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
  556. {
  557. struct virtio_gpu_get_capset_info *cmd_p;
  558. struct virtio_gpu_vbuffer *vbuf;
  559. void *resp_buf;
  560. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
  561. GFP_KERNEL);
  562. if (!resp_buf)
  563. return -ENOMEM;
  564. cmd_p = virtio_gpu_alloc_cmd_resp
  565. (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
  566. sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
  567. resp_buf);
  568. memset(cmd_p, 0, sizeof(*cmd_p));
  569. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
  570. cmd_p->capset_index = cpu_to_le32(idx);
  571. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  572. return 0;
  573. }
  574. int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
  575. int idx, int version,
  576. struct virtio_gpu_drv_cap_cache **cache_p)
  577. {
  578. struct virtio_gpu_get_capset *cmd_p;
  579. struct virtio_gpu_vbuffer *vbuf;
  580. int max_size = vgdev->capsets[idx].max_size;
  581. struct virtio_gpu_drv_cap_cache *cache_ent;
  582. void *resp_buf;
  583. if (idx > vgdev->num_capsets)
  584. return -EINVAL;
  585. if (version > vgdev->capsets[idx].max_version)
  586. return -EINVAL;
  587. cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
  588. if (!cache_ent)
  589. return -ENOMEM;
  590. cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
  591. if (!cache_ent->caps_cache) {
  592. kfree(cache_ent);
  593. return -ENOMEM;
  594. }
  595. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
  596. GFP_KERNEL);
  597. if (!resp_buf) {
  598. kfree(cache_ent->caps_cache);
  599. kfree(cache_ent);
  600. return -ENOMEM;
  601. }
  602. cache_ent->version = version;
  603. cache_ent->id = vgdev->capsets[idx].id;
  604. atomic_set(&cache_ent->is_valid, 0);
  605. cache_ent->size = max_size;
  606. spin_lock(&vgdev->display_info_lock);
  607. list_add_tail(&cache_ent->head, &vgdev->cap_cache);
  608. spin_unlock(&vgdev->display_info_lock);
  609. cmd_p = virtio_gpu_alloc_cmd_resp
  610. (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
  611. sizeof(struct virtio_gpu_resp_capset) + max_size,
  612. resp_buf);
  613. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
  614. cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
  615. cmd_p->capset_version = cpu_to_le32(version);
  616. *cache_p = cache_ent;
  617. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  618. return 0;
  619. }
  620. void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
  621. uint32_t nlen, const char *name)
  622. {
  623. struct virtio_gpu_ctx_create *cmd_p;
  624. struct virtio_gpu_vbuffer *vbuf;
  625. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  626. memset(cmd_p, 0, sizeof(*cmd_p));
  627. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
  628. cmd_p->hdr.ctx_id = cpu_to_le32(id);
  629. cmd_p->nlen = cpu_to_le32(nlen);
  630. strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name)-1);
  631. cmd_p->debug_name[sizeof(cmd_p->debug_name)-1] = 0;
  632. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  633. }
  634. void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
  635. uint32_t id)
  636. {
  637. struct virtio_gpu_ctx_destroy *cmd_p;
  638. struct virtio_gpu_vbuffer *vbuf;
  639. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  640. memset(cmd_p, 0, sizeof(*cmd_p));
  641. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
  642. cmd_p->hdr.ctx_id = cpu_to_le32(id);
  643. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  644. }
  645. void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
  646. uint32_t ctx_id,
  647. uint32_t resource_id)
  648. {
  649. struct virtio_gpu_ctx_resource *cmd_p;
  650. struct virtio_gpu_vbuffer *vbuf;
  651. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  652. memset(cmd_p, 0, sizeof(*cmd_p));
  653. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
  654. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  655. cmd_p->resource_id = cpu_to_le32(resource_id);
  656. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  657. }
  658. void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
  659. uint32_t ctx_id,
  660. uint32_t resource_id)
  661. {
  662. struct virtio_gpu_ctx_resource *cmd_p;
  663. struct virtio_gpu_vbuffer *vbuf;
  664. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  665. memset(cmd_p, 0, sizeof(*cmd_p));
  666. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
  667. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  668. cmd_p->resource_id = cpu_to_le32(resource_id);
  669. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  670. }
  671. void
  672. virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
  673. struct virtio_gpu_resource_create_3d *rc_3d,
  674. struct virtio_gpu_fence **fence)
  675. {
  676. struct virtio_gpu_resource_create_3d *cmd_p;
  677. struct virtio_gpu_vbuffer *vbuf;
  678. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  679. memset(cmd_p, 0, sizeof(*cmd_p));
  680. *cmd_p = *rc_3d;
  681. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
  682. cmd_p->hdr.flags = 0;
  683. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  684. }
  685. void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
  686. uint32_t resource_id, uint32_t ctx_id,
  687. uint64_t offset, uint32_t level,
  688. struct virtio_gpu_box *box,
  689. struct virtio_gpu_fence **fence)
  690. {
  691. struct virtio_gpu_transfer_host_3d *cmd_p;
  692. struct virtio_gpu_vbuffer *vbuf;
  693. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  694. memset(cmd_p, 0, sizeof(*cmd_p));
  695. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
  696. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  697. cmd_p->resource_id = cpu_to_le32(resource_id);
  698. cmd_p->box = *box;
  699. cmd_p->offset = cpu_to_le64(offset);
  700. cmd_p->level = cpu_to_le32(level);
  701. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  702. }
  703. void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
  704. uint32_t resource_id, uint32_t ctx_id,
  705. uint64_t offset, uint32_t level,
  706. struct virtio_gpu_box *box,
  707. struct virtio_gpu_fence **fence)
  708. {
  709. struct virtio_gpu_transfer_host_3d *cmd_p;
  710. struct virtio_gpu_vbuffer *vbuf;
  711. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  712. memset(cmd_p, 0, sizeof(*cmd_p));
  713. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
  714. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  715. cmd_p->resource_id = cpu_to_le32(resource_id);
  716. cmd_p->box = *box;
  717. cmd_p->offset = cpu_to_le64(offset);
  718. cmd_p->level = cpu_to_le32(level);
  719. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  720. }
  721. void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
  722. void *data, uint32_t data_size,
  723. uint32_t ctx_id, struct virtio_gpu_fence **fence)
  724. {
  725. struct virtio_gpu_cmd_submit *cmd_p;
  726. struct virtio_gpu_vbuffer *vbuf;
  727. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  728. memset(cmd_p, 0, sizeof(*cmd_p));
  729. vbuf->data_buf = data;
  730. vbuf->data_size = data_size;
  731. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
  732. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  733. cmd_p->size = cpu_to_le32(data_size);
  734. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  735. }
  736. int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
  737. struct virtio_gpu_object *obj,
  738. uint32_t resource_id,
  739. struct virtio_gpu_fence **fence)
  740. {
  741. struct virtio_gpu_mem_entry *ents;
  742. struct scatterlist *sg;
  743. int si;
  744. if (!obj->pages) {
  745. int ret;
  746. ret = virtio_gpu_object_get_sg_table(vgdev, obj);
  747. if (ret)
  748. return ret;
  749. }
  750. /* gets freed when the ring has consumed it */
  751. ents = kmalloc_array(obj->pages->nents,
  752. sizeof(struct virtio_gpu_mem_entry),
  753. GFP_KERNEL);
  754. if (!ents) {
  755. DRM_ERROR("failed to allocate ent list\n");
  756. return -ENOMEM;
  757. }
  758. for_each_sg(obj->pages->sgl, sg, obj->pages->nents, si) {
  759. ents[si].addr = cpu_to_le64(sg_phys(sg));
  760. ents[si].length = cpu_to_le32(sg->length);
  761. ents[si].padding = 0;
  762. }
  763. virtio_gpu_cmd_resource_attach_backing(vgdev, resource_id,
  764. ents, obj->pages->nents,
  765. fence);
  766. obj->hw_res_handle = resource_id;
  767. return 0;
  768. }
  769. void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
  770. struct virtio_gpu_output *output)
  771. {
  772. struct virtio_gpu_vbuffer *vbuf;
  773. struct virtio_gpu_update_cursor *cur_p;
  774. output->cursor.pos.scanout_id = cpu_to_le32(output->index);
  775. cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
  776. memcpy(cur_p, &output->cursor, sizeof(output->cursor));
  777. virtio_gpu_queue_cursor(vgdev, vbuf);
  778. }