intel-pt.c 64 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <inttypes.h>
  16. #include <stdio.h>
  17. #include <stdbool.h>
  18. #include <errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include "../perf.h"
  22. #include "session.h"
  23. #include "machine.h"
  24. #include "memswap.h"
  25. #include "sort.h"
  26. #include "tool.h"
  27. #include "event.h"
  28. #include "evlist.h"
  29. #include "evsel.h"
  30. #include "map.h"
  31. #include "color.h"
  32. #include "util.h"
  33. #include "thread.h"
  34. #include "thread-stack.h"
  35. #include "symbol.h"
  36. #include "callchain.h"
  37. #include "dso.h"
  38. #include "debug.h"
  39. #include "auxtrace.h"
  40. #include "tsc.h"
  41. #include "intel-pt.h"
  42. #include "config.h"
  43. #include "intel-pt-decoder/intel-pt-log.h"
  44. #include "intel-pt-decoder/intel-pt-decoder.h"
  45. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  46. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  47. #define MAX_TIMESTAMP (~0ULL)
  48. struct intel_pt {
  49. struct auxtrace auxtrace;
  50. struct auxtrace_queues queues;
  51. struct auxtrace_heap heap;
  52. u32 auxtrace_type;
  53. struct perf_session *session;
  54. struct machine *machine;
  55. struct perf_evsel *switch_evsel;
  56. struct thread *unknown_thread;
  57. bool timeless_decoding;
  58. bool sampling_mode;
  59. bool snapshot_mode;
  60. bool per_cpu_mmaps;
  61. bool have_tsc;
  62. bool data_queued;
  63. bool est_tsc;
  64. bool sync_switch;
  65. bool mispred_all;
  66. int have_sched_switch;
  67. u32 pmu_type;
  68. u64 kernel_start;
  69. u64 switch_ip;
  70. u64 ptss_ip;
  71. struct perf_tsc_conversion tc;
  72. bool cap_user_time_zero;
  73. struct itrace_synth_opts synth_opts;
  74. bool sample_instructions;
  75. u64 instructions_sample_type;
  76. u64 instructions_id;
  77. bool sample_branches;
  78. u32 branches_filter;
  79. u64 branches_sample_type;
  80. u64 branches_id;
  81. bool sample_transactions;
  82. u64 transactions_sample_type;
  83. u64 transactions_id;
  84. bool sample_ptwrites;
  85. u64 ptwrites_sample_type;
  86. u64 ptwrites_id;
  87. bool sample_pwr_events;
  88. u64 pwr_events_sample_type;
  89. u64 mwait_id;
  90. u64 pwre_id;
  91. u64 exstop_id;
  92. u64 pwrx_id;
  93. u64 cbr_id;
  94. u64 tsc_bit;
  95. u64 mtc_bit;
  96. u64 mtc_freq_bits;
  97. u32 tsc_ctc_ratio_n;
  98. u32 tsc_ctc_ratio_d;
  99. u64 cyc_bit;
  100. u64 noretcomp_bit;
  101. unsigned max_non_turbo_ratio;
  102. unsigned cbr2khz;
  103. unsigned long num_events;
  104. char *filter;
  105. struct addr_filters filts;
  106. };
  107. enum switch_state {
  108. INTEL_PT_SS_NOT_TRACING,
  109. INTEL_PT_SS_UNKNOWN,
  110. INTEL_PT_SS_TRACING,
  111. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  112. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  113. };
  114. struct intel_pt_queue {
  115. struct intel_pt *pt;
  116. unsigned int queue_nr;
  117. struct auxtrace_buffer *buffer;
  118. struct auxtrace_buffer *old_buffer;
  119. void *decoder;
  120. const struct intel_pt_state *state;
  121. struct ip_callchain *chain;
  122. struct branch_stack *last_branch;
  123. struct branch_stack *last_branch_rb;
  124. size_t last_branch_pos;
  125. union perf_event *event_buf;
  126. bool on_heap;
  127. bool stop;
  128. bool step_through_buffers;
  129. bool use_buffer_pid_tid;
  130. bool sync_switch;
  131. pid_t pid, tid;
  132. int cpu;
  133. int switch_state;
  134. pid_t next_tid;
  135. struct thread *thread;
  136. bool exclude_kernel;
  137. bool have_sample;
  138. u64 time;
  139. u64 timestamp;
  140. u32 flags;
  141. u16 insn_len;
  142. u64 last_insn_cnt;
  143. char insn[INTEL_PT_INSN_BUF_SZ];
  144. };
  145. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  146. unsigned char *buf, size_t len)
  147. {
  148. struct intel_pt_pkt packet;
  149. size_t pos = 0;
  150. int ret, pkt_len, i;
  151. char desc[INTEL_PT_PKT_DESC_MAX];
  152. const char *color = PERF_COLOR_BLUE;
  153. color_fprintf(stdout, color,
  154. ". ... Intel Processor Trace data: size %zu bytes\n",
  155. len);
  156. while (len) {
  157. ret = intel_pt_get_packet(buf, len, &packet);
  158. if (ret > 0)
  159. pkt_len = ret;
  160. else
  161. pkt_len = 1;
  162. printf(".");
  163. color_fprintf(stdout, color, " %08x: ", pos);
  164. for (i = 0; i < pkt_len; i++)
  165. color_fprintf(stdout, color, " %02x", buf[i]);
  166. for (; i < 16; i++)
  167. color_fprintf(stdout, color, " ");
  168. if (ret > 0) {
  169. ret = intel_pt_pkt_desc(&packet, desc,
  170. INTEL_PT_PKT_DESC_MAX);
  171. if (ret > 0)
  172. color_fprintf(stdout, color, " %s\n", desc);
  173. } else {
  174. color_fprintf(stdout, color, " Bad packet!\n");
  175. }
  176. pos += pkt_len;
  177. buf += pkt_len;
  178. len -= pkt_len;
  179. }
  180. }
  181. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  182. size_t len)
  183. {
  184. printf(".\n");
  185. intel_pt_dump(pt, buf, len);
  186. }
  187. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  188. struct auxtrace_buffer *b)
  189. {
  190. bool consecutive = false;
  191. void *start;
  192. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  193. pt->have_tsc, &consecutive);
  194. if (!start)
  195. return -EINVAL;
  196. b->use_size = b->data + b->size - start;
  197. b->use_data = start;
  198. if (b->use_size && consecutive)
  199. b->consecutive = true;
  200. return 0;
  201. }
  202. /* This function assumes data is processed sequentially only */
  203. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  204. {
  205. struct intel_pt_queue *ptq = data;
  206. struct auxtrace_buffer *buffer = ptq->buffer;
  207. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  208. struct auxtrace_queue *queue;
  209. bool might_overlap;
  210. if (ptq->stop) {
  211. b->len = 0;
  212. return 0;
  213. }
  214. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  215. buffer = auxtrace_buffer__next(queue, buffer);
  216. if (!buffer) {
  217. if (old_buffer)
  218. auxtrace_buffer__drop_data(old_buffer);
  219. b->len = 0;
  220. return 0;
  221. }
  222. ptq->buffer = buffer;
  223. if (!buffer->data) {
  224. int fd = perf_data__fd(ptq->pt->session->data);
  225. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  226. if (!buffer->data)
  227. return -ENOMEM;
  228. }
  229. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  230. if (might_overlap && !buffer->consecutive && old_buffer &&
  231. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  232. return -ENOMEM;
  233. if (buffer->use_data) {
  234. b->len = buffer->use_size;
  235. b->buf = buffer->use_data;
  236. } else {
  237. b->len = buffer->size;
  238. b->buf = buffer->data;
  239. }
  240. b->ref_timestamp = buffer->reference;
  241. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  242. b->consecutive = false;
  243. b->trace_nr = buffer->buffer_nr + 1;
  244. } else {
  245. b->consecutive = true;
  246. }
  247. if (ptq->step_through_buffers)
  248. ptq->stop = true;
  249. if (b->len) {
  250. if (old_buffer)
  251. auxtrace_buffer__drop_data(old_buffer);
  252. ptq->old_buffer = buffer;
  253. } else {
  254. auxtrace_buffer__drop_data(buffer);
  255. return intel_pt_get_trace(b, data);
  256. }
  257. return 0;
  258. }
  259. struct intel_pt_cache_entry {
  260. struct auxtrace_cache_entry entry;
  261. u64 insn_cnt;
  262. u64 byte_cnt;
  263. enum intel_pt_insn_op op;
  264. enum intel_pt_insn_branch branch;
  265. int length;
  266. int32_t rel;
  267. char insn[INTEL_PT_INSN_BUF_SZ];
  268. };
  269. static int intel_pt_config_div(const char *var, const char *value, void *data)
  270. {
  271. int *d = data;
  272. long val;
  273. if (!strcmp(var, "intel-pt.cache-divisor")) {
  274. val = strtol(value, NULL, 0);
  275. if (val > 0 && val <= INT_MAX)
  276. *d = val;
  277. }
  278. return 0;
  279. }
  280. static int intel_pt_cache_divisor(void)
  281. {
  282. static int d;
  283. if (d)
  284. return d;
  285. perf_config(intel_pt_config_div, &d);
  286. if (!d)
  287. d = 64;
  288. return d;
  289. }
  290. static unsigned int intel_pt_cache_size(struct dso *dso,
  291. struct machine *machine)
  292. {
  293. off_t size;
  294. size = dso__data_size(dso, machine);
  295. size /= intel_pt_cache_divisor();
  296. if (size < 1000)
  297. return 10;
  298. if (size > (1 << 21))
  299. return 21;
  300. return 32 - __builtin_clz(size);
  301. }
  302. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  303. struct machine *machine)
  304. {
  305. struct auxtrace_cache *c;
  306. unsigned int bits;
  307. if (dso->auxtrace_cache)
  308. return dso->auxtrace_cache;
  309. bits = intel_pt_cache_size(dso, machine);
  310. /* Ignoring cache creation failure */
  311. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  312. dso->auxtrace_cache = c;
  313. return c;
  314. }
  315. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  316. u64 offset, u64 insn_cnt, u64 byte_cnt,
  317. struct intel_pt_insn *intel_pt_insn)
  318. {
  319. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  320. struct intel_pt_cache_entry *e;
  321. int err;
  322. if (!c)
  323. return -ENOMEM;
  324. e = auxtrace_cache__alloc_entry(c);
  325. if (!e)
  326. return -ENOMEM;
  327. e->insn_cnt = insn_cnt;
  328. e->byte_cnt = byte_cnt;
  329. e->op = intel_pt_insn->op;
  330. e->branch = intel_pt_insn->branch;
  331. e->length = intel_pt_insn->length;
  332. e->rel = intel_pt_insn->rel;
  333. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  334. err = auxtrace_cache__add(c, offset, &e->entry);
  335. if (err)
  336. auxtrace_cache__free_entry(c, e);
  337. return err;
  338. }
  339. static struct intel_pt_cache_entry *
  340. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  341. {
  342. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  343. if (!c)
  344. return NULL;
  345. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  346. }
  347. static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
  348. {
  349. return ip >= pt->kernel_start ?
  350. PERF_RECORD_MISC_KERNEL :
  351. PERF_RECORD_MISC_USER;
  352. }
  353. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  354. uint64_t *insn_cnt_ptr, uint64_t *ip,
  355. uint64_t to_ip, uint64_t max_insn_cnt,
  356. void *data)
  357. {
  358. struct intel_pt_queue *ptq = data;
  359. struct machine *machine = ptq->pt->machine;
  360. struct thread *thread;
  361. struct addr_location al;
  362. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  363. ssize_t len;
  364. int x86_64;
  365. u8 cpumode;
  366. u64 offset, start_offset, start_ip;
  367. u64 insn_cnt = 0;
  368. bool one_map = true;
  369. intel_pt_insn->length = 0;
  370. if (to_ip && *ip == to_ip)
  371. goto out_no_cache;
  372. cpumode = intel_pt_cpumode(ptq->pt, *ip);
  373. thread = ptq->thread;
  374. if (!thread) {
  375. if (cpumode != PERF_RECORD_MISC_KERNEL)
  376. return -EINVAL;
  377. thread = ptq->pt->unknown_thread;
  378. }
  379. while (1) {
  380. if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
  381. return -EINVAL;
  382. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  383. dso__data_status_seen(al.map->dso,
  384. DSO_DATA_STATUS_SEEN_ITRACE))
  385. return -ENOENT;
  386. offset = al.map->map_ip(al.map, *ip);
  387. if (!to_ip && one_map) {
  388. struct intel_pt_cache_entry *e;
  389. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  390. if (e &&
  391. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  392. *insn_cnt_ptr = e->insn_cnt;
  393. *ip += e->byte_cnt;
  394. intel_pt_insn->op = e->op;
  395. intel_pt_insn->branch = e->branch;
  396. intel_pt_insn->length = e->length;
  397. intel_pt_insn->rel = e->rel;
  398. memcpy(intel_pt_insn->buf, e->insn,
  399. INTEL_PT_INSN_BUF_SZ);
  400. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  401. return 0;
  402. }
  403. }
  404. start_offset = offset;
  405. start_ip = *ip;
  406. /* Load maps to ensure dso->is_64_bit has been updated */
  407. map__load(al.map);
  408. x86_64 = al.map->dso->is_64_bit;
  409. while (1) {
  410. len = dso__data_read_offset(al.map->dso, machine,
  411. offset, buf,
  412. INTEL_PT_INSN_BUF_SZ);
  413. if (len <= 0)
  414. return -EINVAL;
  415. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  416. return -EINVAL;
  417. intel_pt_log_insn(intel_pt_insn, *ip);
  418. insn_cnt += 1;
  419. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  420. goto out;
  421. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  422. goto out_no_cache;
  423. *ip += intel_pt_insn->length;
  424. if (to_ip && *ip == to_ip)
  425. goto out_no_cache;
  426. if (*ip >= al.map->end)
  427. break;
  428. offset += intel_pt_insn->length;
  429. }
  430. one_map = false;
  431. }
  432. out:
  433. *insn_cnt_ptr = insn_cnt;
  434. if (!one_map)
  435. goto out_no_cache;
  436. /*
  437. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  438. * entries.
  439. */
  440. if (to_ip) {
  441. struct intel_pt_cache_entry *e;
  442. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  443. if (e)
  444. return 0;
  445. }
  446. /* Ignore cache errors */
  447. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  448. *ip - start_ip, intel_pt_insn);
  449. return 0;
  450. out_no_cache:
  451. *insn_cnt_ptr = insn_cnt;
  452. return 0;
  453. }
  454. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  455. uint64_t offset, const char *filename)
  456. {
  457. struct addr_filter *filt;
  458. bool have_filter = false;
  459. bool hit_tracestop = false;
  460. bool hit_filter = false;
  461. list_for_each_entry(filt, &pt->filts.head, list) {
  462. if (filt->start)
  463. have_filter = true;
  464. if ((filename && !filt->filename) ||
  465. (!filename && filt->filename) ||
  466. (filename && strcmp(filename, filt->filename)))
  467. continue;
  468. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  469. continue;
  470. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  471. ip, offset, filename ? filename : "[kernel]",
  472. filt->start ? "filter" : "stop",
  473. filt->addr, filt->size);
  474. if (filt->start)
  475. hit_filter = true;
  476. else
  477. hit_tracestop = true;
  478. }
  479. if (!hit_tracestop && !hit_filter)
  480. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  481. ip, offset, filename ? filename : "[kernel]");
  482. return hit_tracestop || (have_filter && !hit_filter);
  483. }
  484. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  485. {
  486. struct intel_pt_queue *ptq = data;
  487. struct thread *thread;
  488. struct addr_location al;
  489. u8 cpumode;
  490. u64 offset;
  491. if (ip >= ptq->pt->kernel_start)
  492. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  493. cpumode = PERF_RECORD_MISC_USER;
  494. thread = ptq->thread;
  495. if (!thread)
  496. return -EINVAL;
  497. if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
  498. return -EINVAL;
  499. offset = al.map->map_ip(al.map, ip);
  500. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  501. al.map->dso->long_name);
  502. }
  503. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  504. {
  505. return __intel_pt_pgd_ip(ip, data) > 0;
  506. }
  507. static bool intel_pt_get_config(struct intel_pt *pt,
  508. struct perf_event_attr *attr, u64 *config)
  509. {
  510. if (attr->type == pt->pmu_type) {
  511. if (config)
  512. *config = attr->config;
  513. return true;
  514. }
  515. return false;
  516. }
  517. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  518. {
  519. struct perf_evsel *evsel;
  520. evlist__for_each_entry(pt->session->evlist, evsel) {
  521. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  522. !evsel->attr.exclude_kernel)
  523. return false;
  524. }
  525. return true;
  526. }
  527. static bool intel_pt_return_compression(struct intel_pt *pt)
  528. {
  529. struct perf_evsel *evsel;
  530. u64 config;
  531. if (!pt->noretcomp_bit)
  532. return true;
  533. evlist__for_each_entry(pt->session->evlist, evsel) {
  534. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  535. (config & pt->noretcomp_bit))
  536. return false;
  537. }
  538. return true;
  539. }
  540. static bool intel_pt_branch_enable(struct intel_pt *pt)
  541. {
  542. struct perf_evsel *evsel;
  543. u64 config;
  544. evlist__for_each_entry(pt->session->evlist, evsel) {
  545. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  546. (config & 1) && !(config & 0x2000))
  547. return false;
  548. }
  549. return true;
  550. }
  551. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  552. {
  553. struct perf_evsel *evsel;
  554. unsigned int shift;
  555. u64 config;
  556. if (!pt->mtc_freq_bits)
  557. return 0;
  558. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  559. config >>= 1;
  560. evlist__for_each_entry(pt->session->evlist, evsel) {
  561. if (intel_pt_get_config(pt, &evsel->attr, &config))
  562. return (config & pt->mtc_freq_bits) >> shift;
  563. }
  564. return 0;
  565. }
  566. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  567. {
  568. struct perf_evsel *evsel;
  569. bool timeless_decoding = true;
  570. u64 config;
  571. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  572. return true;
  573. evlist__for_each_entry(pt->session->evlist, evsel) {
  574. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  575. return true;
  576. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  577. if (config & pt->tsc_bit)
  578. timeless_decoding = false;
  579. else
  580. return true;
  581. }
  582. }
  583. return timeless_decoding;
  584. }
  585. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  586. {
  587. struct perf_evsel *evsel;
  588. evlist__for_each_entry(pt->session->evlist, evsel) {
  589. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  590. !evsel->attr.exclude_kernel)
  591. return true;
  592. }
  593. return false;
  594. }
  595. static bool intel_pt_have_tsc(struct intel_pt *pt)
  596. {
  597. struct perf_evsel *evsel;
  598. bool have_tsc = false;
  599. u64 config;
  600. if (!pt->tsc_bit)
  601. return false;
  602. evlist__for_each_entry(pt->session->evlist, evsel) {
  603. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  604. if (config & pt->tsc_bit)
  605. have_tsc = true;
  606. else
  607. return false;
  608. }
  609. }
  610. return have_tsc;
  611. }
  612. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  613. {
  614. u64 quot, rem;
  615. quot = ns / pt->tc.time_mult;
  616. rem = ns % pt->tc.time_mult;
  617. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  618. pt->tc.time_mult;
  619. }
  620. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  621. unsigned int queue_nr)
  622. {
  623. struct intel_pt_params params = { .get_trace = 0, };
  624. struct perf_env *env = pt->machine->env;
  625. struct intel_pt_queue *ptq;
  626. ptq = zalloc(sizeof(struct intel_pt_queue));
  627. if (!ptq)
  628. return NULL;
  629. if (pt->synth_opts.callchain) {
  630. size_t sz = sizeof(struct ip_callchain);
  631. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  632. ptq->chain = zalloc(sz);
  633. if (!ptq->chain)
  634. goto out_free;
  635. }
  636. if (pt->synth_opts.last_branch) {
  637. size_t sz = sizeof(struct branch_stack);
  638. sz += pt->synth_opts.last_branch_sz *
  639. sizeof(struct branch_entry);
  640. ptq->last_branch = zalloc(sz);
  641. if (!ptq->last_branch)
  642. goto out_free;
  643. ptq->last_branch_rb = zalloc(sz);
  644. if (!ptq->last_branch_rb)
  645. goto out_free;
  646. }
  647. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  648. if (!ptq->event_buf)
  649. goto out_free;
  650. ptq->pt = pt;
  651. ptq->queue_nr = queue_nr;
  652. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  653. ptq->pid = -1;
  654. ptq->tid = -1;
  655. ptq->cpu = -1;
  656. ptq->next_tid = -1;
  657. params.get_trace = intel_pt_get_trace;
  658. params.walk_insn = intel_pt_walk_next_insn;
  659. params.data = ptq;
  660. params.return_compression = intel_pt_return_compression(pt);
  661. params.branch_enable = intel_pt_branch_enable(pt);
  662. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  663. params.mtc_period = intel_pt_mtc_period(pt);
  664. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  665. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  666. if (pt->filts.cnt > 0)
  667. params.pgd_ip = intel_pt_pgd_ip;
  668. if (pt->synth_opts.instructions) {
  669. if (pt->synth_opts.period) {
  670. switch (pt->synth_opts.period_type) {
  671. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  672. params.period_type =
  673. INTEL_PT_PERIOD_INSTRUCTIONS;
  674. params.period = pt->synth_opts.period;
  675. break;
  676. case PERF_ITRACE_PERIOD_TICKS:
  677. params.period_type = INTEL_PT_PERIOD_TICKS;
  678. params.period = pt->synth_opts.period;
  679. break;
  680. case PERF_ITRACE_PERIOD_NANOSECS:
  681. params.period_type = INTEL_PT_PERIOD_TICKS;
  682. params.period = intel_pt_ns_to_ticks(pt,
  683. pt->synth_opts.period);
  684. break;
  685. default:
  686. break;
  687. }
  688. }
  689. if (!params.period) {
  690. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  691. params.period = 1;
  692. }
  693. }
  694. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  695. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  696. ptq->decoder = intel_pt_decoder_new(&params);
  697. if (!ptq->decoder)
  698. goto out_free;
  699. return ptq;
  700. out_free:
  701. zfree(&ptq->event_buf);
  702. zfree(&ptq->last_branch);
  703. zfree(&ptq->last_branch_rb);
  704. zfree(&ptq->chain);
  705. free(ptq);
  706. return NULL;
  707. }
  708. static void intel_pt_free_queue(void *priv)
  709. {
  710. struct intel_pt_queue *ptq = priv;
  711. if (!ptq)
  712. return;
  713. thread__zput(ptq->thread);
  714. intel_pt_decoder_free(ptq->decoder);
  715. zfree(&ptq->event_buf);
  716. zfree(&ptq->last_branch);
  717. zfree(&ptq->last_branch_rb);
  718. zfree(&ptq->chain);
  719. free(ptq);
  720. }
  721. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  722. struct auxtrace_queue *queue)
  723. {
  724. struct intel_pt_queue *ptq = queue->priv;
  725. if (queue->tid == -1 || pt->have_sched_switch) {
  726. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  727. thread__zput(ptq->thread);
  728. }
  729. if (!ptq->thread && ptq->tid != -1)
  730. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  731. if (ptq->thread) {
  732. ptq->pid = ptq->thread->pid_;
  733. if (queue->cpu == -1)
  734. ptq->cpu = ptq->thread->cpu;
  735. }
  736. }
  737. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  738. {
  739. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  740. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  741. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  742. if (ptq->state->to_ip)
  743. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  744. PERF_IP_FLAG_ASYNC |
  745. PERF_IP_FLAG_INTERRUPT;
  746. else
  747. ptq->flags = PERF_IP_FLAG_BRANCH |
  748. PERF_IP_FLAG_TRACE_END;
  749. ptq->insn_len = 0;
  750. } else {
  751. if (ptq->state->from_ip)
  752. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  753. else
  754. ptq->flags = PERF_IP_FLAG_BRANCH |
  755. PERF_IP_FLAG_TRACE_BEGIN;
  756. if (ptq->state->flags & INTEL_PT_IN_TX)
  757. ptq->flags |= PERF_IP_FLAG_IN_TX;
  758. ptq->insn_len = ptq->state->insn_len;
  759. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  760. }
  761. }
  762. static int intel_pt_setup_queue(struct intel_pt *pt,
  763. struct auxtrace_queue *queue,
  764. unsigned int queue_nr)
  765. {
  766. struct intel_pt_queue *ptq = queue->priv;
  767. if (list_empty(&queue->head))
  768. return 0;
  769. if (!ptq) {
  770. ptq = intel_pt_alloc_queue(pt, queue_nr);
  771. if (!ptq)
  772. return -ENOMEM;
  773. queue->priv = ptq;
  774. if (queue->cpu != -1)
  775. ptq->cpu = queue->cpu;
  776. ptq->tid = queue->tid;
  777. if (pt->sampling_mode && !pt->snapshot_mode &&
  778. pt->timeless_decoding)
  779. ptq->step_through_buffers = true;
  780. ptq->sync_switch = pt->sync_switch;
  781. }
  782. if (!ptq->on_heap &&
  783. (!ptq->sync_switch ||
  784. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  785. const struct intel_pt_state *state;
  786. int ret;
  787. if (pt->timeless_decoding)
  788. return 0;
  789. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  790. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  791. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  792. while (1) {
  793. state = intel_pt_decode(ptq->decoder);
  794. if (state->err) {
  795. if (state->err == INTEL_PT_ERR_NODATA) {
  796. intel_pt_log("queue %u has no timestamp\n",
  797. queue_nr);
  798. return 0;
  799. }
  800. continue;
  801. }
  802. if (state->timestamp)
  803. break;
  804. }
  805. ptq->timestamp = state->timestamp;
  806. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  807. queue_nr, ptq->timestamp);
  808. ptq->state = state;
  809. ptq->have_sample = true;
  810. intel_pt_sample_flags(ptq);
  811. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  812. if (ret)
  813. return ret;
  814. ptq->on_heap = true;
  815. }
  816. return 0;
  817. }
  818. static int intel_pt_setup_queues(struct intel_pt *pt)
  819. {
  820. unsigned int i;
  821. int ret;
  822. for (i = 0; i < pt->queues.nr_queues; i++) {
  823. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  824. if (ret)
  825. return ret;
  826. }
  827. return 0;
  828. }
  829. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  830. {
  831. struct branch_stack *bs_src = ptq->last_branch_rb;
  832. struct branch_stack *bs_dst = ptq->last_branch;
  833. size_t nr = 0;
  834. bs_dst->nr = bs_src->nr;
  835. if (!bs_src->nr)
  836. return;
  837. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  838. memcpy(&bs_dst->entries[0],
  839. &bs_src->entries[ptq->last_branch_pos],
  840. sizeof(struct branch_entry) * nr);
  841. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  842. memcpy(&bs_dst->entries[nr],
  843. &bs_src->entries[0],
  844. sizeof(struct branch_entry) * ptq->last_branch_pos);
  845. }
  846. }
  847. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  848. {
  849. ptq->last_branch_pos = 0;
  850. ptq->last_branch_rb->nr = 0;
  851. }
  852. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  853. {
  854. const struct intel_pt_state *state = ptq->state;
  855. struct branch_stack *bs = ptq->last_branch_rb;
  856. struct branch_entry *be;
  857. if (!ptq->last_branch_pos)
  858. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  859. ptq->last_branch_pos -= 1;
  860. be = &bs->entries[ptq->last_branch_pos];
  861. be->from = state->from_ip;
  862. be->to = state->to_ip;
  863. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  864. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  865. /* No support for mispredict */
  866. be->flags.mispred = ptq->pt->mispred_all;
  867. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  868. bs->nr += 1;
  869. }
  870. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  871. {
  872. return pt->synth_opts.initial_skip &&
  873. pt->num_events++ < pt->synth_opts.initial_skip;
  874. }
  875. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  876. struct intel_pt_queue *ptq,
  877. union perf_event *event,
  878. struct perf_sample *sample)
  879. {
  880. if (!pt->timeless_decoding)
  881. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  882. sample->ip = ptq->state->from_ip;
  883. sample->cpumode = intel_pt_cpumode(pt, sample->ip);
  884. sample->pid = ptq->pid;
  885. sample->tid = ptq->tid;
  886. sample->addr = ptq->state->to_ip;
  887. sample->period = 1;
  888. sample->cpu = ptq->cpu;
  889. sample->flags = ptq->flags;
  890. sample->insn_len = ptq->insn_len;
  891. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  892. event->sample.header.type = PERF_RECORD_SAMPLE;
  893. event->sample.header.misc = sample->cpumode;
  894. event->sample.header.size = sizeof(struct perf_event_header);
  895. }
  896. static int intel_pt_inject_event(union perf_event *event,
  897. struct perf_sample *sample, u64 type)
  898. {
  899. event->header.size = perf_event__sample_event_size(sample, type, 0);
  900. return perf_event__synthesize_sample(event, type, 0, sample);
  901. }
  902. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  903. union perf_event *event,
  904. struct perf_sample *sample, u64 type)
  905. {
  906. if (!pt->synth_opts.inject)
  907. return 0;
  908. return intel_pt_inject_event(event, sample, type);
  909. }
  910. static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
  911. union perf_event *event,
  912. struct perf_sample *sample, u64 type)
  913. {
  914. int ret;
  915. ret = intel_pt_opt_inject(pt, event, sample, type);
  916. if (ret)
  917. return ret;
  918. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  919. if (ret)
  920. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  921. return ret;
  922. }
  923. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  924. {
  925. struct intel_pt *pt = ptq->pt;
  926. union perf_event *event = ptq->event_buf;
  927. struct perf_sample sample = { .ip = 0, };
  928. struct dummy_branch_stack {
  929. u64 nr;
  930. struct branch_entry entries;
  931. } dummy_bs;
  932. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  933. return 0;
  934. if (intel_pt_skip_event(pt))
  935. return 0;
  936. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  937. sample.id = ptq->pt->branches_id;
  938. sample.stream_id = ptq->pt->branches_id;
  939. /*
  940. * perf report cannot handle events without a branch stack when using
  941. * SORT_MODE__BRANCH so make a dummy one.
  942. */
  943. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  944. dummy_bs = (struct dummy_branch_stack){
  945. .nr = 1,
  946. .entries = {
  947. .from = sample.ip,
  948. .to = sample.addr,
  949. },
  950. };
  951. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  952. }
  953. return intel_pt_deliver_synth_b_event(pt, event, &sample,
  954. pt->branches_sample_type);
  955. }
  956. static void intel_pt_prep_sample(struct intel_pt *pt,
  957. struct intel_pt_queue *ptq,
  958. union perf_event *event,
  959. struct perf_sample *sample)
  960. {
  961. intel_pt_prep_b_sample(pt, ptq, event, sample);
  962. if (pt->synth_opts.callchain) {
  963. thread_stack__sample(ptq->thread, ptq->chain,
  964. pt->synth_opts.callchain_sz, sample->ip);
  965. sample->callchain = ptq->chain;
  966. }
  967. if (pt->synth_opts.last_branch) {
  968. intel_pt_copy_last_branch_rb(ptq);
  969. sample->branch_stack = ptq->last_branch;
  970. }
  971. }
  972. static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
  973. struct intel_pt_queue *ptq,
  974. union perf_event *event,
  975. struct perf_sample *sample,
  976. u64 type)
  977. {
  978. int ret;
  979. ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
  980. if (pt->synth_opts.last_branch)
  981. intel_pt_reset_last_branch_rb(ptq);
  982. return ret;
  983. }
  984. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  985. {
  986. struct intel_pt *pt = ptq->pt;
  987. union perf_event *event = ptq->event_buf;
  988. struct perf_sample sample = { .ip = 0, };
  989. if (intel_pt_skip_event(pt))
  990. return 0;
  991. intel_pt_prep_sample(pt, ptq, event, &sample);
  992. sample.id = ptq->pt->instructions_id;
  993. sample.stream_id = ptq->pt->instructions_id;
  994. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  995. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  996. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  997. pt->instructions_sample_type);
  998. }
  999. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  1000. {
  1001. struct intel_pt *pt = ptq->pt;
  1002. union perf_event *event = ptq->event_buf;
  1003. struct perf_sample sample = { .ip = 0, };
  1004. if (intel_pt_skip_event(pt))
  1005. return 0;
  1006. intel_pt_prep_sample(pt, ptq, event, &sample);
  1007. sample.id = ptq->pt->transactions_id;
  1008. sample.stream_id = ptq->pt->transactions_id;
  1009. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1010. pt->transactions_sample_type);
  1011. }
  1012. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1013. struct intel_pt_queue *ptq,
  1014. union perf_event *event,
  1015. struct perf_sample *sample)
  1016. {
  1017. intel_pt_prep_sample(pt, ptq, event, sample);
  1018. /*
  1019. * Zero IP is used to mean "trace start" but that is not the case for
  1020. * power or PTWRITE events with no IP, so clear the flags.
  1021. */
  1022. if (!sample->ip)
  1023. sample->flags = 0;
  1024. }
  1025. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1026. {
  1027. struct intel_pt *pt = ptq->pt;
  1028. union perf_event *event = ptq->event_buf;
  1029. struct perf_sample sample = { .ip = 0, };
  1030. struct perf_synth_intel_ptwrite raw;
  1031. if (intel_pt_skip_event(pt))
  1032. return 0;
  1033. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1034. sample.id = ptq->pt->ptwrites_id;
  1035. sample.stream_id = ptq->pt->ptwrites_id;
  1036. raw.flags = 0;
  1037. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1038. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1039. sample.raw_size = perf_synth__raw_size(raw);
  1040. sample.raw_data = perf_synth__raw_data(&raw);
  1041. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1042. pt->ptwrites_sample_type);
  1043. }
  1044. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1045. {
  1046. struct intel_pt *pt = ptq->pt;
  1047. union perf_event *event = ptq->event_buf;
  1048. struct perf_sample sample = { .ip = 0, };
  1049. struct perf_synth_intel_cbr raw;
  1050. u32 flags;
  1051. if (intel_pt_skip_event(pt))
  1052. return 0;
  1053. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1054. sample.id = ptq->pt->cbr_id;
  1055. sample.stream_id = ptq->pt->cbr_id;
  1056. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1057. raw.flags = cpu_to_le32(flags);
  1058. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1059. raw.reserved3 = 0;
  1060. sample.raw_size = perf_synth__raw_size(raw);
  1061. sample.raw_data = perf_synth__raw_data(&raw);
  1062. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1063. pt->pwr_events_sample_type);
  1064. }
  1065. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1066. {
  1067. struct intel_pt *pt = ptq->pt;
  1068. union perf_event *event = ptq->event_buf;
  1069. struct perf_sample sample = { .ip = 0, };
  1070. struct perf_synth_intel_mwait raw;
  1071. if (intel_pt_skip_event(pt))
  1072. return 0;
  1073. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1074. sample.id = ptq->pt->mwait_id;
  1075. sample.stream_id = ptq->pt->mwait_id;
  1076. raw.reserved = 0;
  1077. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1078. sample.raw_size = perf_synth__raw_size(raw);
  1079. sample.raw_data = perf_synth__raw_data(&raw);
  1080. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1081. pt->pwr_events_sample_type);
  1082. }
  1083. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1084. {
  1085. struct intel_pt *pt = ptq->pt;
  1086. union perf_event *event = ptq->event_buf;
  1087. struct perf_sample sample = { .ip = 0, };
  1088. struct perf_synth_intel_pwre raw;
  1089. if (intel_pt_skip_event(pt))
  1090. return 0;
  1091. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1092. sample.id = ptq->pt->pwre_id;
  1093. sample.stream_id = ptq->pt->pwre_id;
  1094. raw.reserved = 0;
  1095. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1096. sample.raw_size = perf_synth__raw_size(raw);
  1097. sample.raw_data = perf_synth__raw_data(&raw);
  1098. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1099. pt->pwr_events_sample_type);
  1100. }
  1101. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1102. {
  1103. struct intel_pt *pt = ptq->pt;
  1104. union perf_event *event = ptq->event_buf;
  1105. struct perf_sample sample = { .ip = 0, };
  1106. struct perf_synth_intel_exstop raw;
  1107. if (intel_pt_skip_event(pt))
  1108. return 0;
  1109. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1110. sample.id = ptq->pt->exstop_id;
  1111. sample.stream_id = ptq->pt->exstop_id;
  1112. raw.flags = 0;
  1113. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1114. sample.raw_size = perf_synth__raw_size(raw);
  1115. sample.raw_data = perf_synth__raw_data(&raw);
  1116. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1117. pt->pwr_events_sample_type);
  1118. }
  1119. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1120. {
  1121. struct intel_pt *pt = ptq->pt;
  1122. union perf_event *event = ptq->event_buf;
  1123. struct perf_sample sample = { .ip = 0, };
  1124. struct perf_synth_intel_pwrx raw;
  1125. if (intel_pt_skip_event(pt))
  1126. return 0;
  1127. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1128. sample.id = ptq->pt->pwrx_id;
  1129. sample.stream_id = ptq->pt->pwrx_id;
  1130. raw.reserved = 0;
  1131. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1132. sample.raw_size = perf_synth__raw_size(raw);
  1133. sample.raw_data = perf_synth__raw_data(&raw);
  1134. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1135. pt->pwr_events_sample_type);
  1136. }
  1137. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1138. pid_t pid, pid_t tid, u64 ip)
  1139. {
  1140. union perf_event event;
  1141. char msg[MAX_AUXTRACE_ERROR_MSG];
  1142. int err;
  1143. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1144. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1145. code, cpu, pid, tid, ip, msg);
  1146. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1147. if (err)
  1148. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1149. err);
  1150. return err;
  1151. }
  1152. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1153. {
  1154. struct auxtrace_queue *queue;
  1155. pid_t tid = ptq->next_tid;
  1156. int err;
  1157. if (tid == -1)
  1158. return 0;
  1159. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1160. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1161. queue = &pt->queues.queue_array[ptq->queue_nr];
  1162. intel_pt_set_pid_tid_cpu(pt, queue);
  1163. ptq->next_tid = -1;
  1164. return err;
  1165. }
  1166. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1167. {
  1168. struct intel_pt *pt = ptq->pt;
  1169. return ip == pt->switch_ip &&
  1170. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1171. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1172. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1173. }
  1174. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1175. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \
  1176. INTEL_PT_CBR_CHG)
  1177. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1178. {
  1179. const struct intel_pt_state *state = ptq->state;
  1180. struct intel_pt *pt = ptq->pt;
  1181. int err;
  1182. if (!ptq->have_sample)
  1183. return 0;
  1184. ptq->have_sample = false;
  1185. if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) {
  1186. if (state->type & INTEL_PT_CBR_CHG) {
  1187. err = intel_pt_synth_cbr_sample(ptq);
  1188. if (err)
  1189. return err;
  1190. }
  1191. if (state->type & INTEL_PT_MWAIT_OP) {
  1192. err = intel_pt_synth_mwait_sample(ptq);
  1193. if (err)
  1194. return err;
  1195. }
  1196. if (state->type & INTEL_PT_PWR_ENTRY) {
  1197. err = intel_pt_synth_pwre_sample(ptq);
  1198. if (err)
  1199. return err;
  1200. }
  1201. if (state->type & INTEL_PT_EX_STOP) {
  1202. err = intel_pt_synth_exstop_sample(ptq);
  1203. if (err)
  1204. return err;
  1205. }
  1206. if (state->type & INTEL_PT_PWR_EXIT) {
  1207. err = intel_pt_synth_pwrx_sample(ptq);
  1208. if (err)
  1209. return err;
  1210. }
  1211. }
  1212. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1213. err = intel_pt_synth_instruction_sample(ptq);
  1214. if (err)
  1215. return err;
  1216. }
  1217. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1218. err = intel_pt_synth_transaction_sample(ptq);
  1219. if (err)
  1220. return err;
  1221. }
  1222. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1223. err = intel_pt_synth_ptwrite_sample(ptq);
  1224. if (err)
  1225. return err;
  1226. }
  1227. if (!(state->type & INTEL_PT_BRANCH))
  1228. return 0;
  1229. if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
  1230. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1231. state->to_ip, ptq->insn_len,
  1232. state->trace_nr);
  1233. else
  1234. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1235. if (pt->sample_branches) {
  1236. err = intel_pt_synth_branch_sample(ptq);
  1237. if (err)
  1238. return err;
  1239. }
  1240. if (pt->synth_opts.last_branch)
  1241. intel_pt_update_last_branch_rb(ptq);
  1242. if (!ptq->sync_switch)
  1243. return 0;
  1244. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1245. switch (ptq->switch_state) {
  1246. case INTEL_PT_SS_NOT_TRACING:
  1247. case INTEL_PT_SS_UNKNOWN:
  1248. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1249. err = intel_pt_next_tid(pt, ptq);
  1250. if (err)
  1251. return err;
  1252. ptq->switch_state = INTEL_PT_SS_TRACING;
  1253. break;
  1254. default:
  1255. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1256. return 1;
  1257. }
  1258. } else if (!state->to_ip) {
  1259. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1260. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1261. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1262. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1263. state->to_ip == pt->ptss_ip &&
  1264. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1265. ptq->switch_state = INTEL_PT_SS_TRACING;
  1266. }
  1267. return 0;
  1268. }
  1269. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1270. {
  1271. struct machine *machine = pt->machine;
  1272. struct map *map;
  1273. struct symbol *sym, *start;
  1274. u64 ip, switch_ip = 0;
  1275. const char *ptss;
  1276. if (ptss_ip)
  1277. *ptss_ip = 0;
  1278. map = machine__kernel_map(machine);
  1279. if (!map)
  1280. return 0;
  1281. if (map__load(map))
  1282. return 0;
  1283. start = dso__first_symbol(map->dso);
  1284. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1285. if (sym->binding == STB_GLOBAL &&
  1286. !strcmp(sym->name, "__switch_to")) {
  1287. ip = map->unmap_ip(map, sym->start);
  1288. if (ip >= map->start && ip < map->end) {
  1289. switch_ip = ip;
  1290. break;
  1291. }
  1292. }
  1293. }
  1294. if (!switch_ip || !ptss_ip)
  1295. return 0;
  1296. if (pt->have_sched_switch == 1)
  1297. ptss = "perf_trace_sched_switch";
  1298. else
  1299. ptss = "__perf_event_task_sched_out";
  1300. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1301. if (!strcmp(sym->name, ptss)) {
  1302. ip = map->unmap_ip(map, sym->start);
  1303. if (ip >= map->start && ip < map->end) {
  1304. *ptss_ip = ip;
  1305. break;
  1306. }
  1307. }
  1308. }
  1309. return switch_ip;
  1310. }
  1311. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1312. {
  1313. unsigned int i;
  1314. pt->sync_switch = true;
  1315. for (i = 0; i < pt->queues.nr_queues; i++) {
  1316. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1317. struct intel_pt_queue *ptq = queue->priv;
  1318. if (ptq)
  1319. ptq->sync_switch = true;
  1320. }
  1321. }
  1322. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1323. {
  1324. const struct intel_pt_state *state = ptq->state;
  1325. struct intel_pt *pt = ptq->pt;
  1326. int err;
  1327. if (!pt->kernel_start) {
  1328. pt->kernel_start = machine__kernel_start(pt->machine);
  1329. if (pt->per_cpu_mmaps &&
  1330. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1331. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1332. !pt->sampling_mode) {
  1333. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1334. if (pt->switch_ip) {
  1335. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1336. pt->switch_ip, pt->ptss_ip);
  1337. intel_pt_enable_sync_switch(pt);
  1338. }
  1339. }
  1340. }
  1341. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1342. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1343. while (1) {
  1344. err = intel_pt_sample(ptq);
  1345. if (err)
  1346. return err;
  1347. state = intel_pt_decode(ptq->decoder);
  1348. if (state->err) {
  1349. if (state->err == INTEL_PT_ERR_NODATA)
  1350. return 1;
  1351. if (ptq->sync_switch &&
  1352. state->from_ip >= pt->kernel_start) {
  1353. ptq->sync_switch = false;
  1354. intel_pt_next_tid(pt, ptq);
  1355. }
  1356. if (pt->synth_opts.errors) {
  1357. err = intel_pt_synth_error(pt, state->err,
  1358. ptq->cpu, ptq->pid,
  1359. ptq->tid,
  1360. state->from_ip);
  1361. if (err)
  1362. return err;
  1363. }
  1364. continue;
  1365. }
  1366. ptq->state = state;
  1367. ptq->have_sample = true;
  1368. intel_pt_sample_flags(ptq);
  1369. /* Use estimated TSC upon return to user space */
  1370. if (pt->est_tsc &&
  1371. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1372. state->to_ip && state->to_ip < pt->kernel_start) {
  1373. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1374. state->timestamp, state->est_timestamp);
  1375. ptq->timestamp = state->est_timestamp;
  1376. /* Use estimated TSC in unknown switch state */
  1377. } else if (ptq->sync_switch &&
  1378. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1379. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1380. ptq->next_tid == -1) {
  1381. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1382. state->timestamp, state->est_timestamp);
  1383. ptq->timestamp = state->est_timestamp;
  1384. } else if (state->timestamp > ptq->timestamp) {
  1385. ptq->timestamp = state->timestamp;
  1386. }
  1387. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1388. *timestamp = ptq->timestamp;
  1389. return 0;
  1390. }
  1391. }
  1392. return 0;
  1393. }
  1394. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1395. {
  1396. if (pt->queues.new_data) {
  1397. pt->queues.new_data = false;
  1398. return intel_pt_setup_queues(pt);
  1399. }
  1400. return 0;
  1401. }
  1402. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1403. {
  1404. unsigned int queue_nr;
  1405. u64 ts;
  1406. int ret;
  1407. while (1) {
  1408. struct auxtrace_queue *queue;
  1409. struct intel_pt_queue *ptq;
  1410. if (!pt->heap.heap_cnt)
  1411. return 0;
  1412. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1413. return 0;
  1414. queue_nr = pt->heap.heap_array[0].queue_nr;
  1415. queue = &pt->queues.queue_array[queue_nr];
  1416. ptq = queue->priv;
  1417. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1418. queue_nr, pt->heap.heap_array[0].ordinal,
  1419. timestamp);
  1420. auxtrace_heap__pop(&pt->heap);
  1421. if (pt->heap.heap_cnt) {
  1422. ts = pt->heap.heap_array[0].ordinal + 1;
  1423. if (ts > timestamp)
  1424. ts = timestamp;
  1425. } else {
  1426. ts = timestamp;
  1427. }
  1428. intel_pt_set_pid_tid_cpu(pt, queue);
  1429. ret = intel_pt_run_decoder(ptq, &ts);
  1430. if (ret < 0) {
  1431. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1432. return ret;
  1433. }
  1434. if (!ret) {
  1435. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1436. if (ret < 0)
  1437. return ret;
  1438. } else {
  1439. ptq->on_heap = false;
  1440. }
  1441. }
  1442. return 0;
  1443. }
  1444. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1445. u64 time_)
  1446. {
  1447. struct auxtrace_queues *queues = &pt->queues;
  1448. unsigned int i;
  1449. u64 ts = 0;
  1450. for (i = 0; i < queues->nr_queues; i++) {
  1451. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1452. struct intel_pt_queue *ptq = queue->priv;
  1453. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1454. ptq->time = time_;
  1455. intel_pt_set_pid_tid_cpu(pt, queue);
  1456. intel_pt_run_decoder(ptq, &ts);
  1457. }
  1458. }
  1459. return 0;
  1460. }
  1461. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1462. {
  1463. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1464. sample->pid, sample->tid, 0);
  1465. }
  1466. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1467. {
  1468. unsigned i, j;
  1469. if (cpu < 0 || !pt->queues.nr_queues)
  1470. return NULL;
  1471. if ((unsigned)cpu >= pt->queues.nr_queues)
  1472. i = pt->queues.nr_queues - 1;
  1473. else
  1474. i = cpu;
  1475. if (pt->queues.queue_array[i].cpu == cpu)
  1476. return pt->queues.queue_array[i].priv;
  1477. for (j = 0; i > 0; j++) {
  1478. if (pt->queues.queue_array[--i].cpu == cpu)
  1479. return pt->queues.queue_array[i].priv;
  1480. }
  1481. for (; j < pt->queues.nr_queues; j++) {
  1482. if (pt->queues.queue_array[j].cpu == cpu)
  1483. return pt->queues.queue_array[j].priv;
  1484. }
  1485. return NULL;
  1486. }
  1487. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1488. u64 timestamp)
  1489. {
  1490. struct intel_pt_queue *ptq;
  1491. int err;
  1492. if (!pt->sync_switch)
  1493. return 1;
  1494. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1495. if (!ptq || !ptq->sync_switch)
  1496. return 1;
  1497. switch (ptq->switch_state) {
  1498. case INTEL_PT_SS_NOT_TRACING:
  1499. ptq->next_tid = -1;
  1500. break;
  1501. case INTEL_PT_SS_UNKNOWN:
  1502. case INTEL_PT_SS_TRACING:
  1503. ptq->next_tid = tid;
  1504. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1505. return 0;
  1506. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1507. if (!ptq->on_heap) {
  1508. ptq->timestamp = perf_time_to_tsc(timestamp,
  1509. &pt->tc);
  1510. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1511. ptq->timestamp);
  1512. if (err)
  1513. return err;
  1514. ptq->on_heap = true;
  1515. }
  1516. ptq->switch_state = INTEL_PT_SS_TRACING;
  1517. break;
  1518. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1519. ptq->next_tid = tid;
  1520. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1521. break;
  1522. default:
  1523. break;
  1524. }
  1525. return 1;
  1526. }
  1527. static int intel_pt_process_switch(struct intel_pt *pt,
  1528. struct perf_sample *sample)
  1529. {
  1530. struct perf_evsel *evsel;
  1531. pid_t tid;
  1532. int cpu, ret;
  1533. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1534. if (evsel != pt->switch_evsel)
  1535. return 0;
  1536. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1537. cpu = sample->cpu;
  1538. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1539. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1540. &pt->tc));
  1541. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1542. if (ret <= 0)
  1543. return ret;
  1544. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1545. }
  1546. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1547. struct perf_sample *sample)
  1548. {
  1549. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1550. pid_t pid, tid;
  1551. int cpu, ret;
  1552. cpu = sample->cpu;
  1553. if (pt->have_sched_switch == 3) {
  1554. if (!out)
  1555. return 0;
  1556. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1557. pr_err("Expecting CPU-wide context switch event\n");
  1558. return -EINVAL;
  1559. }
  1560. pid = event->context_switch.next_prev_pid;
  1561. tid = event->context_switch.next_prev_tid;
  1562. } else {
  1563. if (out)
  1564. return 0;
  1565. pid = sample->pid;
  1566. tid = sample->tid;
  1567. }
  1568. if (tid == -1) {
  1569. pr_err("context_switch event has no tid\n");
  1570. return -EINVAL;
  1571. }
  1572. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1573. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1574. &pt->tc));
  1575. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1576. if (ret <= 0)
  1577. return ret;
  1578. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1579. }
  1580. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1581. union perf_event *event,
  1582. struct perf_sample *sample)
  1583. {
  1584. if (!pt->per_cpu_mmaps)
  1585. return 0;
  1586. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1587. sample->cpu, event->itrace_start.pid,
  1588. event->itrace_start.tid, sample->time,
  1589. perf_time_to_tsc(sample->time, &pt->tc));
  1590. return machine__set_current_tid(pt->machine, sample->cpu,
  1591. event->itrace_start.pid,
  1592. event->itrace_start.tid);
  1593. }
  1594. static int intel_pt_process_event(struct perf_session *session,
  1595. union perf_event *event,
  1596. struct perf_sample *sample,
  1597. struct perf_tool *tool)
  1598. {
  1599. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1600. auxtrace);
  1601. u64 timestamp;
  1602. int err = 0;
  1603. if (dump_trace)
  1604. return 0;
  1605. if (!tool->ordered_events) {
  1606. pr_err("Intel Processor Trace requires ordered events\n");
  1607. return -EINVAL;
  1608. }
  1609. if (sample->time && sample->time != (u64)-1)
  1610. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1611. else
  1612. timestamp = 0;
  1613. if (timestamp || pt->timeless_decoding) {
  1614. err = intel_pt_update_queues(pt);
  1615. if (err)
  1616. return err;
  1617. }
  1618. if (pt->timeless_decoding) {
  1619. if (event->header.type == PERF_RECORD_EXIT) {
  1620. err = intel_pt_process_timeless_queues(pt,
  1621. event->fork.tid,
  1622. sample->time);
  1623. }
  1624. } else if (timestamp) {
  1625. err = intel_pt_process_queues(pt, timestamp);
  1626. }
  1627. if (err)
  1628. return err;
  1629. if (event->header.type == PERF_RECORD_AUX &&
  1630. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1631. pt->synth_opts.errors) {
  1632. err = intel_pt_lost(pt, sample);
  1633. if (err)
  1634. return err;
  1635. }
  1636. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1637. err = intel_pt_process_switch(pt, sample);
  1638. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1639. err = intel_pt_process_itrace_start(pt, event, sample);
  1640. else if (event->header.type == PERF_RECORD_SWITCH ||
  1641. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1642. err = intel_pt_context_switch(pt, event, sample);
  1643. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1644. perf_event__name(event->header.type), event->header.type,
  1645. sample->cpu, sample->time, timestamp);
  1646. return err;
  1647. }
  1648. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1649. {
  1650. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1651. auxtrace);
  1652. int ret;
  1653. if (dump_trace)
  1654. return 0;
  1655. if (!tool->ordered_events)
  1656. return -EINVAL;
  1657. ret = intel_pt_update_queues(pt);
  1658. if (ret < 0)
  1659. return ret;
  1660. if (pt->timeless_decoding)
  1661. return intel_pt_process_timeless_queues(pt, -1,
  1662. MAX_TIMESTAMP - 1);
  1663. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1664. }
  1665. static void intel_pt_free_events(struct perf_session *session)
  1666. {
  1667. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1668. auxtrace);
  1669. struct auxtrace_queues *queues = &pt->queues;
  1670. unsigned int i;
  1671. for (i = 0; i < queues->nr_queues; i++) {
  1672. intel_pt_free_queue(queues->queue_array[i].priv);
  1673. queues->queue_array[i].priv = NULL;
  1674. }
  1675. intel_pt_log_disable();
  1676. auxtrace_queues__free(queues);
  1677. }
  1678. static void intel_pt_free(struct perf_session *session)
  1679. {
  1680. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1681. auxtrace);
  1682. auxtrace_heap__free(&pt->heap);
  1683. intel_pt_free_events(session);
  1684. session->auxtrace = NULL;
  1685. thread__put(pt->unknown_thread);
  1686. addr_filters__exit(&pt->filts);
  1687. zfree(&pt->filter);
  1688. free(pt);
  1689. }
  1690. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1691. union perf_event *event,
  1692. struct perf_tool *tool __maybe_unused)
  1693. {
  1694. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1695. auxtrace);
  1696. if (!pt->data_queued) {
  1697. struct auxtrace_buffer *buffer;
  1698. off_t data_offset;
  1699. int fd = perf_data__fd(session->data);
  1700. int err;
  1701. if (perf_data__is_pipe(session->data)) {
  1702. data_offset = 0;
  1703. } else {
  1704. data_offset = lseek(fd, 0, SEEK_CUR);
  1705. if (data_offset == -1)
  1706. return -errno;
  1707. }
  1708. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1709. data_offset, &buffer);
  1710. if (err)
  1711. return err;
  1712. /* Dump here now we have copied a piped trace out of the pipe */
  1713. if (dump_trace) {
  1714. if (auxtrace_buffer__get_data(buffer, fd)) {
  1715. intel_pt_dump_event(pt, buffer->data,
  1716. buffer->size);
  1717. auxtrace_buffer__put_data(buffer);
  1718. }
  1719. }
  1720. }
  1721. return 0;
  1722. }
  1723. struct intel_pt_synth {
  1724. struct perf_tool dummy_tool;
  1725. struct perf_session *session;
  1726. };
  1727. static int intel_pt_event_synth(struct perf_tool *tool,
  1728. union perf_event *event,
  1729. struct perf_sample *sample __maybe_unused,
  1730. struct machine *machine __maybe_unused)
  1731. {
  1732. struct intel_pt_synth *intel_pt_synth =
  1733. container_of(tool, struct intel_pt_synth, dummy_tool);
  1734. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1735. NULL);
  1736. }
  1737. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  1738. struct perf_event_attr *attr, u64 id)
  1739. {
  1740. struct intel_pt_synth intel_pt_synth;
  1741. int err;
  1742. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1743. name, id, (u64)attr->sample_type);
  1744. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1745. intel_pt_synth.session = session;
  1746. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1747. &id, intel_pt_event_synth);
  1748. if (err)
  1749. pr_err("%s: failed to synthesize '%s' event type\n",
  1750. __func__, name);
  1751. return err;
  1752. }
  1753. static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id,
  1754. const char *name)
  1755. {
  1756. struct perf_evsel *evsel;
  1757. evlist__for_each_entry(evlist, evsel) {
  1758. if (evsel->id && evsel->id[0] == id) {
  1759. if (evsel->name)
  1760. zfree(&evsel->name);
  1761. evsel->name = strdup(name);
  1762. break;
  1763. }
  1764. }
  1765. }
  1766. static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt,
  1767. struct perf_evlist *evlist)
  1768. {
  1769. struct perf_evsel *evsel;
  1770. evlist__for_each_entry(evlist, evsel) {
  1771. if (evsel->attr.type == pt->pmu_type && evsel->ids)
  1772. return evsel;
  1773. }
  1774. return NULL;
  1775. }
  1776. static int intel_pt_synth_events(struct intel_pt *pt,
  1777. struct perf_session *session)
  1778. {
  1779. struct perf_evlist *evlist = session->evlist;
  1780. struct perf_evsel *evsel = intel_pt_evsel(pt, evlist);
  1781. struct perf_event_attr attr;
  1782. u64 id;
  1783. int err;
  1784. if (!evsel) {
  1785. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1786. return 0;
  1787. }
  1788. memset(&attr, 0, sizeof(struct perf_event_attr));
  1789. attr.size = sizeof(struct perf_event_attr);
  1790. attr.type = PERF_TYPE_HARDWARE;
  1791. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1792. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1793. PERF_SAMPLE_PERIOD;
  1794. if (pt->timeless_decoding)
  1795. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1796. else
  1797. attr.sample_type |= PERF_SAMPLE_TIME;
  1798. if (!pt->per_cpu_mmaps)
  1799. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1800. attr.exclude_user = evsel->attr.exclude_user;
  1801. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1802. attr.exclude_hv = evsel->attr.exclude_hv;
  1803. attr.exclude_host = evsel->attr.exclude_host;
  1804. attr.exclude_guest = evsel->attr.exclude_guest;
  1805. attr.sample_id_all = evsel->attr.sample_id_all;
  1806. attr.read_format = evsel->attr.read_format;
  1807. id = evsel->id[0] + 1000000000;
  1808. if (!id)
  1809. id = 1;
  1810. if (pt->synth_opts.branches) {
  1811. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1812. attr.sample_period = 1;
  1813. attr.sample_type |= PERF_SAMPLE_ADDR;
  1814. err = intel_pt_synth_event(session, "branches", &attr, id);
  1815. if (err)
  1816. return err;
  1817. pt->sample_branches = true;
  1818. pt->branches_sample_type = attr.sample_type;
  1819. pt->branches_id = id;
  1820. id += 1;
  1821. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  1822. }
  1823. if (pt->synth_opts.callchain)
  1824. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1825. if (pt->synth_opts.last_branch)
  1826. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1827. if (pt->synth_opts.instructions) {
  1828. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1829. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1830. attr.sample_period =
  1831. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1832. else
  1833. attr.sample_period = pt->synth_opts.period;
  1834. err = intel_pt_synth_event(session, "instructions", &attr, id);
  1835. if (err)
  1836. return err;
  1837. pt->sample_instructions = true;
  1838. pt->instructions_sample_type = attr.sample_type;
  1839. pt->instructions_id = id;
  1840. id += 1;
  1841. }
  1842. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  1843. attr.sample_period = 1;
  1844. if (pt->synth_opts.transactions) {
  1845. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1846. err = intel_pt_synth_event(session, "transactions", &attr, id);
  1847. if (err)
  1848. return err;
  1849. pt->sample_transactions = true;
  1850. pt->transactions_sample_type = attr.sample_type;
  1851. pt->transactions_id = id;
  1852. intel_pt_set_event_name(evlist, id, "transactions");
  1853. id += 1;
  1854. }
  1855. attr.type = PERF_TYPE_SYNTH;
  1856. attr.sample_type |= PERF_SAMPLE_RAW;
  1857. if (pt->synth_opts.ptwrites) {
  1858. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  1859. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  1860. if (err)
  1861. return err;
  1862. pt->sample_ptwrites = true;
  1863. pt->ptwrites_sample_type = attr.sample_type;
  1864. pt->ptwrites_id = id;
  1865. intel_pt_set_event_name(evlist, id, "ptwrite");
  1866. id += 1;
  1867. }
  1868. if (pt->synth_opts.pwr_events) {
  1869. pt->sample_pwr_events = true;
  1870. pt->pwr_events_sample_type = attr.sample_type;
  1871. attr.config = PERF_SYNTH_INTEL_CBR;
  1872. err = intel_pt_synth_event(session, "cbr", &attr, id);
  1873. if (err)
  1874. return err;
  1875. pt->cbr_id = id;
  1876. intel_pt_set_event_name(evlist, id, "cbr");
  1877. id += 1;
  1878. }
  1879. if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) {
  1880. attr.config = PERF_SYNTH_INTEL_MWAIT;
  1881. err = intel_pt_synth_event(session, "mwait", &attr, id);
  1882. if (err)
  1883. return err;
  1884. pt->mwait_id = id;
  1885. intel_pt_set_event_name(evlist, id, "mwait");
  1886. id += 1;
  1887. attr.config = PERF_SYNTH_INTEL_PWRE;
  1888. err = intel_pt_synth_event(session, "pwre", &attr, id);
  1889. if (err)
  1890. return err;
  1891. pt->pwre_id = id;
  1892. intel_pt_set_event_name(evlist, id, "pwre");
  1893. id += 1;
  1894. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  1895. err = intel_pt_synth_event(session, "exstop", &attr, id);
  1896. if (err)
  1897. return err;
  1898. pt->exstop_id = id;
  1899. intel_pt_set_event_name(evlist, id, "exstop");
  1900. id += 1;
  1901. attr.config = PERF_SYNTH_INTEL_PWRX;
  1902. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  1903. if (err)
  1904. return err;
  1905. pt->pwrx_id = id;
  1906. intel_pt_set_event_name(evlist, id, "pwrx");
  1907. id += 1;
  1908. }
  1909. return 0;
  1910. }
  1911. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1912. {
  1913. struct perf_evsel *evsel;
  1914. evlist__for_each_entry_reverse(evlist, evsel) {
  1915. const char *name = perf_evsel__name(evsel);
  1916. if (!strcmp(name, "sched:sched_switch"))
  1917. return evsel;
  1918. }
  1919. return NULL;
  1920. }
  1921. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1922. {
  1923. struct perf_evsel *evsel;
  1924. evlist__for_each_entry(evlist, evsel) {
  1925. if (evsel->attr.context_switch)
  1926. return true;
  1927. }
  1928. return false;
  1929. }
  1930. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1931. {
  1932. struct intel_pt *pt = data;
  1933. if (!strcmp(var, "intel-pt.mispred-all"))
  1934. pt->mispred_all = perf_config_bool(var, value);
  1935. return 0;
  1936. }
  1937. static const char * const intel_pt_info_fmts[] = {
  1938. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1939. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1940. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1941. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1942. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1943. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1944. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1945. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1946. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1947. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1948. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1949. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1950. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1951. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1952. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  1953. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  1954. };
  1955. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1956. {
  1957. int i;
  1958. if (!dump_trace)
  1959. return;
  1960. for (i = start; i <= finish; i++)
  1961. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1962. }
  1963. static void intel_pt_print_info_str(const char *name, const char *str)
  1964. {
  1965. if (!dump_trace)
  1966. return;
  1967. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  1968. }
  1969. static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos)
  1970. {
  1971. return auxtrace_info->header.size >=
  1972. sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1));
  1973. }
  1974. int intel_pt_process_auxtrace_info(union perf_event *event,
  1975. struct perf_session *session)
  1976. {
  1977. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1978. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1979. struct intel_pt *pt;
  1980. void *info_end;
  1981. u64 *info;
  1982. int err;
  1983. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1984. min_sz)
  1985. return -EINVAL;
  1986. pt = zalloc(sizeof(struct intel_pt));
  1987. if (!pt)
  1988. return -ENOMEM;
  1989. addr_filters__init(&pt->filts);
  1990. err = perf_config(intel_pt_perf_config, pt);
  1991. if (err)
  1992. goto err_free;
  1993. err = auxtrace_queues__init(&pt->queues);
  1994. if (err)
  1995. goto err_free;
  1996. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1997. pt->session = session;
  1998. pt->machine = &session->machines.host; /* No kvm support */
  1999. pt->auxtrace_type = auxtrace_info->type;
  2000. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  2001. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  2002. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  2003. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  2004. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2005. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2006. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2007. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2008. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2009. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2010. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2011. INTEL_PT_PER_CPU_MMAPS);
  2012. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2013. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2014. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2015. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2016. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2017. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2018. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2019. INTEL_PT_CYC_BIT);
  2020. }
  2021. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2022. pt->max_non_turbo_ratio =
  2023. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2024. intel_pt_print_info(&auxtrace_info->priv[0],
  2025. INTEL_PT_MAX_NONTURBO_RATIO,
  2026. INTEL_PT_MAX_NONTURBO_RATIO);
  2027. }
  2028. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2029. info_end = (void *)info + auxtrace_info->header.size;
  2030. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2031. size_t len;
  2032. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2033. intel_pt_print_info(&auxtrace_info->priv[0],
  2034. INTEL_PT_FILTER_STR_LEN,
  2035. INTEL_PT_FILTER_STR_LEN);
  2036. if (len) {
  2037. const char *filter = (const char *)info;
  2038. len = roundup(len + 1, 8);
  2039. info += len >> 3;
  2040. if ((void *)info > info_end) {
  2041. pr_err("%s: bad filter string length\n", __func__);
  2042. err = -EINVAL;
  2043. goto err_free_queues;
  2044. }
  2045. pt->filter = memdup(filter, len);
  2046. if (!pt->filter) {
  2047. err = -ENOMEM;
  2048. goto err_free_queues;
  2049. }
  2050. if (session->header.needs_swap)
  2051. mem_bswap_64(pt->filter, len);
  2052. if (pt->filter[len - 1]) {
  2053. pr_err("%s: filter string not null terminated\n", __func__);
  2054. err = -EINVAL;
  2055. goto err_free_queues;
  2056. }
  2057. err = addr_filters__parse_bare_filter(&pt->filts,
  2058. filter);
  2059. if (err)
  2060. goto err_free_queues;
  2061. }
  2062. intel_pt_print_info_str("Filter string", pt->filter);
  2063. }
  2064. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2065. pt->have_tsc = intel_pt_have_tsc(pt);
  2066. pt->sampling_mode = false;
  2067. pt->est_tsc = !pt->timeless_decoding;
  2068. pt->unknown_thread = thread__new(999999999, 999999999);
  2069. if (!pt->unknown_thread) {
  2070. err = -ENOMEM;
  2071. goto err_free_queues;
  2072. }
  2073. /*
  2074. * Since this thread will not be kept in any rbtree not in a
  2075. * list, initialize its list node so that at thread__put() the
  2076. * current thread lifetime assuption is kept and we don't segfault
  2077. * at list_del_init().
  2078. */
  2079. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2080. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2081. if (err)
  2082. goto err_delete_thread;
  2083. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  2084. err = -ENOMEM;
  2085. goto err_delete_thread;
  2086. }
  2087. pt->auxtrace.process_event = intel_pt_process_event;
  2088. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2089. pt->auxtrace.flush_events = intel_pt_flush;
  2090. pt->auxtrace.free_events = intel_pt_free_events;
  2091. pt->auxtrace.free = intel_pt_free;
  2092. session->auxtrace = &pt->auxtrace;
  2093. if (dump_trace)
  2094. return 0;
  2095. if (pt->have_sched_switch == 1) {
  2096. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2097. if (!pt->switch_evsel) {
  2098. pr_err("%s: missing sched_switch event\n", __func__);
  2099. err = -EINVAL;
  2100. goto err_delete_thread;
  2101. }
  2102. } else if (pt->have_sched_switch == 2 &&
  2103. !intel_pt_find_switch(session->evlist)) {
  2104. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2105. err = -EINVAL;
  2106. goto err_delete_thread;
  2107. }
  2108. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  2109. pt->synth_opts = *session->itrace_synth_opts;
  2110. } else {
  2111. itrace_synth_opts__set_default(&pt->synth_opts);
  2112. if (use_browser != -1) {
  2113. pt->synth_opts.branches = false;
  2114. pt->synth_opts.callchain = true;
  2115. }
  2116. if (session->itrace_synth_opts)
  2117. pt->synth_opts.thread_stack =
  2118. session->itrace_synth_opts->thread_stack;
  2119. }
  2120. if (pt->synth_opts.log)
  2121. intel_pt_log_enable();
  2122. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2123. if (pt->tc.time_mult) {
  2124. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2125. if (!pt->max_non_turbo_ratio)
  2126. pt->max_non_turbo_ratio =
  2127. (tsc_freq + 50000000) / 100000000;
  2128. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2129. intel_pt_log("Maximum non-turbo ratio %u\n",
  2130. pt->max_non_turbo_ratio);
  2131. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2132. }
  2133. if (pt->synth_opts.calls)
  2134. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2135. PERF_IP_FLAG_TRACE_END;
  2136. if (pt->synth_opts.returns)
  2137. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2138. PERF_IP_FLAG_TRACE_BEGIN;
  2139. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  2140. symbol_conf.use_callchain = true;
  2141. if (callchain_register_param(&callchain_param) < 0) {
  2142. symbol_conf.use_callchain = false;
  2143. pt->synth_opts.callchain = false;
  2144. }
  2145. }
  2146. err = intel_pt_synth_events(pt, session);
  2147. if (err)
  2148. goto err_delete_thread;
  2149. err = auxtrace_queues__process_index(&pt->queues, session);
  2150. if (err)
  2151. goto err_delete_thread;
  2152. if (pt->queues.populated)
  2153. pt->data_queued = true;
  2154. if (pt->timeless_decoding)
  2155. pr_debug2("Intel PT decoding without timestamps\n");
  2156. return 0;
  2157. err_delete_thread:
  2158. thread__zput(pt->unknown_thread);
  2159. err_free_queues:
  2160. intel_pt_log_disable();
  2161. auxtrace_queues__free(&pt->queues);
  2162. session->auxtrace = NULL;
  2163. err_free:
  2164. addr_filters__exit(&pt->filts);
  2165. zfree(&pt->filter);
  2166. free(pt);
  2167. return err;
  2168. }