haps_hs_idu.dts 1.7 KB

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  1. /*
  2. * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. /include/ "skeleton_hs_idu.dtsi"
  10. / {
  11. model = "snps,zebu_hs-smp";
  12. compatible = "snps,zebu_hs";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. interrupt-parent = <&core_intc>;
  16. memory {
  17. device_type = "memory";
  18. reg = <0x80000000 0x20000000>; /* 512 */
  19. };
  20. chosen {
  21. bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug";
  22. };
  23. aliases {
  24. serial0 = &uart0;
  25. };
  26. fpga {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. /* child and parent address space 1:1 mapped */
  31. ranges;
  32. core_clk: core_clk {
  33. #clock-cells = <0>;
  34. compatible = "fixed-clock";
  35. clock-frequency = <50000000>; /* 50 MHZ */
  36. };
  37. core_intc: interrupt-controller {
  38. compatible = "snps,archs-intc";
  39. interrupt-controller;
  40. #interrupt-cells = <1>;
  41. /* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
  42. };
  43. idu_intc: idu-interrupt-controller {
  44. compatible = "snps,archs-idu-intc";
  45. interrupt-controller;
  46. interrupt-parent = <&core_intc>;
  47. #interrupt-cells = <1>;
  48. };
  49. uart0: serial@f0000000 {
  50. /* compatible = "ns8250"; Doesn't use FIFOs */
  51. compatible = "ns16550a";
  52. reg = <0xf0000000 0x2000>;
  53. interrupt-parent = <&idu_intc>;
  54. interrupts = <0>;
  55. clock-frequency = <50000000>;
  56. baud = <115200>;
  57. reg-shift = <2>;
  58. reg-io-width = <4>;
  59. no-loopback-test = <1>;
  60. };
  61. arcpct0: pct {
  62. compatible = "snps,archs-pct";
  63. #interrupt-cells = <1>;
  64. interrupts = <20>;
  65. };
  66. };
  67. };