qede_main.c 54 KB

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  1. /* QLogic qede NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/pci.h>
  34. #include <linux/version.h>
  35. #include <linux/device.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/skbuff.h>
  39. #include <linux/errno.h>
  40. #include <linux/list.h>
  41. #include <linux/string.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/interrupt.h>
  44. #include <asm/byteorder.h>
  45. #include <asm/param.h>
  46. #include <linux/io.h>
  47. #include <linux/netdev_features.h>
  48. #include <linux/udp.h>
  49. #include <linux/tcp.h>
  50. #include <net/udp_tunnel.h>
  51. #include <linux/ip.h>
  52. #include <net/ipv6.h>
  53. #include <net/tcp.h>
  54. #include <linux/if_ether.h>
  55. #include <linux/if_vlan.h>
  56. #include <linux/pkt_sched.h>
  57. #include <linux/ethtool.h>
  58. #include <linux/in.h>
  59. #include <linux/random.h>
  60. #include <net/ip6_checksum.h>
  61. #include <linux/bitops.h>
  62. #include <linux/vmalloc.h>
  63. #include <linux/qed/qede_roce.h>
  64. #include "qede.h"
  65. #include "qede_ptp.h"
  66. static char version[] =
  67. "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
  68. MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
  69. MODULE_LICENSE("GPL");
  70. MODULE_VERSION(DRV_MODULE_VERSION);
  71. static uint debug;
  72. module_param(debug, uint, 0);
  73. MODULE_PARM_DESC(debug, " Default debug msglevel");
  74. static const struct qed_eth_ops *qed_ops;
  75. #define CHIP_NUM_57980S_40 0x1634
  76. #define CHIP_NUM_57980S_10 0x1666
  77. #define CHIP_NUM_57980S_MF 0x1636
  78. #define CHIP_NUM_57980S_100 0x1644
  79. #define CHIP_NUM_57980S_50 0x1654
  80. #define CHIP_NUM_57980S_25 0x1656
  81. #define CHIP_NUM_57980S_IOV 0x1664
  82. #define CHIP_NUM_AH 0x8070
  83. #define CHIP_NUM_AH_IOV 0x8090
  84. #ifndef PCI_DEVICE_ID_NX2_57980E
  85. #define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
  86. #define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
  87. #define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
  88. #define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
  89. #define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
  90. #define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
  91. #define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
  92. #define PCI_DEVICE_ID_AH CHIP_NUM_AH
  93. #define PCI_DEVICE_ID_AH_IOV CHIP_NUM_AH_IOV
  94. #endif
  95. enum qede_pci_private {
  96. QEDE_PRIVATE_PF,
  97. QEDE_PRIVATE_VF
  98. };
  99. static const struct pci_device_id qede_pci_tbl[] = {
  100. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
  101. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
  102. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
  103. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
  104. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
  105. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
  106. #ifdef CONFIG_QED_SRIOV
  107. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
  108. #endif
  109. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH), QEDE_PRIVATE_PF},
  110. #ifdef CONFIG_QED_SRIOV
  111. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH_IOV), QEDE_PRIVATE_VF},
  112. #endif
  113. { 0 }
  114. };
  115. MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
  116. static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
  117. #define TX_TIMEOUT (5 * HZ)
  118. /* Utilize last protocol index for XDP */
  119. #define XDP_PI 11
  120. static void qede_remove(struct pci_dev *pdev);
  121. static void qede_shutdown(struct pci_dev *pdev);
  122. static void qede_link_update(void *dev, struct qed_link_output *link);
  123. /* The qede lock is used to protect driver state change and driver flows that
  124. * are not reentrant.
  125. */
  126. void __qede_lock(struct qede_dev *edev)
  127. {
  128. mutex_lock(&edev->qede_lock);
  129. }
  130. void __qede_unlock(struct qede_dev *edev)
  131. {
  132. mutex_unlock(&edev->qede_lock);
  133. }
  134. #ifdef CONFIG_QED_SRIOV
  135. static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
  136. __be16 vlan_proto)
  137. {
  138. struct qede_dev *edev = netdev_priv(ndev);
  139. if (vlan > 4095) {
  140. DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
  141. return -EINVAL;
  142. }
  143. if (vlan_proto != htons(ETH_P_8021Q))
  144. return -EPROTONOSUPPORT;
  145. DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
  146. vlan, vf);
  147. return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
  148. }
  149. static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
  150. {
  151. struct qede_dev *edev = netdev_priv(ndev);
  152. DP_VERBOSE(edev, QED_MSG_IOV,
  153. "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
  154. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
  155. if (!is_valid_ether_addr(mac)) {
  156. DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
  157. return -EINVAL;
  158. }
  159. return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
  160. }
  161. static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
  162. {
  163. struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
  164. struct qed_dev_info *qed_info = &edev->dev_info.common;
  165. struct qed_update_vport_params *vport_params;
  166. int rc;
  167. vport_params = vzalloc(sizeof(*vport_params));
  168. if (!vport_params)
  169. return -ENOMEM;
  170. DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
  171. rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
  172. /* Enable/Disable Tx switching for PF */
  173. if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
  174. qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
  175. vport_params->vport_id = 0;
  176. vport_params->update_tx_switching_flg = 1;
  177. vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
  178. edev->ops->vport_update(edev->cdev, vport_params);
  179. }
  180. vfree(vport_params);
  181. return rc;
  182. }
  183. #endif
  184. static struct pci_driver qede_pci_driver = {
  185. .name = "qede",
  186. .id_table = qede_pci_tbl,
  187. .probe = qede_probe,
  188. .remove = qede_remove,
  189. .shutdown = qede_shutdown,
  190. #ifdef CONFIG_QED_SRIOV
  191. .sriov_configure = qede_sriov_configure,
  192. #endif
  193. };
  194. static struct qed_eth_cb_ops qede_ll_ops = {
  195. {
  196. #ifdef CONFIG_RFS_ACCEL
  197. .arfs_filter_op = qede_arfs_filter_op,
  198. #endif
  199. .link_update = qede_link_update,
  200. },
  201. .force_mac = qede_force_mac,
  202. };
  203. static int qede_netdev_event(struct notifier_block *this, unsigned long event,
  204. void *ptr)
  205. {
  206. struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
  207. struct ethtool_drvinfo drvinfo;
  208. struct qede_dev *edev;
  209. if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
  210. goto done;
  211. /* Check whether this is a qede device */
  212. if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
  213. goto done;
  214. memset(&drvinfo, 0, sizeof(drvinfo));
  215. ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
  216. if (strcmp(drvinfo.driver, "qede"))
  217. goto done;
  218. edev = netdev_priv(ndev);
  219. switch (event) {
  220. case NETDEV_CHANGENAME:
  221. /* Notify qed of the name change */
  222. if (!edev->ops || !edev->ops->common)
  223. goto done;
  224. edev->ops->common->set_id(edev->cdev, edev->ndev->name, "qede");
  225. break;
  226. case NETDEV_CHANGEADDR:
  227. edev = netdev_priv(ndev);
  228. qede_roce_event_changeaddr(edev);
  229. break;
  230. }
  231. done:
  232. return NOTIFY_DONE;
  233. }
  234. static struct notifier_block qede_netdev_notifier = {
  235. .notifier_call = qede_netdev_event,
  236. };
  237. static
  238. int __init qede_init(void)
  239. {
  240. int ret;
  241. pr_info("qede_init: %s\n", version);
  242. qed_ops = qed_get_eth_ops();
  243. if (!qed_ops) {
  244. pr_notice("Failed to get qed ethtool operations\n");
  245. return -EINVAL;
  246. }
  247. /* Must register notifier before pci ops, since we might miss
  248. * interface rename after pci probe and netdev registeration.
  249. */
  250. ret = register_netdevice_notifier(&qede_netdev_notifier);
  251. if (ret) {
  252. pr_notice("Failed to register netdevice_notifier\n");
  253. qed_put_eth_ops();
  254. return -EINVAL;
  255. }
  256. ret = pci_register_driver(&qede_pci_driver);
  257. if (ret) {
  258. pr_notice("Failed to register driver\n");
  259. unregister_netdevice_notifier(&qede_netdev_notifier);
  260. qed_put_eth_ops();
  261. return -EINVAL;
  262. }
  263. return 0;
  264. }
  265. static void __exit qede_cleanup(void)
  266. {
  267. if (debug & QED_LOG_INFO_MASK)
  268. pr_info("qede_cleanup called\n");
  269. unregister_netdevice_notifier(&qede_netdev_notifier);
  270. pci_unregister_driver(&qede_pci_driver);
  271. qed_put_eth_ops();
  272. }
  273. module_init(qede_init);
  274. module_exit(qede_cleanup);
  275. static int qede_open(struct net_device *ndev);
  276. static int qede_close(struct net_device *ndev);
  277. void qede_fill_by_demand_stats(struct qede_dev *edev)
  278. {
  279. struct qede_stats_common *p_common = &edev->stats.common;
  280. struct qed_eth_stats stats;
  281. edev->ops->get_vport_stats(edev->cdev, &stats);
  282. p_common->no_buff_discards = stats.common.no_buff_discards;
  283. p_common->packet_too_big_discard = stats.common.packet_too_big_discard;
  284. p_common->ttl0_discard = stats.common.ttl0_discard;
  285. p_common->rx_ucast_bytes = stats.common.rx_ucast_bytes;
  286. p_common->rx_mcast_bytes = stats.common.rx_mcast_bytes;
  287. p_common->rx_bcast_bytes = stats.common.rx_bcast_bytes;
  288. p_common->rx_ucast_pkts = stats.common.rx_ucast_pkts;
  289. p_common->rx_mcast_pkts = stats.common.rx_mcast_pkts;
  290. p_common->rx_bcast_pkts = stats.common.rx_bcast_pkts;
  291. p_common->mftag_filter_discards = stats.common.mftag_filter_discards;
  292. p_common->mac_filter_discards = stats.common.mac_filter_discards;
  293. p_common->tx_ucast_bytes = stats.common.tx_ucast_bytes;
  294. p_common->tx_mcast_bytes = stats.common.tx_mcast_bytes;
  295. p_common->tx_bcast_bytes = stats.common.tx_bcast_bytes;
  296. p_common->tx_ucast_pkts = stats.common.tx_ucast_pkts;
  297. p_common->tx_mcast_pkts = stats.common.tx_mcast_pkts;
  298. p_common->tx_bcast_pkts = stats.common.tx_bcast_pkts;
  299. p_common->tx_err_drop_pkts = stats.common.tx_err_drop_pkts;
  300. p_common->coalesced_pkts = stats.common.tpa_coalesced_pkts;
  301. p_common->coalesced_events = stats.common.tpa_coalesced_events;
  302. p_common->coalesced_aborts_num = stats.common.tpa_aborts_num;
  303. p_common->non_coalesced_pkts = stats.common.tpa_not_coalesced_pkts;
  304. p_common->coalesced_bytes = stats.common.tpa_coalesced_bytes;
  305. p_common->rx_64_byte_packets = stats.common.rx_64_byte_packets;
  306. p_common->rx_65_to_127_byte_packets =
  307. stats.common.rx_65_to_127_byte_packets;
  308. p_common->rx_128_to_255_byte_packets =
  309. stats.common.rx_128_to_255_byte_packets;
  310. p_common->rx_256_to_511_byte_packets =
  311. stats.common.rx_256_to_511_byte_packets;
  312. p_common->rx_512_to_1023_byte_packets =
  313. stats.common.rx_512_to_1023_byte_packets;
  314. p_common->rx_1024_to_1518_byte_packets =
  315. stats.common.rx_1024_to_1518_byte_packets;
  316. p_common->rx_crc_errors = stats.common.rx_crc_errors;
  317. p_common->rx_mac_crtl_frames = stats.common.rx_mac_crtl_frames;
  318. p_common->rx_pause_frames = stats.common.rx_pause_frames;
  319. p_common->rx_pfc_frames = stats.common.rx_pfc_frames;
  320. p_common->rx_align_errors = stats.common.rx_align_errors;
  321. p_common->rx_carrier_errors = stats.common.rx_carrier_errors;
  322. p_common->rx_oversize_packets = stats.common.rx_oversize_packets;
  323. p_common->rx_jabbers = stats.common.rx_jabbers;
  324. p_common->rx_undersize_packets = stats.common.rx_undersize_packets;
  325. p_common->rx_fragments = stats.common.rx_fragments;
  326. p_common->tx_64_byte_packets = stats.common.tx_64_byte_packets;
  327. p_common->tx_65_to_127_byte_packets =
  328. stats.common.tx_65_to_127_byte_packets;
  329. p_common->tx_128_to_255_byte_packets =
  330. stats.common.tx_128_to_255_byte_packets;
  331. p_common->tx_256_to_511_byte_packets =
  332. stats.common.tx_256_to_511_byte_packets;
  333. p_common->tx_512_to_1023_byte_packets =
  334. stats.common.tx_512_to_1023_byte_packets;
  335. p_common->tx_1024_to_1518_byte_packets =
  336. stats.common.tx_1024_to_1518_byte_packets;
  337. p_common->tx_pause_frames = stats.common.tx_pause_frames;
  338. p_common->tx_pfc_frames = stats.common.tx_pfc_frames;
  339. p_common->brb_truncates = stats.common.brb_truncates;
  340. p_common->brb_discards = stats.common.brb_discards;
  341. p_common->tx_mac_ctrl_frames = stats.common.tx_mac_ctrl_frames;
  342. if (QEDE_IS_BB(edev)) {
  343. struct qede_stats_bb *p_bb = &edev->stats.bb;
  344. p_bb->rx_1519_to_1522_byte_packets =
  345. stats.bb.rx_1519_to_1522_byte_packets;
  346. p_bb->rx_1519_to_2047_byte_packets =
  347. stats.bb.rx_1519_to_2047_byte_packets;
  348. p_bb->rx_2048_to_4095_byte_packets =
  349. stats.bb.rx_2048_to_4095_byte_packets;
  350. p_bb->rx_4096_to_9216_byte_packets =
  351. stats.bb.rx_4096_to_9216_byte_packets;
  352. p_bb->rx_9217_to_16383_byte_packets =
  353. stats.bb.rx_9217_to_16383_byte_packets;
  354. p_bb->tx_1519_to_2047_byte_packets =
  355. stats.bb.tx_1519_to_2047_byte_packets;
  356. p_bb->tx_2048_to_4095_byte_packets =
  357. stats.bb.tx_2048_to_4095_byte_packets;
  358. p_bb->tx_4096_to_9216_byte_packets =
  359. stats.bb.tx_4096_to_9216_byte_packets;
  360. p_bb->tx_9217_to_16383_byte_packets =
  361. stats.bb.tx_9217_to_16383_byte_packets;
  362. p_bb->tx_lpi_entry_count = stats.bb.tx_lpi_entry_count;
  363. p_bb->tx_total_collisions = stats.bb.tx_total_collisions;
  364. } else {
  365. struct qede_stats_ah *p_ah = &edev->stats.ah;
  366. p_ah->rx_1519_to_max_byte_packets =
  367. stats.ah.rx_1519_to_max_byte_packets;
  368. p_ah->tx_1519_to_max_byte_packets =
  369. stats.ah.tx_1519_to_max_byte_packets;
  370. }
  371. }
  372. static void qede_get_stats64(struct net_device *dev,
  373. struct rtnl_link_stats64 *stats)
  374. {
  375. struct qede_dev *edev = netdev_priv(dev);
  376. struct qede_stats_common *p_common;
  377. qede_fill_by_demand_stats(edev);
  378. p_common = &edev->stats.common;
  379. stats->rx_packets = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
  380. p_common->rx_bcast_pkts;
  381. stats->tx_packets = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
  382. p_common->tx_bcast_pkts;
  383. stats->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
  384. p_common->rx_bcast_bytes;
  385. stats->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
  386. p_common->tx_bcast_bytes;
  387. stats->tx_errors = p_common->tx_err_drop_pkts;
  388. stats->multicast = p_common->rx_mcast_pkts + p_common->rx_bcast_pkts;
  389. stats->rx_fifo_errors = p_common->no_buff_discards;
  390. if (QEDE_IS_BB(edev))
  391. stats->collisions = edev->stats.bb.tx_total_collisions;
  392. stats->rx_crc_errors = p_common->rx_crc_errors;
  393. stats->rx_frame_errors = p_common->rx_align_errors;
  394. }
  395. #ifdef CONFIG_QED_SRIOV
  396. static int qede_get_vf_config(struct net_device *dev, int vfidx,
  397. struct ifla_vf_info *ivi)
  398. {
  399. struct qede_dev *edev = netdev_priv(dev);
  400. if (!edev->ops)
  401. return -EINVAL;
  402. return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
  403. }
  404. static int qede_set_vf_rate(struct net_device *dev, int vfidx,
  405. int min_tx_rate, int max_tx_rate)
  406. {
  407. struct qede_dev *edev = netdev_priv(dev);
  408. return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
  409. max_tx_rate);
  410. }
  411. static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
  412. {
  413. struct qede_dev *edev = netdev_priv(dev);
  414. if (!edev->ops)
  415. return -EINVAL;
  416. return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
  417. }
  418. static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
  419. int link_state)
  420. {
  421. struct qede_dev *edev = netdev_priv(dev);
  422. if (!edev->ops)
  423. return -EINVAL;
  424. return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
  425. }
  426. static int qede_set_vf_trust(struct net_device *dev, int vfidx, bool setting)
  427. {
  428. struct qede_dev *edev = netdev_priv(dev);
  429. if (!edev->ops)
  430. return -EINVAL;
  431. return edev->ops->iov->set_trust(edev->cdev, vfidx, setting);
  432. }
  433. #endif
  434. static int qede_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  435. {
  436. struct qede_dev *edev = netdev_priv(dev);
  437. if (!netif_running(dev))
  438. return -EAGAIN;
  439. switch (cmd) {
  440. case SIOCSHWTSTAMP:
  441. return qede_ptp_hw_ts(edev, ifr);
  442. default:
  443. DP_VERBOSE(edev, QED_MSG_DEBUG,
  444. "default IOCTL cmd 0x%x\n", cmd);
  445. return -EOPNOTSUPP;
  446. }
  447. return 0;
  448. }
  449. static const struct net_device_ops qede_netdev_ops = {
  450. .ndo_open = qede_open,
  451. .ndo_stop = qede_close,
  452. .ndo_start_xmit = qede_start_xmit,
  453. .ndo_set_rx_mode = qede_set_rx_mode,
  454. .ndo_set_mac_address = qede_set_mac_addr,
  455. .ndo_validate_addr = eth_validate_addr,
  456. .ndo_change_mtu = qede_change_mtu,
  457. .ndo_do_ioctl = qede_ioctl,
  458. #ifdef CONFIG_QED_SRIOV
  459. .ndo_set_vf_mac = qede_set_vf_mac,
  460. .ndo_set_vf_vlan = qede_set_vf_vlan,
  461. .ndo_set_vf_trust = qede_set_vf_trust,
  462. #endif
  463. .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
  464. .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
  465. .ndo_set_features = qede_set_features,
  466. .ndo_get_stats64 = qede_get_stats64,
  467. #ifdef CONFIG_QED_SRIOV
  468. .ndo_set_vf_link_state = qede_set_vf_link_state,
  469. .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
  470. .ndo_get_vf_config = qede_get_vf_config,
  471. .ndo_set_vf_rate = qede_set_vf_rate,
  472. #endif
  473. .ndo_udp_tunnel_add = qede_udp_tunnel_add,
  474. .ndo_udp_tunnel_del = qede_udp_tunnel_del,
  475. .ndo_features_check = qede_features_check,
  476. .ndo_xdp = qede_xdp,
  477. #ifdef CONFIG_RFS_ACCEL
  478. .ndo_rx_flow_steer = qede_rx_flow_steer,
  479. #endif
  480. };
  481. /* -------------------------------------------------------------------------
  482. * START OF PROBE / REMOVE
  483. * -------------------------------------------------------------------------
  484. */
  485. static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
  486. struct pci_dev *pdev,
  487. struct qed_dev_eth_info *info,
  488. u32 dp_module, u8 dp_level)
  489. {
  490. struct net_device *ndev;
  491. struct qede_dev *edev;
  492. ndev = alloc_etherdev_mqs(sizeof(*edev),
  493. info->num_queues, info->num_queues);
  494. if (!ndev) {
  495. pr_err("etherdev allocation failed\n");
  496. return NULL;
  497. }
  498. edev = netdev_priv(ndev);
  499. edev->ndev = ndev;
  500. edev->cdev = cdev;
  501. edev->pdev = pdev;
  502. edev->dp_module = dp_module;
  503. edev->dp_level = dp_level;
  504. edev->ops = qed_ops;
  505. edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
  506. edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
  507. DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
  508. info->num_queues, info->num_queues);
  509. SET_NETDEV_DEV(ndev, &pdev->dev);
  510. memset(&edev->stats, 0, sizeof(edev->stats));
  511. memcpy(&edev->dev_info, info, sizeof(*info));
  512. INIT_LIST_HEAD(&edev->vlan_list);
  513. return edev;
  514. }
  515. static void qede_init_ndev(struct qede_dev *edev)
  516. {
  517. struct net_device *ndev = edev->ndev;
  518. struct pci_dev *pdev = edev->pdev;
  519. netdev_features_t hw_features;
  520. pci_set_drvdata(pdev, ndev);
  521. ndev->mem_start = edev->dev_info.common.pci_mem_start;
  522. ndev->base_addr = ndev->mem_start;
  523. ndev->mem_end = edev->dev_info.common.pci_mem_end;
  524. ndev->irq = edev->dev_info.common.pci_irq;
  525. ndev->watchdog_timeo = TX_TIMEOUT;
  526. ndev->netdev_ops = &qede_netdev_ops;
  527. qede_set_ethtool_ops(ndev);
  528. ndev->priv_flags |= IFF_UNICAST_FLT;
  529. /* user-changeble features */
  530. hw_features = NETIF_F_GRO | NETIF_F_SG |
  531. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  532. NETIF_F_TSO | NETIF_F_TSO6;
  533. /* Encap features*/
  534. hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
  535. NETIF_F_TSO_ECN | NETIF_F_GSO_UDP_TUNNEL_CSUM |
  536. NETIF_F_GSO_GRE_CSUM;
  537. if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1)
  538. hw_features |= NETIF_F_NTUPLE;
  539. ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  540. NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
  541. NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  542. NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM |
  543. NETIF_F_GSO_UDP_TUNNEL_CSUM |
  544. NETIF_F_GSO_GRE_CSUM;
  545. ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
  546. NETIF_F_HIGHDMA;
  547. ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
  548. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
  549. NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
  550. ndev->hw_features = hw_features;
  551. /* MTU range: 46 - 9600 */
  552. ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
  553. ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
  554. /* Set network device HW mac */
  555. ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
  556. ndev->mtu = edev->dev_info.common.mtu;
  557. }
  558. /* This function converts from 32b param to two params of level and module
  559. * Input 32b decoding:
  560. * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
  561. * 'happy' flow, e.g. memory allocation failed.
  562. * b30 - enable all INFO prints. INFO prints are for major steps in the flow
  563. * and provide important parameters.
  564. * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
  565. * module. VERBOSE prints are for tracking the specific flow in low level.
  566. *
  567. * Notice that the level should be that of the lowest required logs.
  568. */
  569. void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
  570. {
  571. *p_dp_level = QED_LEVEL_NOTICE;
  572. *p_dp_module = 0;
  573. if (debug & QED_LOG_VERBOSE_MASK) {
  574. *p_dp_level = QED_LEVEL_VERBOSE;
  575. *p_dp_module = (debug & 0x3FFFFFFF);
  576. } else if (debug & QED_LOG_INFO_MASK) {
  577. *p_dp_level = QED_LEVEL_INFO;
  578. } else if (debug & QED_LOG_NOTICE_MASK) {
  579. *p_dp_level = QED_LEVEL_NOTICE;
  580. }
  581. }
  582. static void qede_free_fp_array(struct qede_dev *edev)
  583. {
  584. if (edev->fp_array) {
  585. struct qede_fastpath *fp;
  586. int i;
  587. for_each_queue(i) {
  588. fp = &edev->fp_array[i];
  589. kfree(fp->sb_info);
  590. kfree(fp->rxq);
  591. kfree(fp->xdp_tx);
  592. kfree(fp->txq);
  593. }
  594. kfree(edev->fp_array);
  595. }
  596. edev->num_queues = 0;
  597. edev->fp_num_tx = 0;
  598. edev->fp_num_rx = 0;
  599. }
  600. static int qede_alloc_fp_array(struct qede_dev *edev)
  601. {
  602. u8 fp_combined, fp_rx = edev->fp_num_rx;
  603. struct qede_fastpath *fp;
  604. int i;
  605. edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
  606. sizeof(*edev->fp_array), GFP_KERNEL);
  607. if (!edev->fp_array) {
  608. DP_NOTICE(edev, "fp array allocation failed\n");
  609. goto err;
  610. }
  611. fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
  612. /* Allocate the FP elements for Rx queues followed by combined and then
  613. * the Tx. This ordering should be maintained so that the respective
  614. * queues (Rx or Tx) will be together in the fastpath array and the
  615. * associated ids will be sequential.
  616. */
  617. for_each_queue(i) {
  618. fp = &edev->fp_array[i];
  619. fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
  620. if (!fp->sb_info) {
  621. DP_NOTICE(edev, "sb info struct allocation failed\n");
  622. goto err;
  623. }
  624. if (fp_rx) {
  625. fp->type = QEDE_FASTPATH_RX;
  626. fp_rx--;
  627. } else if (fp_combined) {
  628. fp->type = QEDE_FASTPATH_COMBINED;
  629. fp_combined--;
  630. } else {
  631. fp->type = QEDE_FASTPATH_TX;
  632. }
  633. if (fp->type & QEDE_FASTPATH_TX) {
  634. fp->txq = kzalloc(sizeof(*fp->txq), GFP_KERNEL);
  635. if (!fp->txq)
  636. goto err;
  637. }
  638. if (fp->type & QEDE_FASTPATH_RX) {
  639. fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
  640. if (!fp->rxq)
  641. goto err;
  642. if (edev->xdp_prog) {
  643. fp->xdp_tx = kzalloc(sizeof(*fp->xdp_tx),
  644. GFP_KERNEL);
  645. if (!fp->xdp_tx)
  646. goto err;
  647. fp->type |= QEDE_FASTPATH_XDP;
  648. }
  649. }
  650. }
  651. return 0;
  652. err:
  653. qede_free_fp_array(edev);
  654. return -ENOMEM;
  655. }
  656. static void qede_sp_task(struct work_struct *work)
  657. {
  658. struct qede_dev *edev = container_of(work, struct qede_dev,
  659. sp_task.work);
  660. struct qed_dev *cdev = edev->cdev;
  661. __qede_lock(edev);
  662. if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
  663. if (edev->state == QEDE_STATE_OPEN)
  664. qede_config_rx_mode(edev->ndev);
  665. if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
  666. struct qed_tunn_params tunn_params;
  667. memset(&tunn_params, 0, sizeof(tunn_params));
  668. tunn_params.update_vxlan_port = 1;
  669. tunn_params.vxlan_port = edev->vxlan_dst_port;
  670. qed_ops->tunn_config(cdev, &tunn_params);
  671. }
  672. if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
  673. struct qed_tunn_params tunn_params;
  674. memset(&tunn_params, 0, sizeof(tunn_params));
  675. tunn_params.update_geneve_port = 1;
  676. tunn_params.geneve_port = edev->geneve_dst_port;
  677. qed_ops->tunn_config(cdev, &tunn_params);
  678. }
  679. #ifdef CONFIG_RFS_ACCEL
  680. if (test_and_clear_bit(QEDE_SP_ARFS_CONFIG, &edev->sp_flags)) {
  681. if (edev->state == QEDE_STATE_OPEN)
  682. qede_process_arfs_filters(edev, false);
  683. }
  684. #endif
  685. __qede_unlock(edev);
  686. }
  687. static void qede_update_pf_params(struct qed_dev *cdev)
  688. {
  689. struct qed_pf_params pf_params;
  690. /* 64 rx + 64 tx + 64 XDP */
  691. memset(&pf_params, 0, sizeof(struct qed_pf_params));
  692. pf_params.eth_pf_params.num_cons = (MAX_SB_PER_PF_MIMD - 1) * 3;
  693. #ifdef CONFIG_RFS_ACCEL
  694. pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
  695. #endif
  696. qed_ops->common->update_pf_params(cdev, &pf_params);
  697. }
  698. enum qede_probe_mode {
  699. QEDE_PROBE_NORMAL,
  700. };
  701. static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
  702. bool is_vf, enum qede_probe_mode mode)
  703. {
  704. struct qed_probe_params probe_params;
  705. struct qed_slowpath_params sp_params;
  706. struct qed_dev_eth_info dev_info;
  707. struct qede_dev *edev;
  708. struct qed_dev *cdev;
  709. int rc;
  710. if (unlikely(dp_level & QED_LEVEL_INFO))
  711. pr_notice("Starting qede probe\n");
  712. memset(&probe_params, 0, sizeof(probe_params));
  713. probe_params.protocol = QED_PROTOCOL_ETH;
  714. probe_params.dp_module = dp_module;
  715. probe_params.dp_level = dp_level;
  716. probe_params.is_vf = is_vf;
  717. cdev = qed_ops->common->probe(pdev, &probe_params);
  718. if (!cdev) {
  719. rc = -ENODEV;
  720. goto err0;
  721. }
  722. qede_update_pf_params(cdev);
  723. /* Start the Slowpath-process */
  724. memset(&sp_params, 0, sizeof(sp_params));
  725. sp_params.int_mode = QED_INT_MODE_MSIX;
  726. sp_params.drv_major = QEDE_MAJOR_VERSION;
  727. sp_params.drv_minor = QEDE_MINOR_VERSION;
  728. sp_params.drv_rev = QEDE_REVISION_VERSION;
  729. sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
  730. strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
  731. rc = qed_ops->common->slowpath_start(cdev, &sp_params);
  732. if (rc) {
  733. pr_notice("Cannot start slowpath\n");
  734. goto err1;
  735. }
  736. /* Learn information crucial for qede to progress */
  737. rc = qed_ops->fill_dev_info(cdev, &dev_info);
  738. if (rc)
  739. goto err2;
  740. edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
  741. dp_level);
  742. if (!edev) {
  743. rc = -ENOMEM;
  744. goto err2;
  745. }
  746. if (is_vf)
  747. edev->flags |= QEDE_FLAG_IS_VF;
  748. qede_init_ndev(edev);
  749. rc = qede_roce_dev_add(edev);
  750. if (rc)
  751. goto err3;
  752. /* Prepare the lock prior to the registeration of the netdev,
  753. * as once it's registered we might reach flows requiring it
  754. * [it's even possible to reach a flow needing it directly
  755. * from there, although it's unlikely].
  756. */
  757. INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
  758. mutex_init(&edev->qede_lock);
  759. rc = register_netdev(edev->ndev);
  760. if (rc) {
  761. DP_NOTICE(edev, "Cannot register net-device\n");
  762. goto err4;
  763. }
  764. edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
  765. /* PTP not supported on VFs */
  766. if (!is_vf) {
  767. rc = qede_ptp_register_phc(edev);
  768. if (rc) {
  769. DP_NOTICE(edev, "Cannot register PHC\n");
  770. goto err5;
  771. }
  772. }
  773. edev->ops->register_ops(cdev, &qede_ll_ops, edev);
  774. #ifdef CONFIG_DCB
  775. if (!IS_VF(edev))
  776. qede_set_dcbnl_ops(edev->ndev);
  777. #endif
  778. edev->rx_copybreak = QEDE_RX_HDR_SIZE;
  779. DP_INFO(edev, "Ending successfully qede probe\n");
  780. return 0;
  781. err5:
  782. unregister_netdev(edev->ndev);
  783. err4:
  784. qede_roce_dev_remove(edev);
  785. err3:
  786. free_netdev(edev->ndev);
  787. err2:
  788. qed_ops->common->slowpath_stop(cdev);
  789. err1:
  790. qed_ops->common->remove(cdev);
  791. err0:
  792. return rc;
  793. }
  794. static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  795. {
  796. bool is_vf = false;
  797. u32 dp_module = 0;
  798. u8 dp_level = 0;
  799. switch ((enum qede_pci_private)id->driver_data) {
  800. case QEDE_PRIVATE_VF:
  801. if (debug & QED_LOG_VERBOSE_MASK)
  802. dev_err(&pdev->dev, "Probing a VF\n");
  803. is_vf = true;
  804. break;
  805. default:
  806. if (debug & QED_LOG_VERBOSE_MASK)
  807. dev_err(&pdev->dev, "Probing a PF\n");
  808. }
  809. qede_config_debug(debug, &dp_module, &dp_level);
  810. return __qede_probe(pdev, dp_module, dp_level, is_vf,
  811. QEDE_PROBE_NORMAL);
  812. }
  813. enum qede_remove_mode {
  814. QEDE_REMOVE_NORMAL,
  815. };
  816. static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
  817. {
  818. struct net_device *ndev = pci_get_drvdata(pdev);
  819. struct qede_dev *edev = netdev_priv(ndev);
  820. struct qed_dev *cdev = edev->cdev;
  821. DP_INFO(edev, "Starting qede_remove\n");
  822. unregister_netdev(ndev);
  823. cancel_delayed_work_sync(&edev->sp_task);
  824. qede_ptp_remove(edev);
  825. qede_roce_dev_remove(edev);
  826. edev->ops->common->set_power_state(cdev, PCI_D0);
  827. pci_set_drvdata(pdev, NULL);
  828. /* Release edev's reference to XDP's bpf if such exist */
  829. if (edev->xdp_prog)
  830. bpf_prog_put(edev->xdp_prog);
  831. /* Use global ops since we've freed edev */
  832. qed_ops->common->slowpath_stop(cdev);
  833. if (system_state == SYSTEM_POWER_OFF)
  834. return;
  835. qed_ops->common->remove(cdev);
  836. /* Since this can happen out-of-sync with other flows,
  837. * don't release the netdevice until after slowpath stop
  838. * has been called to guarantee various other contexts
  839. * [e.g., QED register callbacks] won't break anything when
  840. * accessing the netdevice.
  841. */
  842. free_netdev(ndev);
  843. dev_info(&pdev->dev, "Ending qede_remove successfully\n");
  844. }
  845. static void qede_remove(struct pci_dev *pdev)
  846. {
  847. __qede_remove(pdev, QEDE_REMOVE_NORMAL);
  848. }
  849. static void qede_shutdown(struct pci_dev *pdev)
  850. {
  851. __qede_remove(pdev, QEDE_REMOVE_NORMAL);
  852. }
  853. /* -------------------------------------------------------------------------
  854. * START OF LOAD / UNLOAD
  855. * -------------------------------------------------------------------------
  856. */
  857. static int qede_set_num_queues(struct qede_dev *edev)
  858. {
  859. int rc;
  860. u16 rss_num;
  861. /* Setup queues according to possible resources*/
  862. if (edev->req_queues)
  863. rss_num = edev->req_queues;
  864. else
  865. rss_num = netif_get_num_default_rss_queues() *
  866. edev->dev_info.common.num_hwfns;
  867. rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
  868. rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
  869. if (rc > 0) {
  870. /* Managed to request interrupts for our queues */
  871. edev->num_queues = rc;
  872. DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
  873. QEDE_QUEUE_CNT(edev), rss_num);
  874. rc = 0;
  875. }
  876. edev->fp_num_tx = edev->req_num_tx;
  877. edev->fp_num_rx = edev->req_num_rx;
  878. return rc;
  879. }
  880. static void qede_free_mem_sb(struct qede_dev *edev,
  881. struct qed_sb_info *sb_info)
  882. {
  883. if (sb_info->sb_virt)
  884. dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
  885. (void *)sb_info->sb_virt, sb_info->sb_phys);
  886. }
  887. /* This function allocates fast-path status block memory */
  888. static int qede_alloc_mem_sb(struct qede_dev *edev,
  889. struct qed_sb_info *sb_info, u16 sb_id)
  890. {
  891. struct status_block *sb_virt;
  892. dma_addr_t sb_phys;
  893. int rc;
  894. sb_virt = dma_alloc_coherent(&edev->pdev->dev,
  895. sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
  896. if (!sb_virt) {
  897. DP_ERR(edev, "Status block allocation failed\n");
  898. return -ENOMEM;
  899. }
  900. rc = edev->ops->common->sb_init(edev->cdev, sb_info,
  901. sb_virt, sb_phys, sb_id,
  902. QED_SB_TYPE_L2_QUEUE);
  903. if (rc) {
  904. DP_ERR(edev, "Status block initialization failed\n");
  905. dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
  906. sb_virt, sb_phys);
  907. return rc;
  908. }
  909. return 0;
  910. }
  911. static void qede_free_rx_buffers(struct qede_dev *edev,
  912. struct qede_rx_queue *rxq)
  913. {
  914. u16 i;
  915. for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
  916. struct sw_rx_data *rx_buf;
  917. struct page *data;
  918. rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
  919. data = rx_buf->data;
  920. dma_unmap_page(&edev->pdev->dev,
  921. rx_buf->mapping, PAGE_SIZE, rxq->data_direction);
  922. rx_buf->data = NULL;
  923. __free_page(data);
  924. }
  925. }
  926. static void qede_free_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
  927. {
  928. int i;
  929. if (edev->gro_disable)
  930. return;
  931. for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
  932. struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
  933. struct sw_rx_data *replace_buf = &tpa_info->buffer;
  934. if (replace_buf->data) {
  935. dma_unmap_page(&edev->pdev->dev,
  936. replace_buf->mapping,
  937. PAGE_SIZE, DMA_FROM_DEVICE);
  938. __free_page(replace_buf->data);
  939. }
  940. }
  941. }
  942. static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
  943. {
  944. qede_free_sge_mem(edev, rxq);
  945. /* Free rx buffers */
  946. qede_free_rx_buffers(edev, rxq);
  947. /* Free the parallel SW ring */
  948. kfree(rxq->sw_rx_ring);
  949. /* Free the real RQ ring used by FW */
  950. edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
  951. edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
  952. }
  953. static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
  954. {
  955. dma_addr_t mapping;
  956. int i;
  957. /* Don't perform FW aggregations in case of XDP */
  958. if (edev->xdp_prog)
  959. edev->gro_disable = 1;
  960. if (edev->gro_disable)
  961. return 0;
  962. if (edev->ndev->mtu > PAGE_SIZE) {
  963. edev->gro_disable = 1;
  964. return 0;
  965. }
  966. for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
  967. struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
  968. struct sw_rx_data *replace_buf = &tpa_info->buffer;
  969. replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
  970. if (unlikely(!replace_buf->data)) {
  971. DP_NOTICE(edev,
  972. "Failed to allocate TPA skb pool [replacement buffer]\n");
  973. goto err;
  974. }
  975. mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
  976. PAGE_SIZE, DMA_FROM_DEVICE);
  977. if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
  978. DP_NOTICE(edev,
  979. "Failed to map TPA replacement buffer\n");
  980. goto err;
  981. }
  982. replace_buf->mapping = mapping;
  983. tpa_info->buffer.page_offset = 0;
  984. tpa_info->buffer_mapping = mapping;
  985. tpa_info->state = QEDE_AGG_STATE_NONE;
  986. }
  987. return 0;
  988. err:
  989. qede_free_sge_mem(edev, rxq);
  990. edev->gro_disable = 1;
  991. return -ENOMEM;
  992. }
  993. /* This function allocates all memory needed per Rx queue */
  994. static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
  995. {
  996. int i, rc, size;
  997. rxq->num_rx_buffers = edev->q_num_rx_buffers;
  998. rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
  999. rxq->rx_headroom = edev->xdp_prog ? XDP_PACKET_HEADROOM : 0;
  1000. /* Make sure that the headroom and payload fit in a single page */
  1001. if (rxq->rx_buf_size + rxq->rx_headroom > PAGE_SIZE)
  1002. rxq->rx_buf_size = PAGE_SIZE - rxq->rx_headroom;
  1003. /* Segment size to spilt a page in multiple equal parts,
  1004. * unless XDP is used in which case we'd use the entire page.
  1005. */
  1006. if (!edev->xdp_prog)
  1007. rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
  1008. else
  1009. rxq->rx_buf_seg_size = PAGE_SIZE;
  1010. /* Allocate the parallel driver ring for Rx buffers */
  1011. size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
  1012. rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
  1013. if (!rxq->sw_rx_ring) {
  1014. DP_ERR(edev, "Rx buffers ring allocation failed\n");
  1015. rc = -ENOMEM;
  1016. goto err;
  1017. }
  1018. /* Allocate FW Rx ring */
  1019. rc = edev->ops->common->chain_alloc(edev->cdev,
  1020. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1021. QED_CHAIN_MODE_NEXT_PTR,
  1022. QED_CHAIN_CNT_TYPE_U16,
  1023. RX_RING_SIZE,
  1024. sizeof(struct eth_rx_bd),
  1025. &rxq->rx_bd_ring);
  1026. if (rc)
  1027. goto err;
  1028. /* Allocate FW completion ring */
  1029. rc = edev->ops->common->chain_alloc(edev->cdev,
  1030. QED_CHAIN_USE_TO_CONSUME,
  1031. QED_CHAIN_MODE_PBL,
  1032. QED_CHAIN_CNT_TYPE_U16,
  1033. RX_RING_SIZE,
  1034. sizeof(union eth_rx_cqe),
  1035. &rxq->rx_comp_ring);
  1036. if (rc)
  1037. goto err;
  1038. /* Allocate buffers for the Rx ring */
  1039. rxq->filled_buffers = 0;
  1040. for (i = 0; i < rxq->num_rx_buffers; i++) {
  1041. rc = qede_alloc_rx_buffer(rxq, false);
  1042. if (rc) {
  1043. DP_ERR(edev,
  1044. "Rx buffers allocation failed at index %d\n", i);
  1045. goto err;
  1046. }
  1047. }
  1048. rc = qede_alloc_sge_mem(edev, rxq);
  1049. err:
  1050. return rc;
  1051. }
  1052. static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
  1053. {
  1054. /* Free the parallel SW ring */
  1055. if (txq->is_xdp)
  1056. kfree(txq->sw_tx_ring.xdp);
  1057. else
  1058. kfree(txq->sw_tx_ring.skbs);
  1059. /* Free the real RQ ring used by FW */
  1060. edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
  1061. }
  1062. /* This function allocates all memory needed per Tx queue */
  1063. static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
  1064. {
  1065. union eth_tx_bd_types *p_virt;
  1066. int size, rc;
  1067. txq->num_tx_buffers = edev->q_num_tx_buffers;
  1068. /* Allocate the parallel driver ring for Tx buffers */
  1069. if (txq->is_xdp) {
  1070. size = sizeof(*txq->sw_tx_ring.xdp) * TX_RING_SIZE;
  1071. txq->sw_tx_ring.xdp = kzalloc(size, GFP_KERNEL);
  1072. if (!txq->sw_tx_ring.xdp)
  1073. goto err;
  1074. } else {
  1075. size = sizeof(*txq->sw_tx_ring.skbs) * TX_RING_SIZE;
  1076. txq->sw_tx_ring.skbs = kzalloc(size, GFP_KERNEL);
  1077. if (!txq->sw_tx_ring.skbs)
  1078. goto err;
  1079. }
  1080. rc = edev->ops->common->chain_alloc(edev->cdev,
  1081. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  1082. QED_CHAIN_MODE_PBL,
  1083. QED_CHAIN_CNT_TYPE_U16,
  1084. TX_RING_SIZE,
  1085. sizeof(*p_virt), &txq->tx_pbl);
  1086. if (rc)
  1087. goto err;
  1088. return 0;
  1089. err:
  1090. qede_free_mem_txq(edev, txq);
  1091. return -ENOMEM;
  1092. }
  1093. /* This function frees all memory of a single fp */
  1094. static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
  1095. {
  1096. qede_free_mem_sb(edev, fp->sb_info);
  1097. if (fp->type & QEDE_FASTPATH_RX)
  1098. qede_free_mem_rxq(edev, fp->rxq);
  1099. if (fp->type & QEDE_FASTPATH_TX)
  1100. qede_free_mem_txq(edev, fp->txq);
  1101. }
  1102. /* This function allocates all memory needed for a single fp (i.e. an entity
  1103. * which contains status block, one rx queue and/or multiple per-TC tx queues.
  1104. */
  1105. static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
  1106. {
  1107. int rc = 0;
  1108. rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
  1109. if (rc)
  1110. goto out;
  1111. if (fp->type & QEDE_FASTPATH_RX) {
  1112. rc = qede_alloc_mem_rxq(edev, fp->rxq);
  1113. if (rc)
  1114. goto out;
  1115. }
  1116. if (fp->type & QEDE_FASTPATH_XDP) {
  1117. rc = qede_alloc_mem_txq(edev, fp->xdp_tx);
  1118. if (rc)
  1119. goto out;
  1120. }
  1121. if (fp->type & QEDE_FASTPATH_TX) {
  1122. rc = qede_alloc_mem_txq(edev, fp->txq);
  1123. if (rc)
  1124. goto out;
  1125. }
  1126. out:
  1127. return rc;
  1128. }
  1129. static void qede_free_mem_load(struct qede_dev *edev)
  1130. {
  1131. int i;
  1132. for_each_queue(i) {
  1133. struct qede_fastpath *fp = &edev->fp_array[i];
  1134. qede_free_mem_fp(edev, fp);
  1135. }
  1136. }
  1137. /* This function allocates all qede memory at NIC load. */
  1138. static int qede_alloc_mem_load(struct qede_dev *edev)
  1139. {
  1140. int rc = 0, queue_id;
  1141. for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
  1142. struct qede_fastpath *fp = &edev->fp_array[queue_id];
  1143. rc = qede_alloc_mem_fp(edev, fp);
  1144. if (rc) {
  1145. DP_ERR(edev,
  1146. "Failed to allocate memory for fastpath - rss id = %d\n",
  1147. queue_id);
  1148. qede_free_mem_load(edev);
  1149. return rc;
  1150. }
  1151. }
  1152. return 0;
  1153. }
  1154. /* This function inits fp content and resets the SB, RXQ and TXQ structures */
  1155. static void qede_init_fp(struct qede_dev *edev)
  1156. {
  1157. int queue_id, rxq_index = 0, txq_index = 0;
  1158. struct qede_fastpath *fp;
  1159. for_each_queue(queue_id) {
  1160. fp = &edev->fp_array[queue_id];
  1161. fp->edev = edev;
  1162. fp->id = queue_id;
  1163. if (fp->type & QEDE_FASTPATH_XDP) {
  1164. fp->xdp_tx->index = QEDE_TXQ_IDX_TO_XDP(edev,
  1165. rxq_index);
  1166. fp->xdp_tx->is_xdp = 1;
  1167. }
  1168. if (fp->type & QEDE_FASTPATH_RX) {
  1169. fp->rxq->rxq_id = rxq_index++;
  1170. /* Determine how to map buffers for this queue */
  1171. if (fp->type & QEDE_FASTPATH_XDP)
  1172. fp->rxq->data_direction = DMA_BIDIRECTIONAL;
  1173. else
  1174. fp->rxq->data_direction = DMA_FROM_DEVICE;
  1175. fp->rxq->dev = &edev->pdev->dev;
  1176. }
  1177. if (fp->type & QEDE_FASTPATH_TX) {
  1178. fp->txq->index = txq_index++;
  1179. if (edev->dev_info.is_legacy)
  1180. fp->txq->is_legacy = 1;
  1181. fp->txq->dev = &edev->pdev->dev;
  1182. }
  1183. snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
  1184. edev->ndev->name, queue_id);
  1185. }
  1186. edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
  1187. }
  1188. static int qede_set_real_num_queues(struct qede_dev *edev)
  1189. {
  1190. int rc = 0;
  1191. rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_COUNT(edev));
  1192. if (rc) {
  1193. DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
  1194. return rc;
  1195. }
  1196. rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
  1197. if (rc) {
  1198. DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
  1199. return rc;
  1200. }
  1201. return 0;
  1202. }
  1203. static void qede_napi_disable_remove(struct qede_dev *edev)
  1204. {
  1205. int i;
  1206. for_each_queue(i) {
  1207. napi_disable(&edev->fp_array[i].napi);
  1208. netif_napi_del(&edev->fp_array[i].napi);
  1209. }
  1210. }
  1211. static void qede_napi_add_enable(struct qede_dev *edev)
  1212. {
  1213. int i;
  1214. /* Add NAPI objects */
  1215. for_each_queue(i) {
  1216. netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
  1217. qede_poll, NAPI_POLL_WEIGHT);
  1218. napi_enable(&edev->fp_array[i].napi);
  1219. }
  1220. }
  1221. static void qede_sync_free_irqs(struct qede_dev *edev)
  1222. {
  1223. int i;
  1224. for (i = 0; i < edev->int_info.used_cnt; i++) {
  1225. if (edev->int_info.msix_cnt) {
  1226. synchronize_irq(edev->int_info.msix[i].vector);
  1227. free_irq(edev->int_info.msix[i].vector,
  1228. &edev->fp_array[i]);
  1229. } else {
  1230. edev->ops->common->simd_handler_clean(edev->cdev, i);
  1231. }
  1232. }
  1233. edev->int_info.used_cnt = 0;
  1234. }
  1235. static int qede_req_msix_irqs(struct qede_dev *edev)
  1236. {
  1237. int i, rc;
  1238. /* Sanitize number of interrupts == number of prepared RSS queues */
  1239. if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
  1240. DP_ERR(edev,
  1241. "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
  1242. QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
  1243. return -EINVAL;
  1244. }
  1245. for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
  1246. #ifdef CONFIG_RFS_ACCEL
  1247. struct qede_fastpath *fp = &edev->fp_array[i];
  1248. if (edev->ndev->rx_cpu_rmap && (fp->type & QEDE_FASTPATH_RX)) {
  1249. rc = irq_cpu_rmap_add(edev->ndev->rx_cpu_rmap,
  1250. edev->int_info.msix[i].vector);
  1251. if (rc) {
  1252. DP_ERR(edev, "Failed to add CPU rmap\n");
  1253. qede_free_arfs(edev);
  1254. }
  1255. }
  1256. #endif
  1257. rc = request_irq(edev->int_info.msix[i].vector,
  1258. qede_msix_fp_int, 0, edev->fp_array[i].name,
  1259. &edev->fp_array[i]);
  1260. if (rc) {
  1261. DP_ERR(edev, "Request fp %d irq failed\n", i);
  1262. qede_sync_free_irqs(edev);
  1263. return rc;
  1264. }
  1265. DP_VERBOSE(edev, NETIF_MSG_INTR,
  1266. "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
  1267. edev->fp_array[i].name, i,
  1268. &edev->fp_array[i]);
  1269. edev->int_info.used_cnt++;
  1270. }
  1271. return 0;
  1272. }
  1273. static void qede_simd_fp_handler(void *cookie)
  1274. {
  1275. struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
  1276. napi_schedule_irqoff(&fp->napi);
  1277. }
  1278. static int qede_setup_irqs(struct qede_dev *edev)
  1279. {
  1280. int i, rc = 0;
  1281. /* Learn Interrupt configuration */
  1282. rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
  1283. if (rc)
  1284. return rc;
  1285. if (edev->int_info.msix_cnt) {
  1286. rc = qede_req_msix_irqs(edev);
  1287. if (rc)
  1288. return rc;
  1289. edev->ndev->irq = edev->int_info.msix[0].vector;
  1290. } else {
  1291. const struct qed_common_ops *ops;
  1292. /* qed should learn receive the RSS ids and callbacks */
  1293. ops = edev->ops->common;
  1294. for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
  1295. ops->simd_handler_config(edev->cdev,
  1296. &edev->fp_array[i], i,
  1297. qede_simd_fp_handler);
  1298. edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
  1299. }
  1300. return 0;
  1301. }
  1302. static int qede_drain_txq(struct qede_dev *edev,
  1303. struct qede_tx_queue *txq, bool allow_drain)
  1304. {
  1305. int rc, cnt = 1000;
  1306. while (txq->sw_tx_cons != txq->sw_tx_prod) {
  1307. if (!cnt) {
  1308. if (allow_drain) {
  1309. DP_NOTICE(edev,
  1310. "Tx queue[%d] is stuck, requesting MCP to drain\n",
  1311. txq->index);
  1312. rc = edev->ops->common->drain(edev->cdev);
  1313. if (rc)
  1314. return rc;
  1315. return qede_drain_txq(edev, txq, false);
  1316. }
  1317. DP_NOTICE(edev,
  1318. "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
  1319. txq->index, txq->sw_tx_prod,
  1320. txq->sw_tx_cons);
  1321. return -ENODEV;
  1322. }
  1323. cnt--;
  1324. usleep_range(1000, 2000);
  1325. barrier();
  1326. }
  1327. /* FW finished processing, wait for HW to transmit all tx packets */
  1328. usleep_range(1000, 2000);
  1329. return 0;
  1330. }
  1331. static int qede_stop_txq(struct qede_dev *edev,
  1332. struct qede_tx_queue *txq, int rss_id)
  1333. {
  1334. return edev->ops->q_tx_stop(edev->cdev, rss_id, txq->handle);
  1335. }
  1336. static int qede_stop_queues(struct qede_dev *edev)
  1337. {
  1338. struct qed_update_vport_params *vport_update_params;
  1339. struct qed_dev *cdev = edev->cdev;
  1340. struct qede_fastpath *fp;
  1341. int rc, i;
  1342. /* Disable the vport */
  1343. vport_update_params = vzalloc(sizeof(*vport_update_params));
  1344. if (!vport_update_params)
  1345. return -ENOMEM;
  1346. vport_update_params->vport_id = 0;
  1347. vport_update_params->update_vport_active_flg = 1;
  1348. vport_update_params->vport_active_flg = 0;
  1349. vport_update_params->update_rss_flg = 0;
  1350. rc = edev->ops->vport_update(cdev, vport_update_params);
  1351. vfree(vport_update_params);
  1352. if (rc) {
  1353. DP_ERR(edev, "Failed to update vport\n");
  1354. return rc;
  1355. }
  1356. /* Flush Tx queues. If needed, request drain from MCP */
  1357. for_each_queue(i) {
  1358. fp = &edev->fp_array[i];
  1359. if (fp->type & QEDE_FASTPATH_TX) {
  1360. rc = qede_drain_txq(edev, fp->txq, true);
  1361. if (rc)
  1362. return rc;
  1363. }
  1364. if (fp->type & QEDE_FASTPATH_XDP) {
  1365. rc = qede_drain_txq(edev, fp->xdp_tx, true);
  1366. if (rc)
  1367. return rc;
  1368. }
  1369. }
  1370. /* Stop all Queues in reverse order */
  1371. for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
  1372. fp = &edev->fp_array[i];
  1373. /* Stop the Tx Queue(s) */
  1374. if (fp->type & QEDE_FASTPATH_TX) {
  1375. rc = qede_stop_txq(edev, fp->txq, i);
  1376. if (rc)
  1377. return rc;
  1378. }
  1379. /* Stop the Rx Queue */
  1380. if (fp->type & QEDE_FASTPATH_RX) {
  1381. rc = edev->ops->q_rx_stop(cdev, i, fp->rxq->handle);
  1382. if (rc) {
  1383. DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
  1384. return rc;
  1385. }
  1386. }
  1387. /* Stop the XDP forwarding queue */
  1388. if (fp->type & QEDE_FASTPATH_XDP) {
  1389. rc = qede_stop_txq(edev, fp->xdp_tx, i);
  1390. if (rc)
  1391. return rc;
  1392. bpf_prog_put(fp->rxq->xdp_prog);
  1393. }
  1394. }
  1395. /* Stop the vport */
  1396. rc = edev->ops->vport_stop(cdev, 0);
  1397. if (rc)
  1398. DP_ERR(edev, "Failed to stop VPORT\n");
  1399. return rc;
  1400. }
  1401. static int qede_start_txq(struct qede_dev *edev,
  1402. struct qede_fastpath *fp,
  1403. struct qede_tx_queue *txq, u8 rss_id, u16 sb_idx)
  1404. {
  1405. dma_addr_t phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
  1406. u32 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
  1407. struct qed_queue_start_common_params params;
  1408. struct qed_txq_start_ret_params ret_params;
  1409. int rc;
  1410. memset(&params, 0, sizeof(params));
  1411. memset(&ret_params, 0, sizeof(ret_params));
  1412. /* Let the XDP queue share the queue-zone with one of the regular txq.
  1413. * We don't really care about its coalescing.
  1414. */
  1415. if (txq->is_xdp)
  1416. params.queue_id = QEDE_TXQ_XDP_TO_IDX(edev, txq);
  1417. else
  1418. params.queue_id = txq->index;
  1419. params.sb = fp->sb_info->igu_sb_id;
  1420. params.sb_idx = sb_idx;
  1421. rc = edev->ops->q_tx_start(edev->cdev, rss_id, &params, phys_table,
  1422. page_cnt, &ret_params);
  1423. if (rc) {
  1424. DP_ERR(edev, "Start TXQ #%d failed %d\n", txq->index, rc);
  1425. return rc;
  1426. }
  1427. txq->doorbell_addr = ret_params.p_doorbell;
  1428. txq->handle = ret_params.p_handle;
  1429. /* Determine the FW consumer address associated */
  1430. txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[sb_idx];
  1431. /* Prepare the doorbell parameters */
  1432. SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, DB_DEST_XCM);
  1433. SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
  1434. SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_VAL_SEL,
  1435. DQ_XCM_ETH_TX_BD_PROD_CMD);
  1436. txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
  1437. return rc;
  1438. }
  1439. static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
  1440. {
  1441. int vlan_removal_en = 1;
  1442. struct qed_dev *cdev = edev->cdev;
  1443. struct qed_dev_info *qed_info = &edev->dev_info.common;
  1444. struct qed_update_vport_params *vport_update_params;
  1445. struct qed_queue_start_common_params q_params;
  1446. struct qed_start_vport_params start = {0};
  1447. int rc, i;
  1448. if (!edev->num_queues) {
  1449. DP_ERR(edev,
  1450. "Cannot update V-VPORT as active as there are no Rx queues\n");
  1451. return -EINVAL;
  1452. }
  1453. vport_update_params = vzalloc(sizeof(*vport_update_params));
  1454. if (!vport_update_params)
  1455. return -ENOMEM;
  1456. start.handle_ptp_pkts = !!(edev->ptp);
  1457. start.gro_enable = !edev->gro_disable;
  1458. start.mtu = edev->ndev->mtu;
  1459. start.vport_id = 0;
  1460. start.drop_ttl0 = true;
  1461. start.remove_inner_vlan = vlan_removal_en;
  1462. start.clear_stats = clear_stats;
  1463. rc = edev->ops->vport_start(cdev, &start);
  1464. if (rc) {
  1465. DP_ERR(edev, "Start V-PORT failed %d\n", rc);
  1466. goto out;
  1467. }
  1468. DP_VERBOSE(edev, NETIF_MSG_IFUP,
  1469. "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
  1470. start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
  1471. for_each_queue(i) {
  1472. struct qede_fastpath *fp = &edev->fp_array[i];
  1473. dma_addr_t p_phys_table;
  1474. u32 page_cnt;
  1475. if (fp->type & QEDE_FASTPATH_RX) {
  1476. struct qed_rxq_start_ret_params ret_params;
  1477. struct qede_rx_queue *rxq = fp->rxq;
  1478. __le16 *val;
  1479. memset(&ret_params, 0, sizeof(ret_params));
  1480. memset(&q_params, 0, sizeof(q_params));
  1481. q_params.queue_id = rxq->rxq_id;
  1482. q_params.vport_id = 0;
  1483. q_params.sb = fp->sb_info->igu_sb_id;
  1484. q_params.sb_idx = RX_PI;
  1485. p_phys_table =
  1486. qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
  1487. page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
  1488. rc = edev->ops->q_rx_start(cdev, i, &q_params,
  1489. rxq->rx_buf_size,
  1490. rxq->rx_bd_ring.p_phys_addr,
  1491. p_phys_table,
  1492. page_cnt, &ret_params);
  1493. if (rc) {
  1494. DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
  1495. rc);
  1496. goto out;
  1497. }
  1498. /* Use the return parameters */
  1499. rxq->hw_rxq_prod_addr = ret_params.p_prod;
  1500. rxq->handle = ret_params.p_handle;
  1501. val = &fp->sb_info->sb_virt->pi_array[RX_PI];
  1502. rxq->hw_cons_ptr = val;
  1503. qede_update_rx_prod(edev, rxq);
  1504. }
  1505. if (fp->type & QEDE_FASTPATH_XDP) {
  1506. rc = qede_start_txq(edev, fp, fp->xdp_tx, i, XDP_PI);
  1507. if (rc)
  1508. goto out;
  1509. fp->rxq->xdp_prog = bpf_prog_add(edev->xdp_prog, 1);
  1510. if (IS_ERR(fp->rxq->xdp_prog)) {
  1511. rc = PTR_ERR(fp->rxq->xdp_prog);
  1512. fp->rxq->xdp_prog = NULL;
  1513. goto out;
  1514. }
  1515. }
  1516. if (fp->type & QEDE_FASTPATH_TX) {
  1517. rc = qede_start_txq(edev, fp, fp->txq, i, TX_PI(0));
  1518. if (rc)
  1519. goto out;
  1520. }
  1521. }
  1522. /* Prepare and send the vport enable */
  1523. vport_update_params->vport_id = start.vport_id;
  1524. vport_update_params->update_vport_active_flg = 1;
  1525. vport_update_params->vport_active_flg = 1;
  1526. if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
  1527. qed_info->tx_switching) {
  1528. vport_update_params->update_tx_switching_flg = 1;
  1529. vport_update_params->tx_switching_flg = 1;
  1530. }
  1531. qede_fill_rss_params(edev, &vport_update_params->rss_params,
  1532. &vport_update_params->update_rss_flg);
  1533. rc = edev->ops->vport_update(cdev, vport_update_params);
  1534. if (rc)
  1535. DP_ERR(edev, "Update V-PORT failed %d\n", rc);
  1536. out:
  1537. vfree(vport_update_params);
  1538. return rc;
  1539. }
  1540. enum qede_unload_mode {
  1541. QEDE_UNLOAD_NORMAL,
  1542. };
  1543. static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
  1544. bool is_locked)
  1545. {
  1546. struct qed_link_params link_params;
  1547. int rc;
  1548. DP_INFO(edev, "Starting qede unload\n");
  1549. if (!is_locked)
  1550. __qede_lock(edev);
  1551. qede_roce_dev_event_close(edev);
  1552. edev->state = QEDE_STATE_CLOSED;
  1553. qede_ptp_stop(edev);
  1554. /* Close OS Tx */
  1555. netif_tx_disable(edev->ndev);
  1556. netif_carrier_off(edev->ndev);
  1557. /* Reset the link */
  1558. memset(&link_params, 0, sizeof(link_params));
  1559. link_params.link_up = false;
  1560. edev->ops->common->set_link(edev->cdev, &link_params);
  1561. rc = qede_stop_queues(edev);
  1562. if (rc) {
  1563. qede_sync_free_irqs(edev);
  1564. goto out;
  1565. }
  1566. DP_INFO(edev, "Stopped Queues\n");
  1567. qede_vlan_mark_nonconfigured(edev);
  1568. edev->ops->fastpath_stop(edev->cdev);
  1569. #ifdef CONFIG_RFS_ACCEL
  1570. if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
  1571. qede_poll_for_freeing_arfs_filters(edev);
  1572. qede_free_arfs(edev);
  1573. }
  1574. #endif
  1575. /* Release the interrupts */
  1576. qede_sync_free_irqs(edev);
  1577. edev->ops->common->set_fp_int(edev->cdev, 0);
  1578. qede_napi_disable_remove(edev);
  1579. qede_free_mem_load(edev);
  1580. qede_free_fp_array(edev);
  1581. out:
  1582. if (!is_locked)
  1583. __qede_unlock(edev);
  1584. DP_INFO(edev, "Ending qede unload\n");
  1585. }
  1586. enum qede_load_mode {
  1587. QEDE_LOAD_NORMAL,
  1588. QEDE_LOAD_RELOAD,
  1589. };
  1590. static int qede_load(struct qede_dev *edev, enum qede_load_mode mode,
  1591. bool is_locked)
  1592. {
  1593. struct qed_link_params link_params;
  1594. int rc;
  1595. DP_INFO(edev, "Starting qede load\n");
  1596. if (!is_locked)
  1597. __qede_lock(edev);
  1598. rc = qede_set_num_queues(edev);
  1599. if (rc)
  1600. goto out;
  1601. rc = qede_alloc_fp_array(edev);
  1602. if (rc)
  1603. goto out;
  1604. qede_init_fp(edev);
  1605. rc = qede_alloc_mem_load(edev);
  1606. if (rc)
  1607. goto err1;
  1608. DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
  1609. QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
  1610. rc = qede_set_real_num_queues(edev);
  1611. if (rc)
  1612. goto err2;
  1613. #ifdef CONFIG_RFS_ACCEL
  1614. if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
  1615. rc = qede_alloc_arfs(edev);
  1616. if (rc)
  1617. DP_NOTICE(edev, "aRFS memory allocation failed\n");
  1618. }
  1619. #endif
  1620. qede_napi_add_enable(edev);
  1621. DP_INFO(edev, "Napi added and enabled\n");
  1622. rc = qede_setup_irqs(edev);
  1623. if (rc)
  1624. goto err3;
  1625. DP_INFO(edev, "Setup IRQs succeeded\n");
  1626. rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
  1627. if (rc)
  1628. goto err4;
  1629. DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
  1630. /* Add primary mac and set Rx filters */
  1631. ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
  1632. /* Program un-configured VLANs */
  1633. qede_configure_vlan_filters(edev);
  1634. /* Ask for link-up using current configuration */
  1635. memset(&link_params, 0, sizeof(link_params));
  1636. link_params.link_up = true;
  1637. edev->ops->common->set_link(edev->cdev, &link_params);
  1638. qede_roce_dev_event_open(edev);
  1639. qede_ptp_start(edev, (mode == QEDE_LOAD_NORMAL));
  1640. edev->state = QEDE_STATE_OPEN;
  1641. DP_INFO(edev, "Ending successfully qede load\n");
  1642. goto out;
  1643. err4:
  1644. qede_sync_free_irqs(edev);
  1645. memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
  1646. err3:
  1647. qede_napi_disable_remove(edev);
  1648. err2:
  1649. qede_free_mem_load(edev);
  1650. err1:
  1651. edev->ops->common->set_fp_int(edev->cdev, 0);
  1652. qede_free_fp_array(edev);
  1653. edev->num_queues = 0;
  1654. edev->fp_num_tx = 0;
  1655. edev->fp_num_rx = 0;
  1656. out:
  1657. if (!is_locked)
  1658. __qede_unlock(edev);
  1659. return rc;
  1660. }
  1661. /* 'func' should be able to run between unload and reload assuming interface
  1662. * is actually running, or afterwards in case it's currently DOWN.
  1663. */
  1664. void qede_reload(struct qede_dev *edev,
  1665. struct qede_reload_args *args, bool is_locked)
  1666. {
  1667. if (!is_locked)
  1668. __qede_lock(edev);
  1669. /* Since qede_lock is held, internal state wouldn't change even
  1670. * if netdev state would start transitioning. Check whether current
  1671. * internal configuration indicates device is up, then reload.
  1672. */
  1673. if (edev->state == QEDE_STATE_OPEN) {
  1674. qede_unload(edev, QEDE_UNLOAD_NORMAL, true);
  1675. if (args)
  1676. args->func(edev, args);
  1677. qede_load(edev, QEDE_LOAD_RELOAD, true);
  1678. /* Since no one is going to do it for us, re-configure */
  1679. qede_config_rx_mode(edev->ndev);
  1680. } else if (args) {
  1681. args->func(edev, args);
  1682. }
  1683. if (!is_locked)
  1684. __qede_unlock(edev);
  1685. }
  1686. /* called with rtnl_lock */
  1687. static int qede_open(struct net_device *ndev)
  1688. {
  1689. struct qede_dev *edev = netdev_priv(ndev);
  1690. int rc;
  1691. netif_carrier_off(ndev);
  1692. edev->ops->common->set_power_state(edev->cdev, PCI_D0);
  1693. rc = qede_load(edev, QEDE_LOAD_NORMAL, false);
  1694. if (rc)
  1695. return rc;
  1696. udp_tunnel_get_rx_info(ndev);
  1697. edev->ops->common->update_drv_state(edev->cdev, true);
  1698. return 0;
  1699. }
  1700. static int qede_close(struct net_device *ndev)
  1701. {
  1702. struct qede_dev *edev = netdev_priv(ndev);
  1703. qede_unload(edev, QEDE_UNLOAD_NORMAL, false);
  1704. edev->ops->common->update_drv_state(edev->cdev, false);
  1705. return 0;
  1706. }
  1707. static void qede_link_update(void *dev, struct qed_link_output *link)
  1708. {
  1709. struct qede_dev *edev = dev;
  1710. if (!netif_running(edev->ndev)) {
  1711. DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
  1712. return;
  1713. }
  1714. if (link->link_up) {
  1715. if (!netif_carrier_ok(edev->ndev)) {
  1716. DP_NOTICE(edev, "Link is up\n");
  1717. netif_tx_start_all_queues(edev->ndev);
  1718. netif_carrier_on(edev->ndev);
  1719. }
  1720. } else {
  1721. if (netif_carrier_ok(edev->ndev)) {
  1722. DP_NOTICE(edev, "Link is down\n");
  1723. netif_tx_disable(edev->ndev);
  1724. netif_carrier_off(edev->ndev);
  1725. }
  1726. }
  1727. }