malidp_drv.c 13 KB

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  1. /*
  2. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  3. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4. *
  5. * This program is free software and is provided to you under the terms of the
  6. * GNU General Public License version 2 as published by the Free Software
  7. * Foundation, and any use by you of this program is subject to the terms
  8. * of such GNU licence.
  9. *
  10. * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  11. */
  12. #include <linux/module.h>
  13. #include <linux/clk.h>
  14. #include <linux/component.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/of_reserved_mem.h>
  18. #include <drm/drmP.h>
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include <drm/drm_fb_cma_helper.h>
  25. #include <drm/drm_gem_cma_helper.h>
  26. #include <drm/drm_of.h>
  27. #include "malidp_drv.h"
  28. #include "malidp_regs.h"
  29. #include "malidp_hw.h"
  30. #define MALIDP_CONF_VALID_TIMEOUT 250
  31. /*
  32. * set the "config valid" bit and wait until the hardware acts on it
  33. */
  34. static int malidp_set_and_wait_config_valid(struct drm_device *drm)
  35. {
  36. struct malidp_drm *malidp = drm->dev_private;
  37. struct malidp_hw_device *hwdev = malidp->dev;
  38. int ret;
  39. atomic_set(&malidp->config_valid, 0);
  40. hwdev->set_config_valid(hwdev);
  41. /* don't wait for config_valid flag if we are in config mode */
  42. if (hwdev->in_config_mode(hwdev))
  43. return 0;
  44. ret = wait_event_interruptible_timeout(malidp->wq,
  45. atomic_read(&malidp->config_valid) == 1,
  46. msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
  47. return (ret > 0) ? 0 : -ETIMEDOUT;
  48. }
  49. static void malidp_output_poll_changed(struct drm_device *drm)
  50. {
  51. struct malidp_drm *malidp = drm->dev_private;
  52. drm_fbdev_cma_hotplug_event(malidp->fbdev);
  53. }
  54. static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
  55. {
  56. struct drm_pending_vblank_event *event;
  57. struct drm_device *drm = state->dev;
  58. struct malidp_drm *malidp = drm->dev_private;
  59. int ret = malidp_set_and_wait_config_valid(drm);
  60. if (ret)
  61. DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
  62. event = malidp->crtc.state->event;
  63. if (event) {
  64. malidp->crtc.state->event = NULL;
  65. spin_lock_irq(&drm->event_lock);
  66. if (drm_crtc_vblank_get(&malidp->crtc) == 0)
  67. drm_crtc_arm_vblank_event(&malidp->crtc, event);
  68. else
  69. drm_crtc_send_vblank_event(&malidp->crtc, event);
  70. spin_unlock_irq(&drm->event_lock);
  71. }
  72. drm_atomic_helper_commit_hw_done(state);
  73. }
  74. static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
  75. {
  76. struct drm_device *drm = state->dev;
  77. drm_atomic_helper_commit_modeset_disables(drm, state);
  78. drm_atomic_helper_commit_modeset_enables(drm, state);
  79. drm_atomic_helper_commit_planes(drm, state,
  80. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  81. malidp_atomic_commit_hw_done(state);
  82. drm_atomic_helper_wait_for_vblanks(drm, state);
  83. drm_atomic_helper_cleanup_planes(drm, state);
  84. }
  85. static struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
  86. .atomic_commit_tail = malidp_atomic_commit_tail,
  87. };
  88. static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
  89. .fb_create = drm_fb_cma_create,
  90. .output_poll_changed = malidp_output_poll_changed,
  91. .atomic_check = drm_atomic_helper_check,
  92. .atomic_commit = drm_atomic_helper_commit,
  93. };
  94. static int malidp_enable_vblank(struct drm_device *drm, unsigned int crtc)
  95. {
  96. struct malidp_drm *malidp = drm->dev_private;
  97. struct malidp_hw_device *hwdev = malidp->dev;
  98. malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
  99. hwdev->map.de_irq_map.vsync_irq);
  100. return 0;
  101. }
  102. static void malidp_disable_vblank(struct drm_device *drm, unsigned int pipe)
  103. {
  104. struct malidp_drm *malidp = drm->dev_private;
  105. struct malidp_hw_device *hwdev = malidp->dev;
  106. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
  107. hwdev->map.de_irq_map.vsync_irq);
  108. }
  109. static int malidp_init(struct drm_device *drm)
  110. {
  111. int ret;
  112. struct malidp_drm *malidp = drm->dev_private;
  113. struct malidp_hw_device *hwdev = malidp->dev;
  114. drm_mode_config_init(drm);
  115. drm->mode_config.min_width = hwdev->min_line_size;
  116. drm->mode_config.min_height = hwdev->min_line_size;
  117. drm->mode_config.max_width = hwdev->max_line_size;
  118. drm->mode_config.max_height = hwdev->max_line_size;
  119. drm->mode_config.funcs = &malidp_mode_config_funcs;
  120. drm->mode_config.helper_private = &malidp_mode_config_helpers;
  121. ret = malidp_crtc_init(drm);
  122. if (ret) {
  123. drm_mode_config_cleanup(drm);
  124. return ret;
  125. }
  126. return 0;
  127. }
  128. static void malidp_fini(struct drm_device *drm)
  129. {
  130. malidp_de_planes_destroy(drm);
  131. drm_mode_config_cleanup(drm);
  132. }
  133. static int malidp_irq_init(struct platform_device *pdev)
  134. {
  135. int irq_de, irq_se, ret = 0;
  136. struct drm_device *drm = dev_get_drvdata(&pdev->dev);
  137. /* fetch the interrupts from DT */
  138. irq_de = platform_get_irq_byname(pdev, "DE");
  139. if (irq_de < 0) {
  140. DRM_ERROR("no 'DE' IRQ specified!\n");
  141. return irq_de;
  142. }
  143. irq_se = platform_get_irq_byname(pdev, "SE");
  144. if (irq_se < 0) {
  145. DRM_ERROR("no 'SE' IRQ specified!\n");
  146. return irq_se;
  147. }
  148. ret = malidp_de_irq_init(drm, irq_de);
  149. if (ret)
  150. return ret;
  151. ret = malidp_se_irq_init(drm, irq_se);
  152. if (ret) {
  153. malidp_de_irq_fini(drm);
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. static void malidp_lastclose(struct drm_device *drm)
  159. {
  160. struct malidp_drm *malidp = drm->dev_private;
  161. drm_fbdev_cma_restore_mode(malidp->fbdev);
  162. }
  163. static const struct file_operations fops = {
  164. .owner = THIS_MODULE,
  165. .open = drm_open,
  166. .release = drm_release,
  167. .unlocked_ioctl = drm_ioctl,
  168. #ifdef CONFIG_COMPAT
  169. .compat_ioctl = drm_compat_ioctl,
  170. #endif
  171. .poll = drm_poll,
  172. .read = drm_read,
  173. .llseek = noop_llseek,
  174. .mmap = drm_gem_cma_mmap,
  175. };
  176. static struct drm_driver malidp_driver = {
  177. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
  178. DRIVER_PRIME,
  179. .lastclose = malidp_lastclose,
  180. .get_vblank_counter = drm_vblank_no_hw_counter,
  181. .enable_vblank = malidp_enable_vblank,
  182. .disable_vblank = malidp_disable_vblank,
  183. .gem_free_object_unlocked = drm_gem_cma_free_object,
  184. .gem_vm_ops = &drm_gem_cma_vm_ops,
  185. .dumb_create = drm_gem_cma_dumb_create,
  186. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  187. .dumb_destroy = drm_gem_dumb_destroy,
  188. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  189. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  190. .gem_prime_export = drm_gem_prime_export,
  191. .gem_prime_import = drm_gem_prime_import,
  192. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  193. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  194. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  195. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  196. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  197. .fops = &fops,
  198. .name = "mali-dp",
  199. .desc = "ARM Mali Display Processor driver",
  200. .date = "20160106",
  201. .major = 1,
  202. .minor = 0,
  203. };
  204. static const struct of_device_id malidp_drm_of_match[] = {
  205. {
  206. .compatible = "arm,mali-dp500",
  207. .data = &malidp_device[MALIDP_500]
  208. },
  209. {
  210. .compatible = "arm,mali-dp550",
  211. .data = &malidp_device[MALIDP_550]
  212. },
  213. {
  214. .compatible = "arm,mali-dp650",
  215. .data = &malidp_device[MALIDP_650]
  216. },
  217. {},
  218. };
  219. MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
  220. #define MAX_OUTPUT_CHANNELS 3
  221. static int malidp_bind(struct device *dev)
  222. {
  223. struct resource *res;
  224. struct drm_device *drm;
  225. struct device_node *ep;
  226. struct malidp_drm *malidp;
  227. struct malidp_hw_device *hwdev;
  228. struct platform_device *pdev = to_platform_device(dev);
  229. /* number of lines for the R, G and B output */
  230. u8 output_width[MAX_OUTPUT_CHANNELS];
  231. int ret = 0, i;
  232. u32 version, out_depth = 0;
  233. malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
  234. if (!malidp)
  235. return -ENOMEM;
  236. hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
  237. if (!hwdev)
  238. return -ENOMEM;
  239. /*
  240. * copy the associated data from malidp_drm_of_match to avoid
  241. * having to keep a reference to the OF node after binding
  242. */
  243. memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
  244. malidp->dev = hwdev;
  245. INIT_LIST_HEAD(&malidp->event_list);
  246. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  247. hwdev->regs = devm_ioremap_resource(dev, res);
  248. if (IS_ERR(hwdev->regs))
  249. return PTR_ERR(hwdev->regs);
  250. hwdev->pclk = devm_clk_get(dev, "pclk");
  251. if (IS_ERR(hwdev->pclk))
  252. return PTR_ERR(hwdev->pclk);
  253. hwdev->aclk = devm_clk_get(dev, "aclk");
  254. if (IS_ERR(hwdev->aclk))
  255. return PTR_ERR(hwdev->aclk);
  256. hwdev->mclk = devm_clk_get(dev, "mclk");
  257. if (IS_ERR(hwdev->mclk))
  258. return PTR_ERR(hwdev->mclk);
  259. hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
  260. if (IS_ERR(hwdev->pxlclk))
  261. return PTR_ERR(hwdev->pxlclk);
  262. /* Get the optional framebuffer memory resource */
  263. ret = of_reserved_mem_device_init(dev);
  264. if (ret && ret != -ENODEV)
  265. return ret;
  266. drm = drm_dev_alloc(&malidp_driver, dev);
  267. if (IS_ERR(drm)) {
  268. ret = PTR_ERR(drm);
  269. goto alloc_fail;
  270. }
  271. /* Enable APB clock in order to get access to the registers */
  272. clk_prepare_enable(hwdev->pclk);
  273. /*
  274. * Enable AXI clock and main clock so that prefetch can start once
  275. * the registers are set
  276. */
  277. clk_prepare_enable(hwdev->aclk);
  278. clk_prepare_enable(hwdev->mclk);
  279. ret = hwdev->query_hw(hwdev);
  280. if (ret) {
  281. DRM_ERROR("Invalid HW configuration\n");
  282. goto query_hw_fail;
  283. }
  284. version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
  285. DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
  286. (version >> 12) & 0xf, (version >> 8) & 0xf);
  287. /* set the number of lines used for output of RGB data */
  288. ret = of_property_read_u8_array(dev->of_node,
  289. "arm,malidp-output-port-lines",
  290. output_width, MAX_OUTPUT_CHANNELS);
  291. if (ret)
  292. goto query_hw_fail;
  293. for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
  294. out_depth = (out_depth << 8) | (output_width[i] & 0xf);
  295. malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
  296. drm->dev_private = malidp;
  297. dev_set_drvdata(dev, drm);
  298. atomic_set(&malidp->config_valid, 0);
  299. init_waitqueue_head(&malidp->wq);
  300. ret = malidp_init(drm);
  301. if (ret < 0)
  302. goto init_fail;
  303. ret = drm_dev_register(drm, 0);
  304. if (ret)
  305. goto register_fail;
  306. /* Set the CRTC's port so that the encoder component can find it */
  307. ep = of_graph_get_next_endpoint(dev->of_node, NULL);
  308. if (!ep) {
  309. ret = -EINVAL;
  310. goto port_fail;
  311. }
  312. malidp->crtc.port = of_get_next_parent(ep);
  313. ret = component_bind_all(dev, drm);
  314. if (ret) {
  315. DRM_ERROR("Failed to bind all components\n");
  316. goto bind_fail;
  317. }
  318. ret = malidp_irq_init(pdev);
  319. if (ret < 0)
  320. goto irq_init_fail;
  321. drm->irq_enabled = true;
  322. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  323. if (ret < 0) {
  324. DRM_ERROR("failed to initialise vblank\n");
  325. goto vblank_fail;
  326. }
  327. drm_mode_config_reset(drm);
  328. malidp->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
  329. drm->mode_config.num_connector);
  330. if (IS_ERR(malidp->fbdev)) {
  331. ret = PTR_ERR(malidp->fbdev);
  332. malidp->fbdev = NULL;
  333. goto fbdev_fail;
  334. }
  335. drm_kms_helper_poll_init(drm);
  336. return 0;
  337. fbdev_fail:
  338. drm_vblank_cleanup(drm);
  339. vblank_fail:
  340. malidp_se_irq_fini(drm);
  341. malidp_de_irq_fini(drm);
  342. drm->irq_enabled = false;
  343. irq_init_fail:
  344. component_unbind_all(dev, drm);
  345. bind_fail:
  346. of_node_put(malidp->crtc.port);
  347. malidp->crtc.port = NULL;
  348. port_fail:
  349. drm_dev_unregister(drm);
  350. register_fail:
  351. malidp_fini(drm);
  352. init_fail:
  353. drm->dev_private = NULL;
  354. dev_set_drvdata(dev, NULL);
  355. query_hw_fail:
  356. clk_disable_unprepare(hwdev->mclk);
  357. clk_disable_unprepare(hwdev->aclk);
  358. clk_disable_unprepare(hwdev->pclk);
  359. drm_dev_unref(drm);
  360. alloc_fail:
  361. of_reserved_mem_device_release(dev);
  362. return ret;
  363. }
  364. static void malidp_unbind(struct device *dev)
  365. {
  366. struct drm_device *drm = dev_get_drvdata(dev);
  367. struct malidp_drm *malidp = drm->dev_private;
  368. struct malidp_hw_device *hwdev = malidp->dev;
  369. if (malidp->fbdev) {
  370. drm_fbdev_cma_fini(malidp->fbdev);
  371. malidp->fbdev = NULL;
  372. }
  373. drm_kms_helper_poll_fini(drm);
  374. malidp_se_irq_fini(drm);
  375. malidp_de_irq_fini(drm);
  376. drm_vblank_cleanup(drm);
  377. component_unbind_all(dev, drm);
  378. of_node_put(malidp->crtc.port);
  379. malidp->crtc.port = NULL;
  380. drm_dev_unregister(drm);
  381. malidp_fini(drm);
  382. drm->dev_private = NULL;
  383. dev_set_drvdata(dev, NULL);
  384. clk_disable_unprepare(hwdev->mclk);
  385. clk_disable_unprepare(hwdev->aclk);
  386. clk_disable_unprepare(hwdev->pclk);
  387. drm_dev_unref(drm);
  388. of_reserved_mem_device_release(dev);
  389. }
  390. static const struct component_master_ops malidp_master_ops = {
  391. .bind = malidp_bind,
  392. .unbind = malidp_unbind,
  393. };
  394. static int malidp_compare_dev(struct device *dev, void *data)
  395. {
  396. struct device_node *np = data;
  397. return dev->of_node == np;
  398. }
  399. static int malidp_platform_probe(struct platform_device *pdev)
  400. {
  401. struct device_node *port, *ep;
  402. struct component_match *match = NULL;
  403. if (!pdev->dev.of_node)
  404. return -ENODEV;
  405. /* there is only one output port inside each device, find it */
  406. ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
  407. if (!ep)
  408. return -ENODEV;
  409. if (!of_device_is_available(ep)) {
  410. of_node_put(ep);
  411. return -ENODEV;
  412. }
  413. /* add the remote encoder port as component */
  414. port = of_graph_get_remote_port_parent(ep);
  415. of_node_put(ep);
  416. if (!port || !of_device_is_available(port)) {
  417. of_node_put(port);
  418. return -EAGAIN;
  419. }
  420. drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
  421. port);
  422. of_node_put(port);
  423. return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
  424. match);
  425. }
  426. static int malidp_platform_remove(struct platform_device *pdev)
  427. {
  428. component_master_del(&pdev->dev, &malidp_master_ops);
  429. return 0;
  430. }
  431. static struct platform_driver malidp_platform_driver = {
  432. .probe = malidp_platform_probe,
  433. .remove = malidp_platform_remove,
  434. .driver = {
  435. .name = "mali-dp",
  436. .of_match_table = malidp_drm_of_match,
  437. },
  438. };
  439. module_platform_driver(malidp_platform_driver);
  440. MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
  441. MODULE_DESCRIPTION("ARM Mali DP DRM driver");
  442. MODULE_LICENSE("GPL v2");