cs35l32.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592
  1. /*
  2. * cs35l32.c -- CS35L32 ALSA SoC audio driver
  3. *
  4. * Copyright 2014 CirrusLogic, Inc.
  5. *
  6. * Author: Brian Austin <brian.austin@cirrus.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/i2c.h>
  19. #include <linux/gpio.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/of_device.h>
  26. #include <sound/core.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/soc.h>
  30. #include <sound/soc-dapm.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include <dt-bindings/sound/cs35l32.h>
  34. #include "cs35l32.h"
  35. #define CS35L32_NUM_SUPPLIES 2
  36. static const char *const cs35l32_supply_names[CS35L32_NUM_SUPPLIES] = {
  37. "VA",
  38. "VP",
  39. };
  40. struct cs35l32_private {
  41. struct regmap *regmap;
  42. struct snd_soc_codec *codec;
  43. struct regulator_bulk_data supplies[CS35L32_NUM_SUPPLIES];
  44. struct cs35l32_platform_data pdata;
  45. struct gpio_desc *reset_gpio;
  46. };
  47. static const struct reg_default cs35l32_reg_defaults[] = {
  48. { 0x06, 0x04 }, /* Power Ctl 1 */
  49. { 0x07, 0xE8 }, /* Power Ctl 2 */
  50. { 0x08, 0x40 }, /* Clock Ctl */
  51. { 0x09, 0x20 }, /* Low Battery Threshold */
  52. { 0x0A, 0x00 }, /* Voltage Monitor [RO] */
  53. { 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
  54. { 0x0C, 0x07 }, /* IMON Scaling */
  55. { 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
  56. { 0x0F, 0x20 }, /* Serial Port Control */
  57. { 0x10, 0x14 }, /* Class D Amp CTL */
  58. { 0x11, 0x00 }, /* Protection Release CTL */
  59. { 0x12, 0xFF }, /* Interrupt Mask 1 */
  60. { 0x13, 0xFF }, /* Interrupt Mask 2 */
  61. { 0x14, 0xFF }, /* Interrupt Mask 3 */
  62. { 0x19, 0x00 }, /* LED Flash Mode Current */
  63. { 0x1A, 0x00 }, /* LED Movie Mode Current */
  64. { 0x1B, 0x20 }, /* LED Flash Timer */
  65. { 0x1C, 0x00 }, /* LED Flash Inhibit Current */
  66. };
  67. static bool cs35l32_readable_register(struct device *dev, unsigned int reg)
  68. {
  69. switch (reg) {
  70. case CS35L32_DEVID_AB ... CS35L32_AUDIO_LED_MNGR:
  71. case CS35L32_ADSP_CTL ... CS35L32_FLASH_INHIBIT:
  72. return true;
  73. default:
  74. return false;
  75. }
  76. }
  77. static bool cs35l32_volatile_register(struct device *dev, unsigned int reg)
  78. {
  79. switch (reg) {
  80. case CS35L32_DEVID_AB ... CS35L32_REV_ID:
  81. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  82. return true;
  83. default:
  84. return false;
  85. }
  86. }
  87. static bool cs35l32_precious_register(struct device *dev, unsigned int reg)
  88. {
  89. switch (reg) {
  90. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  91. return true;
  92. default:
  93. return false;
  94. }
  95. }
  96. static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 300, 0);
  97. static const struct snd_kcontrol_new imon_ctl =
  98. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 6, 1, 1);
  99. static const struct snd_kcontrol_new vmon_ctl =
  100. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 7, 1, 1);
  101. static const struct snd_kcontrol_new vpmon_ctl =
  102. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 5, 1, 1);
  103. static const struct snd_kcontrol_new cs35l32_snd_controls[] = {
  104. SOC_SINGLE_TLV("Speaker Volume", CS35L32_CLASSD_CTL,
  105. 3, 0x04, 1, classd_ctl_tlv),
  106. SOC_SINGLE("Zero Cross Switch", CS35L32_CLASSD_CTL, 2, 1, 0),
  107. SOC_SINGLE("Gain Manager Switch", CS35L32_AUDIO_LED_MNGR, 3, 1, 0),
  108. };
  109. static const struct snd_soc_dapm_widget cs35l32_dapm_widgets[] = {
  110. SND_SOC_DAPM_SUPPLY("BOOST", CS35L32_PWRCTL1, 2, 1, NULL, 0),
  111. SND_SOC_DAPM_OUT_DRV("Speaker", CS35L32_PWRCTL1, 7, 1, NULL, 0),
  112. SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L32_PWRCTL2, 3, 1),
  113. SND_SOC_DAPM_INPUT("VP"),
  114. SND_SOC_DAPM_INPUT("ISENSE"),
  115. SND_SOC_DAPM_INPUT("VSENSE"),
  116. SND_SOC_DAPM_SWITCH("VMON ADC", CS35L32_PWRCTL2, 7, 1, &vmon_ctl),
  117. SND_SOC_DAPM_SWITCH("IMON ADC", CS35L32_PWRCTL2, 6, 1, &imon_ctl),
  118. SND_SOC_DAPM_SWITCH("VPMON ADC", CS35L32_PWRCTL2, 5, 1, &vpmon_ctl),
  119. };
  120. static const struct snd_soc_dapm_route cs35l32_audio_map[] = {
  121. {"Speaker", NULL, "BOOST"},
  122. {"VMON ADC", NULL, "VSENSE"},
  123. {"IMON ADC", NULL, "ISENSE"},
  124. {"VPMON ADC", NULL, "VP"},
  125. {"SDOUT", "Switch", "VMON ADC"},
  126. {"SDOUT", "Switch", "IMON ADC"},
  127. {"SDOUT", "Switch", "VPMON ADC"},
  128. {"Capture", NULL, "SDOUT"},
  129. };
  130. static int cs35l32_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  131. {
  132. struct snd_soc_codec *codec = codec_dai->codec;
  133. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  134. case SND_SOC_DAIFMT_CBM_CFM:
  135. snd_soc_update_bits(codec, CS35L32_ADSP_CTL,
  136. CS35L32_ADSP_MASTER_MASK,
  137. CS35L32_ADSP_MASTER_MASK);
  138. break;
  139. case SND_SOC_DAIFMT_CBS_CFS:
  140. snd_soc_update_bits(codec, CS35L32_ADSP_CTL,
  141. CS35L32_ADSP_MASTER_MASK, 0);
  142. break;
  143. default:
  144. return -EINVAL;
  145. }
  146. return 0;
  147. }
  148. static int cs35l32_set_tristate(struct snd_soc_dai *dai, int tristate)
  149. {
  150. struct snd_soc_codec *codec = dai->codec;
  151. return snd_soc_update_bits(codec, CS35L32_PWRCTL2,
  152. CS35L32_SDOUT_3ST, tristate << 3);
  153. }
  154. static const struct snd_soc_dai_ops cs35l32_ops = {
  155. .set_fmt = cs35l32_set_dai_fmt,
  156. .set_tristate = cs35l32_set_tristate,
  157. };
  158. static struct snd_soc_dai_driver cs35l32_dai[] = {
  159. {
  160. .name = "cs35l32-monitor",
  161. .id = 0,
  162. .capture = {
  163. .stream_name = "Capture",
  164. .channels_min = 2,
  165. .channels_max = 2,
  166. .rates = CS35L32_RATES,
  167. .formats = CS35L32_FORMATS,
  168. },
  169. .ops = &cs35l32_ops,
  170. .symmetric_rates = 1,
  171. }
  172. };
  173. static int cs35l32_codec_set_sysclk(struct snd_soc_codec *codec,
  174. int clk_id, int source, unsigned int freq, int dir)
  175. {
  176. unsigned int val;
  177. switch (freq) {
  178. case 6000000:
  179. val = CS35L32_MCLK_RATIO;
  180. break;
  181. case 12000000:
  182. val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO;
  183. break;
  184. case 6144000:
  185. val = 0;
  186. break;
  187. case 12288000:
  188. val = CS35L32_MCLK_DIV2_MASK;
  189. break;
  190. default:
  191. return -EINVAL;
  192. }
  193. return snd_soc_update_bits(codec, CS35L32_CLK_CTL,
  194. CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val);
  195. }
  196. static const struct snd_soc_codec_driver soc_codec_dev_cs35l32 = {
  197. .set_sysclk = cs35l32_codec_set_sysclk,
  198. .dapm_widgets = cs35l32_dapm_widgets,
  199. .num_dapm_widgets = ARRAY_SIZE(cs35l32_dapm_widgets),
  200. .dapm_routes = cs35l32_audio_map,
  201. .num_dapm_routes = ARRAY_SIZE(cs35l32_audio_map),
  202. .controls = cs35l32_snd_controls,
  203. .num_controls = ARRAY_SIZE(cs35l32_snd_controls),
  204. };
  205. /* Current and threshold powerup sequence Pg37 in datasheet */
  206. static const struct reg_sequence cs35l32_monitor_patch[] = {
  207. { 0x00, 0x99 },
  208. { 0x48, 0x17 },
  209. { 0x49, 0x56 },
  210. { 0x43, 0x01 },
  211. { 0x3B, 0x62 },
  212. { 0x3C, 0x80 },
  213. { 0x00, 0x00 },
  214. };
  215. static const struct regmap_config cs35l32_regmap = {
  216. .reg_bits = 8,
  217. .val_bits = 8,
  218. .max_register = CS35L32_MAX_REGISTER,
  219. .reg_defaults = cs35l32_reg_defaults,
  220. .num_reg_defaults = ARRAY_SIZE(cs35l32_reg_defaults),
  221. .volatile_reg = cs35l32_volatile_register,
  222. .readable_reg = cs35l32_readable_register,
  223. .precious_reg = cs35l32_precious_register,
  224. .cache_type = REGCACHE_RBTREE,
  225. };
  226. static int cs35l32_handle_of_data(struct i2c_client *i2c_client,
  227. struct cs35l32_platform_data *pdata)
  228. {
  229. struct device_node *np = i2c_client->dev.of_node;
  230. unsigned int val;
  231. if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
  232. pdata->sdout_share = val;
  233. if (of_property_read_u32(np, "cirrus,boost-manager", &val))
  234. val = -1u;
  235. switch (val) {
  236. case CS35L32_BOOST_MGR_AUTO:
  237. case CS35L32_BOOST_MGR_AUTO_AUDIO:
  238. case CS35L32_BOOST_MGR_BYPASS:
  239. case CS35L32_BOOST_MGR_FIXED:
  240. pdata->boost_mng = val;
  241. break;
  242. case -1u:
  243. default:
  244. dev_err(&i2c_client->dev,
  245. "Wrong cirrus,boost-manager DT value %d\n", val);
  246. pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
  247. }
  248. if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
  249. val = -1u;
  250. switch (val) {
  251. case CS35L32_DATA_CFG_LR_VP:
  252. case CS35L32_DATA_CFG_LR_STAT:
  253. case CS35L32_DATA_CFG_LR:
  254. case CS35L32_DATA_CFG_LR_VPSTAT:
  255. pdata->sdout_datacfg = val;
  256. break;
  257. case -1u:
  258. default:
  259. dev_err(&i2c_client->dev,
  260. "Wrong cirrus,sdout-datacfg DT value %d\n", val);
  261. pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
  262. }
  263. if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
  264. val = -1u;
  265. switch (val) {
  266. case CS35L32_BATT_THRESH_3_1V:
  267. case CS35L32_BATT_THRESH_3_2V:
  268. case CS35L32_BATT_THRESH_3_3V:
  269. case CS35L32_BATT_THRESH_3_4V:
  270. pdata->batt_thresh = val;
  271. break;
  272. case -1u:
  273. default:
  274. dev_err(&i2c_client->dev,
  275. "Wrong cirrus,battery-threshold DT value %d\n", val);
  276. pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
  277. }
  278. if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
  279. val = -1u;
  280. switch (val) {
  281. case CS35L32_BATT_RECOV_3_1V:
  282. case CS35L32_BATT_RECOV_3_2V:
  283. case CS35L32_BATT_RECOV_3_3V:
  284. case CS35L32_BATT_RECOV_3_4V:
  285. case CS35L32_BATT_RECOV_3_5V:
  286. case CS35L32_BATT_RECOV_3_6V:
  287. pdata->batt_recov = val;
  288. break;
  289. case -1u:
  290. default:
  291. dev_err(&i2c_client->dev,
  292. "Wrong cirrus,battery-recovery DT value %d\n", val);
  293. pdata->batt_recov = CS35L32_BATT_RECOV_3_4V;
  294. }
  295. return 0;
  296. }
  297. static int cs35l32_i2c_probe(struct i2c_client *i2c_client,
  298. const struct i2c_device_id *id)
  299. {
  300. struct cs35l32_private *cs35l32;
  301. struct cs35l32_platform_data *pdata =
  302. dev_get_platdata(&i2c_client->dev);
  303. int ret, i;
  304. unsigned int devid = 0;
  305. unsigned int reg;
  306. cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l32_private),
  307. GFP_KERNEL);
  308. if (!cs35l32) {
  309. dev_err(&i2c_client->dev, "could not allocate codec\n");
  310. return -ENOMEM;
  311. }
  312. i2c_set_clientdata(i2c_client, cs35l32);
  313. cs35l32->regmap = devm_regmap_init_i2c(i2c_client, &cs35l32_regmap);
  314. if (IS_ERR(cs35l32->regmap)) {
  315. ret = PTR_ERR(cs35l32->regmap);
  316. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  317. return ret;
  318. }
  319. if (pdata) {
  320. cs35l32->pdata = *pdata;
  321. } else {
  322. pdata = devm_kzalloc(&i2c_client->dev,
  323. sizeof(struct cs35l32_platform_data),
  324. GFP_KERNEL);
  325. if (!pdata) {
  326. dev_err(&i2c_client->dev, "could not allocate pdata\n");
  327. return -ENOMEM;
  328. }
  329. if (i2c_client->dev.of_node) {
  330. ret = cs35l32_handle_of_data(i2c_client,
  331. &cs35l32->pdata);
  332. if (ret != 0)
  333. return ret;
  334. }
  335. }
  336. for (i = 0; i < ARRAY_SIZE(cs35l32->supplies); i++)
  337. cs35l32->supplies[i].supply = cs35l32_supply_names[i];
  338. ret = devm_regulator_bulk_get(&i2c_client->dev,
  339. ARRAY_SIZE(cs35l32->supplies),
  340. cs35l32->supplies);
  341. if (ret != 0) {
  342. dev_err(&i2c_client->dev,
  343. "Failed to request supplies: %d\n", ret);
  344. return ret;
  345. }
  346. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  347. cs35l32->supplies);
  348. if (ret != 0) {
  349. dev_err(&i2c_client->dev,
  350. "Failed to enable supplies: %d\n", ret);
  351. return ret;
  352. }
  353. /* Reset the Device */
  354. cs35l32->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  355. "reset", GPIOD_OUT_LOW);
  356. if (IS_ERR(cs35l32->reset_gpio))
  357. return PTR_ERR(cs35l32->reset_gpio);
  358. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  359. /* initialize codec */
  360. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_AB, &reg);
  361. devid = (reg & 0xFF) << 12;
  362. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_CD, &reg);
  363. devid |= (reg & 0xFF) << 4;
  364. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_E, &reg);
  365. devid |= (reg & 0xF0) >> 4;
  366. if (devid != CS35L32_CHIP_ID) {
  367. ret = -ENODEV;
  368. dev_err(&i2c_client->dev,
  369. "CS35L32 Device ID (%X). Expected %X\n",
  370. devid, CS35L32_CHIP_ID);
  371. return ret;
  372. }
  373. ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, &reg);
  374. if (ret < 0) {
  375. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  376. return ret;
  377. }
  378. ret = regmap_register_patch(cs35l32->regmap, cs35l32_monitor_patch,
  379. ARRAY_SIZE(cs35l32_monitor_patch));
  380. if (ret < 0) {
  381. dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
  382. return ret;
  383. }
  384. dev_info(&i2c_client->dev,
  385. "Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF);
  386. /* Setup VBOOST Management */
  387. if (cs35l32->pdata.boost_mng)
  388. regmap_update_bits(cs35l32->regmap, CS35L32_AUDIO_LED_MNGR,
  389. CS35L32_BOOST_MASK,
  390. cs35l32->pdata.boost_mng);
  391. /* Setup ADSP Format Config */
  392. if (cs35l32->pdata.sdout_share)
  393. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  394. CS35L32_ADSP_SHARE_MASK,
  395. cs35l32->pdata.sdout_share << 3);
  396. /* Setup ADSP Data Configuration */
  397. if (cs35l32->pdata.sdout_datacfg)
  398. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  399. CS35L32_ADSP_DATACFG_MASK,
  400. cs35l32->pdata.sdout_datacfg << 4);
  401. /* Setup Low Battery Recovery */
  402. if (cs35l32->pdata.batt_recov)
  403. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  404. CS35L32_BATT_REC_MASK,
  405. cs35l32->pdata.batt_recov << 1);
  406. /* Setup Low Battery Threshold */
  407. if (cs35l32->pdata.batt_thresh)
  408. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  409. CS35L32_BATT_THRESH_MASK,
  410. cs35l32->pdata.batt_thresh << 4);
  411. /* Power down the AMP */
  412. regmap_update_bits(cs35l32->regmap, CS35L32_PWRCTL1, CS35L32_PDN_AMP,
  413. CS35L32_PDN_AMP);
  414. /* Clear MCLK Error Bit since we don't have the clock yet */
  415. ret = regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, &reg);
  416. ret = snd_soc_register_codec(&i2c_client->dev,
  417. &soc_codec_dev_cs35l32, cs35l32_dai,
  418. ARRAY_SIZE(cs35l32_dai));
  419. if (ret < 0)
  420. goto err_disable;
  421. return 0;
  422. err_disable:
  423. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  424. cs35l32->supplies);
  425. return ret;
  426. }
  427. static int cs35l32_i2c_remove(struct i2c_client *i2c_client)
  428. {
  429. struct cs35l32_private *cs35l32 = i2c_get_clientdata(i2c_client);
  430. snd_soc_unregister_codec(&i2c_client->dev);
  431. /* Hold down reset */
  432. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  433. return 0;
  434. }
  435. #ifdef CONFIG_PM
  436. static int cs35l32_runtime_suspend(struct device *dev)
  437. {
  438. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  439. regcache_cache_only(cs35l32->regmap, true);
  440. regcache_mark_dirty(cs35l32->regmap);
  441. /* Hold down reset */
  442. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  443. /* remove power */
  444. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  445. cs35l32->supplies);
  446. return 0;
  447. }
  448. static int cs35l32_runtime_resume(struct device *dev)
  449. {
  450. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  451. int ret;
  452. /* Enable power */
  453. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  454. cs35l32->supplies);
  455. if (ret != 0) {
  456. dev_err(dev, "Failed to enable supplies: %d\n",
  457. ret);
  458. return ret;
  459. }
  460. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  461. regcache_cache_only(cs35l32->regmap, false);
  462. regcache_sync(cs35l32->regmap);
  463. return 0;
  464. }
  465. #endif
  466. static const struct dev_pm_ops cs35l32_runtime_pm = {
  467. SET_RUNTIME_PM_OPS(cs35l32_runtime_suspend, cs35l32_runtime_resume,
  468. NULL)
  469. };
  470. static const struct of_device_id cs35l32_of_match[] = {
  471. { .compatible = "cirrus,cs35l32", },
  472. {},
  473. };
  474. MODULE_DEVICE_TABLE(of, cs35l32_of_match);
  475. static const struct i2c_device_id cs35l32_id[] = {
  476. {"cs35l32", 0},
  477. {}
  478. };
  479. MODULE_DEVICE_TABLE(i2c, cs35l32_id);
  480. static struct i2c_driver cs35l32_i2c_driver = {
  481. .driver = {
  482. .name = "cs35l32",
  483. .pm = &cs35l32_runtime_pm,
  484. .of_match_table = cs35l32_of_match,
  485. },
  486. .id_table = cs35l32_id,
  487. .probe = cs35l32_i2c_probe,
  488. .remove = cs35l32_i2c_remove,
  489. };
  490. module_i2c_driver(cs35l32_i2c_driver);
  491. MODULE_DESCRIPTION("ASoC CS35L32 driver");
  492. MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
  493. MODULE_LICENSE("GPL");