amdgpu_ctx.c 4.1 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: monk liu <monk.liu@amd.com>
  23. */
  24. #include <drm/drmP.h>
  25. #include "amdgpu.h"
  26. static void amdgpu_ctx_do_release(struct kref *ref)
  27. {
  28. struct amdgpu_ctx *ctx;
  29. struct amdgpu_ctx_mgr *mgr;
  30. ctx = container_of(ref, struct amdgpu_ctx, refcount);
  31. mgr = &ctx->fpriv->ctx_mgr;
  32. mutex_lock(&mgr->hlock);
  33. idr_remove(&mgr->ctx_handles, ctx->id);
  34. mutex_unlock(&mgr->hlock);
  35. kfree(ctx);
  36. }
  37. int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags)
  38. {
  39. int r;
  40. struct amdgpu_ctx *ctx;
  41. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  42. ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
  43. if (!ctx)
  44. return -ENOMEM;
  45. mutex_lock(&mgr->hlock);
  46. r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL);
  47. if (r < 0) {
  48. mutex_unlock(&mgr->hlock);
  49. kfree(ctx);
  50. return r;
  51. }
  52. mutex_unlock(&mgr->hlock);
  53. *id = (uint32_t)r;
  54. memset(ctx, 0, sizeof(*ctx));
  55. ctx->id = *id;
  56. ctx->fpriv = fpriv;
  57. kref_init(&ctx->refcount);
  58. return 0;
  59. }
  60. int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
  61. {
  62. int r;
  63. struct amdgpu_ctx *ctx;
  64. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  65. rcu_read_lock();
  66. ctx = idr_find(&mgr->ctx_handles, id);
  67. rcu_read_unlock();
  68. if (ctx) {
  69. /* if no task is pending on this context, free it */
  70. r = kref_put(&ctx->refcount, amdgpu_ctx_do_release);
  71. if (r == 1)
  72. return 0;//context is removed successfully
  73. else {
  74. /* context is still in using */
  75. kref_get(&ctx->refcount);
  76. return -ERESTARTSYS;
  77. }
  78. }
  79. return -EINVAL;
  80. }
  81. int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id, struct amdgpu_ctx_state *state)
  82. {
  83. struct amdgpu_ctx *ctx;
  84. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  85. rcu_read_lock();
  86. ctx = idr_find(&mgr->ctx_handles, id);
  87. rcu_read_unlock();
  88. if (ctx) {
  89. /* state should alter with CS activity */
  90. *state = ctx->state;
  91. return 0;
  92. }
  93. return -EINVAL;
  94. }
  95. void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
  96. {
  97. struct idr *idp;
  98. struct amdgpu_ctx *ctx;
  99. uint32_t id;
  100. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  101. idp = &mgr->ctx_handles;
  102. idr_for_each_entry(idp,ctx,id) {
  103. if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
  104. DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id);
  105. }
  106. mutex_destroy(&mgr->hlock);
  107. }
  108. int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
  109. struct drm_file *filp)
  110. {
  111. int r;
  112. uint32_t id;
  113. uint32_t flags;
  114. struct amdgpu_ctx_state state;
  115. union drm_amdgpu_ctx *args = data;
  116. struct amdgpu_device *adev = dev->dev_private;
  117. struct amdgpu_fpriv *fpriv = filp->driver_priv;
  118. r = 0;
  119. id = args->in.ctx_id;
  120. flags = args->in.flags;
  121. switch (args->in.op) {
  122. case AMDGPU_CTX_OP_ALLOC_CTX:
  123. r = amdgpu_ctx_alloc(adev, fpriv, &id, flags);
  124. args->out.alloc.ctx_id = id;
  125. break;
  126. case AMDGPU_CTX_OP_FREE_CTX:
  127. r = amdgpu_ctx_free(adev, fpriv, id);
  128. break;
  129. case AMDGPU_CTX_OP_QUERY_STATE:
  130. r = amdgpu_ctx_query(adev, fpriv, id, &state);
  131. if (r == 0) {
  132. args->out.state.flags = state.flags;
  133. args->out.state.hangs = state.hangs;
  134. }
  135. break;
  136. default:
  137. return -EINVAL;
  138. }
  139. return r;
  140. }