imx6qdl-gw53xx.dtsi 12 KB

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  1. /*
  2. * Copyright 2013 Gateworks Corporation
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. / {
  12. /* these are used by bootloader for disabling nodes */
  13. aliases {
  14. can0 = &can1;
  15. ethernet0 = &fec;
  16. ethernet1 = &eth1;
  17. led0 = &led0;
  18. led1 = &led1;
  19. led2 = &led2;
  20. nand = &gpmi;
  21. sky2 = &eth1;
  22. ssi0 = &ssi1;
  23. usb0 = &usbh1;
  24. usb1 = &usbotg;
  25. usdhc2 = &usdhc3;
  26. };
  27. chosen {
  28. bootargs = "console=ttymxc1,115200";
  29. };
  30. backlight {
  31. compatible = "pwm-backlight";
  32. pwms = <&pwm4 0 5000000>;
  33. brightness-levels = <0 4 8 16 32 64 128 255>;
  34. default-brightness-level = <7>;
  35. };
  36. leds {
  37. compatible = "gpio-leds";
  38. led0: user1 {
  39. label = "user1";
  40. gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
  41. default-state = "on";
  42. linux,default-trigger = "heartbeat";
  43. };
  44. led1: user2 {
  45. label = "user2";
  46. gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
  47. default-state = "off";
  48. };
  49. led2: user3 {
  50. label = "user3";
  51. gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
  52. default-state = "off";
  53. };
  54. };
  55. memory {
  56. reg = <0x10000000 0x40000000>;
  57. };
  58. pps {
  59. compatible = "pps-gpio";
  60. gpios = <&gpio1 26 0>;
  61. status = "okay";
  62. };
  63. regulators {
  64. compatible = "simple-bus";
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. reg_1p0v: regulator@0 {
  68. compatible = "regulator-fixed";
  69. reg = <0>;
  70. regulator-name = "1P0V";
  71. regulator-min-microvolt = <1000000>;
  72. regulator-max-microvolt = <1000000>;
  73. regulator-always-on;
  74. };
  75. /* remove when pmic 1p8 regulator available */
  76. reg_1p8v: regulator@1 {
  77. compatible = "regulator-fixed";
  78. reg = <1>;
  79. regulator-name = "1P8V";
  80. regulator-min-microvolt = <1800000>;
  81. regulator-max-microvolt = <1800000>;
  82. regulator-always-on;
  83. };
  84. reg_3p3v: regulator@2 {
  85. compatible = "regulator-fixed";
  86. reg = <2>;
  87. regulator-name = "3P3V";
  88. regulator-min-microvolt = <3300000>;
  89. regulator-max-microvolt = <3300000>;
  90. regulator-always-on;
  91. };
  92. reg_usb_h1_vbus: regulator@3 {
  93. compatible = "regulator-fixed";
  94. reg = <3>;
  95. regulator-name = "usb_h1_vbus";
  96. regulator-min-microvolt = <5000000>;
  97. regulator-max-microvolt = <5000000>;
  98. regulator-always-on;
  99. };
  100. reg_usb_otg_vbus: regulator@4 {
  101. compatible = "regulator-fixed";
  102. reg = <4>;
  103. regulator-name = "usb_otg_vbus";
  104. regulator-min-microvolt = <5000000>;
  105. regulator-max-microvolt = <5000000>;
  106. gpio = <&gpio3 22 0>;
  107. enable-active-high;
  108. };
  109. };
  110. sound {
  111. compatible = "fsl,imx6q-sabrelite-sgtl5000",
  112. "fsl,imx-audio-sgtl5000";
  113. model = "imx6q-sabrelite-sgtl5000";
  114. ssi-controller = <&ssi1>;
  115. audio-codec = <&codec>;
  116. audio-routing =
  117. "MIC_IN", "Mic Jack",
  118. "Mic Jack", "Mic Bias",
  119. "Headphone Jack", "HP_OUT";
  120. mux-int-port = <1>;
  121. mux-ext-port = <4>;
  122. };
  123. };
  124. &audmux {
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&pinctrl_audmux>;
  127. status = "okay";
  128. };
  129. &can1 {
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_flexcan1>;
  132. status = "okay";
  133. };
  134. &fec {
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&pinctrl_enet>;
  137. phy-mode = "rgmii";
  138. phy-reset-gpios = <&gpio1 30 0>;
  139. status = "okay";
  140. };
  141. &gpmi {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_gpmi_nand>;
  144. status = "okay";
  145. };
  146. &hdmi {
  147. ddc-i2c-bus = <&i2c3>;
  148. status = "okay";
  149. };
  150. &i2c1 {
  151. clock-frequency = <100000>;
  152. pinctrl-names = "default";
  153. pinctrl-0 = <&pinctrl_i2c1>;
  154. status = "okay";
  155. eeprom1: eeprom@50 {
  156. compatible = "atmel,24c02";
  157. reg = <0x50>;
  158. pagesize = <16>;
  159. };
  160. eeprom2: eeprom@51 {
  161. compatible = "atmel,24c02";
  162. reg = <0x51>;
  163. pagesize = <16>;
  164. };
  165. eeprom3: eeprom@52 {
  166. compatible = "atmel,24c02";
  167. reg = <0x52>;
  168. pagesize = <16>;
  169. };
  170. eeprom4: eeprom@53 {
  171. compatible = "atmel,24c02";
  172. reg = <0x53>;
  173. pagesize = <16>;
  174. };
  175. gpio: pca9555@23 {
  176. compatible = "nxp,pca9555";
  177. reg = <0x23>;
  178. gpio-controller;
  179. #gpio-cells = <2>;
  180. };
  181. hwmon: gsc@29 {
  182. compatible = "gw,gsp";
  183. reg = <0x29>;
  184. };
  185. rtc: ds1672@68 {
  186. compatible = "dallas,ds1672";
  187. reg = <0x68>;
  188. };
  189. };
  190. &i2c2 {
  191. clock-frequency = <100000>;
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&pinctrl_i2c2>;
  194. status = "okay";
  195. pciclkgen: si53156@6b {
  196. compatible = "sil,si53156";
  197. reg = <0x6b>;
  198. };
  199. pciswitch: pex8606@3f {
  200. compatible = "plx,pex8606";
  201. reg = <0x3f>;
  202. };
  203. pmic: ltc3676@3c {
  204. compatible = "lltc,ltc3676";
  205. reg = <0x3c>;
  206. regulators {
  207. /* VDD_SOC */
  208. sw1_reg: ltc3676__sw1 {
  209. regulator-min-microvolt = <1175000>;
  210. regulator-max-microvolt = <1175000>;
  211. regulator-boot-on;
  212. regulator-always-on;
  213. };
  214. /* VDD_1P8 */
  215. sw2_reg: ltc3676__sw2 {
  216. regulator-min-microvolt = <1800000>;
  217. regulator-max-microvolt = <1800000>;
  218. regulator-boot-on;
  219. regulator-always-on;
  220. };
  221. /* VDD_ARM */
  222. sw3_reg: ltc3676__sw3 {
  223. regulator-min-microvolt = <1175000>;
  224. regulator-max-microvolt = <1175000>;
  225. regulator-boot-on;
  226. regulator-always-on;
  227. };
  228. /* VDD_DDR */
  229. sw4_reg: ltc3676__sw4 {
  230. regulator-min-microvolt = <1500000>;
  231. regulator-max-microvolt = <1500000>;
  232. regulator-boot-on;
  233. regulator-always-on;
  234. };
  235. /* VDD_2P5 */
  236. ldo2_reg: ltc3676__ldo2 {
  237. regulator-min-microvolt = <2500000>;
  238. regulator-max-microvolt = <2500000>;
  239. regulator-boot-on;
  240. regulator-always-on;
  241. };
  242. /* VDD_1P8 */
  243. ldo3_reg: ltc3676__ldo3 {
  244. regulator-min-microvolt = <1800000>;
  245. regulator-max-microvolt = <1800000>;
  246. regulator-boot-on;
  247. regulator-always-on;
  248. };
  249. /* VDD_HIGH */
  250. ldo4_reg: ltc3676__ldo4 {
  251. regulator-min-microvolt = <3000000>;
  252. regulator-max-microvolt = <3000000>;
  253. };
  254. };
  255. };
  256. };
  257. &i2c3 {
  258. clock-frequency = <100000>;
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&pinctrl_i2c3>;
  261. status = "okay";
  262. accelerometer: fxos8700@1e {
  263. compatible = "fsl,fxos8700";
  264. reg = <0x1e>;
  265. };
  266. codec: sgtl5000@0a {
  267. compatible = "fsl,sgtl5000";
  268. reg = <0x0a>;
  269. clocks = <&clks 201>;
  270. VDDA-supply = <&reg_1p8v>;
  271. VDDIO-supply = <&reg_3p3v>;
  272. };
  273. hdmiin: adv7611@4c {
  274. compatible = "adi,adv7611";
  275. reg = <0x4c>;
  276. };
  277. touchscreen: egalax_ts@04 {
  278. compatible = "eeti,egalax_ts";
  279. reg = <0x04>;
  280. interrupt-parent = <&gpio1>;
  281. interrupts = <11 2>; /* gpio1_11 active low */
  282. wakeup-gpios = <&gpio1 11 0>;
  283. };
  284. videoout: adv7393@2a {
  285. compatible = "adi,adv7393";
  286. reg = <0x2a>;
  287. };
  288. videoin: adv7180@20 {
  289. compatible = "adi,adv7180";
  290. reg = <0x20>;
  291. };
  292. };
  293. &iomuxc {
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_hog>;
  296. imx6qdl-gw53xx {
  297. pinctrl_hog: hoggrp {
  298. fsl,pins = <
  299. MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */
  300. MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */
  301. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
  302. MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */
  303. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
  304. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
  305. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
  306. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
  307. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
  308. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */
  309. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */
  310. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */
  311. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */
  312. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
  313. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
  314. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
  315. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
  316. MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
  317. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
  318. >;
  319. };
  320. pinctrl_audmux: audmuxgrp {
  321. fsl,pins = <
  322. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  323. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  324. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  325. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  326. >;
  327. };
  328. pinctrl_enet: enetgrp {
  329. fsl,pins = <
  330. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  331. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  332. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  333. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  334. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  335. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  336. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  337. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  338. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  339. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  340. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  341. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  342. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  343. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  344. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  345. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  346. >;
  347. };
  348. pinctrl_flexcan1: flexcan1grp {
  349. fsl,pins = <
  350. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
  351. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
  352. >;
  353. };
  354. pinctrl_gpmi_nand: gpminandgrp {
  355. fsl,pins = <
  356. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  357. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  358. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  359. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  360. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  361. MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  362. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  363. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  364. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  365. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  366. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  367. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  368. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  369. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  370. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  371. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  372. >;
  373. };
  374. pinctrl_i2c1: i2c1grp {
  375. fsl,pins = <
  376. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  377. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  378. >;
  379. };
  380. pinctrl_i2c2: i2c2grp {
  381. fsl,pins = <
  382. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  383. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  384. >;
  385. };
  386. pinctrl_i2c3: i2c3grp {
  387. fsl,pins = <
  388. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  389. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  390. >;
  391. };
  392. pinctrl_pwm4: pwm4grp {
  393. fsl,pins = <
  394. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  395. >;
  396. };
  397. pinctrl_uart1: uart1grp {
  398. fsl,pins = <
  399. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  400. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  401. >;
  402. };
  403. pinctrl_uart2: uart2grp {
  404. fsl,pins = <
  405. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  406. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  407. >;
  408. };
  409. pinctrl_uart5: uart5grp {
  410. fsl,pins = <
  411. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  412. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  413. >;
  414. };
  415. pinctrl_usbotg: usbotggrp {
  416. fsl,pins = <
  417. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  418. >;
  419. };
  420. pinctrl_usdhc3: usdhc3grp {
  421. fsl,pins = <
  422. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  423. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  424. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  425. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  426. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  427. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  428. >;
  429. };
  430. };
  431. };
  432. &ldb {
  433. status = "okay";
  434. lvds-channel@1 {
  435. fsl,data-mapping = "spwg";
  436. fsl,data-width = <18>;
  437. status = "okay";
  438. display-timings {
  439. native-mode = <&timing0>;
  440. timing0: hsd100pxn1 {
  441. clock-frequency = <65000000>;
  442. hactive = <1024>;
  443. vactive = <768>;
  444. hback-porch = <220>;
  445. hfront-porch = <40>;
  446. vback-porch = <21>;
  447. vfront-porch = <7>;
  448. hsync-len = <60>;
  449. vsync-len = <10>;
  450. };
  451. };
  452. };
  453. };
  454. &pcie {
  455. reset-gpio = <&gpio1 29 0>;
  456. status = "okay";
  457. eth1: sky2@8 { /* MAC/PHY on bus 8 */
  458. compatible = "marvell,sky2";
  459. };
  460. };
  461. &pwm4 {
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_pwm4>;
  464. status = "okay";
  465. };
  466. &ssi1 {
  467. fsl,mode = "i2s-slave";
  468. status = "okay";
  469. };
  470. &uart1 {
  471. pinctrl-names = "default";
  472. pinctrl-0 = <&pinctrl_uart1>;
  473. status = "okay";
  474. };
  475. &uart2 {
  476. pinctrl-names = "default";
  477. pinctrl-0 = <&pinctrl_uart2>;
  478. status = "okay";
  479. };
  480. &uart5 {
  481. pinctrl-names = "default";
  482. pinctrl-0 = <&pinctrl_uart5>;
  483. status = "okay";
  484. };
  485. &usbotg {
  486. vbus-supply = <&reg_usb_otg_vbus>;
  487. pinctrl-names = "default";
  488. pinctrl-0 = <&pinctrl_usbotg>;
  489. disable-over-current;
  490. status = "okay";
  491. };
  492. &usbh1 {
  493. vbus-supply = <&reg_usb_h1_vbus>;
  494. status = "okay";
  495. };
  496. &usdhc3 {
  497. pinctrl-names = "default";
  498. pinctrl-0 = <&pinctrl_usdhc3>;
  499. cd-gpios = <&gpio7 0 0>;
  500. vmmc-supply = <&reg_3p3v>;
  501. status = "okay";
  502. };