rtc-s3c.c 16 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <mach/hardware.h>
  29. #include <asm/uaccess.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <plat/regs-rtc.h>
  33. enum s3c_cpu_type {
  34. TYPE_S3C2410,
  35. TYPE_S3C64XX,
  36. };
  37. /* I have yet to find an S3C implementation with more than one
  38. * of these rtc blocks in */
  39. static struct resource *s3c_rtc_mem;
  40. static struct clk *rtc_clk;
  41. static void __iomem *s3c_rtc_base;
  42. static int s3c_rtc_alarmno = NO_IRQ;
  43. static int s3c_rtc_tickno = NO_IRQ;
  44. static bool wake_en;
  45. static enum s3c_cpu_type s3c_rtc_cpu_type;
  46. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  47. static void s3c_rtc_alarm_clk_enable(bool enable)
  48. {
  49. static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
  50. static bool alarm_clk_enabled;
  51. unsigned long irq_flags;
  52. spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
  53. if (enable) {
  54. if (!alarm_clk_enabled) {
  55. clk_enable(rtc_clk);
  56. alarm_clk_enabled = true;
  57. }
  58. } else {
  59. if (alarm_clk_enabled) {
  60. clk_disable(rtc_clk);
  61. alarm_clk_enabled = false;
  62. }
  63. }
  64. spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
  65. }
  66. /* IRQ Handlers */
  67. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  68. {
  69. struct rtc_device *rdev = id;
  70. clk_enable(rtc_clk);
  71. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  72. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  73. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  74. clk_disable(rtc_clk);
  75. s3c_rtc_alarm_clk_enable(false);
  76. return IRQ_HANDLED;
  77. }
  78. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  79. {
  80. struct rtc_device *rdev = id;
  81. clk_enable(rtc_clk);
  82. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  83. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  84. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  85. clk_disable(rtc_clk);
  86. return IRQ_HANDLED;
  87. }
  88. /* Update control registers */
  89. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  90. {
  91. unsigned int tmp;
  92. pr_debug("%s: aie=%d\n", __func__, enabled);
  93. clk_enable(rtc_clk);
  94. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  95. if (enabled)
  96. tmp |= S3C2410_RTCALM_ALMEN;
  97. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  98. clk_disable(rtc_clk);
  99. s3c_rtc_alarm_clk_enable(enabled);
  100. return 0;
  101. }
  102. static int s3c_rtc_setfreq(struct device *dev, int freq)
  103. {
  104. struct platform_device *pdev = to_platform_device(dev);
  105. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  106. unsigned int tmp = 0;
  107. if (!is_power_of_2(freq))
  108. return -EINVAL;
  109. clk_enable(rtc_clk);
  110. spin_lock_irq(&s3c_rtc_pie_lock);
  111. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  112. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  113. tmp &= S3C2410_TICNT_ENABLE;
  114. }
  115. tmp |= (rtc_dev->max_user_freq / freq)-1;
  116. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  117. spin_unlock_irq(&s3c_rtc_pie_lock);
  118. clk_disable(rtc_clk);
  119. return 0;
  120. }
  121. /* Time read/write */
  122. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  123. {
  124. unsigned int have_retried = 0;
  125. void __iomem *base = s3c_rtc_base;
  126. clk_enable(rtc_clk);
  127. retry_get_time:
  128. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  129. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  130. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  131. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  132. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  133. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  134. /* the only way to work out wether the system was mid-update
  135. * when we read it is to check the second counter, and if it
  136. * is zero, then we re-try the entire read
  137. */
  138. if (rtc_tm->tm_sec == 0 && !have_retried) {
  139. have_retried = 1;
  140. goto retry_get_time;
  141. }
  142. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  143. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  144. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  145. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  146. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  147. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  148. rtc_tm->tm_year += 100;
  149. pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n",
  150. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  151. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  152. rtc_tm->tm_mon -= 1;
  153. clk_disable(rtc_clk);
  154. return rtc_valid_tm(rtc_tm);
  155. }
  156. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  157. {
  158. void __iomem *base = s3c_rtc_base;
  159. int year = tm->tm_year - 100;
  160. pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n",
  161. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  162. tm->tm_hour, tm->tm_min, tm->tm_sec);
  163. /* we get around y2k by simply not supporting it */
  164. if (year < 0 || year >= 100) {
  165. dev_err(dev, "rtc only supports 100 years\n");
  166. return -EINVAL;
  167. }
  168. clk_enable(rtc_clk);
  169. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  170. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  171. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  172. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  173. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  174. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  175. clk_disable(rtc_clk);
  176. return 0;
  177. }
  178. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  179. {
  180. struct rtc_time *alm_tm = &alrm->time;
  181. void __iomem *base = s3c_rtc_base;
  182. unsigned int alm_en;
  183. clk_enable(rtc_clk);
  184. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  185. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  186. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  187. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  188. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  189. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  190. alm_en = readb(base + S3C2410_RTCALM);
  191. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  192. pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  193. alm_en,
  194. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  195. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  196. /* decode the alarm enable field */
  197. if (alm_en & S3C2410_RTCALM_SECEN)
  198. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  199. else
  200. alm_tm->tm_sec = -1;
  201. if (alm_en & S3C2410_RTCALM_MINEN)
  202. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  203. else
  204. alm_tm->tm_min = -1;
  205. if (alm_en & S3C2410_RTCALM_HOUREN)
  206. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  207. else
  208. alm_tm->tm_hour = -1;
  209. if (alm_en & S3C2410_RTCALM_DAYEN)
  210. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  211. else
  212. alm_tm->tm_mday = -1;
  213. if (alm_en & S3C2410_RTCALM_MONEN) {
  214. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  215. alm_tm->tm_mon -= 1;
  216. } else {
  217. alm_tm->tm_mon = -1;
  218. }
  219. if (alm_en & S3C2410_RTCALM_YEAREN)
  220. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  221. else
  222. alm_tm->tm_year = -1;
  223. clk_disable(rtc_clk);
  224. return 0;
  225. }
  226. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  227. {
  228. struct rtc_time *tm = &alrm->time;
  229. void __iomem *base = s3c_rtc_base;
  230. unsigned int alrm_en;
  231. clk_enable(rtc_clk);
  232. pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  233. alrm->enabled,
  234. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  235. tm->tm_hour, tm->tm_min, tm->tm_sec);
  236. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  237. writeb(0x00, base + S3C2410_RTCALM);
  238. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  239. alrm_en |= S3C2410_RTCALM_SECEN;
  240. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  241. }
  242. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  243. alrm_en |= S3C2410_RTCALM_MINEN;
  244. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  245. }
  246. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  247. alrm_en |= S3C2410_RTCALM_HOUREN;
  248. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  249. }
  250. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  251. writeb(alrm_en, base + S3C2410_RTCALM);
  252. s3c_rtc_setaie(dev, alrm->enabled);
  253. clk_disable(rtc_clk);
  254. return 0;
  255. }
  256. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  257. {
  258. unsigned int ticnt;
  259. clk_enable(rtc_clk);
  260. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  261. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  262. ticnt &= S3C64XX_RTCCON_TICEN;
  263. } else {
  264. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  265. ticnt &= S3C2410_TICNT_ENABLE;
  266. }
  267. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  268. clk_disable(rtc_clk);
  269. return 0;
  270. }
  271. static const struct rtc_class_ops s3c_rtcops = {
  272. .read_time = s3c_rtc_gettime,
  273. .set_time = s3c_rtc_settime,
  274. .read_alarm = s3c_rtc_getalarm,
  275. .set_alarm = s3c_rtc_setalarm,
  276. .proc = s3c_rtc_proc,
  277. .alarm_irq_enable = s3c_rtc_setaie,
  278. };
  279. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  280. {
  281. void __iomem *base = s3c_rtc_base;
  282. unsigned int tmp;
  283. if (s3c_rtc_base == NULL)
  284. return;
  285. clk_enable(rtc_clk);
  286. if (!en) {
  287. tmp = readw(base + S3C2410_RTCCON);
  288. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  289. tmp &= ~S3C64XX_RTCCON_TICEN;
  290. tmp &= ~S3C2410_RTCCON_RTCEN;
  291. writew(tmp, base + S3C2410_RTCCON);
  292. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  293. tmp = readb(base + S3C2410_TICNT);
  294. tmp &= ~S3C2410_TICNT_ENABLE;
  295. writeb(tmp, base + S3C2410_TICNT);
  296. }
  297. } else {
  298. /* re-enable the device, and check it is ok */
  299. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  300. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  301. tmp = readw(base + S3C2410_RTCCON);
  302. writew(tmp | S3C2410_RTCCON_RTCEN,
  303. base + S3C2410_RTCCON);
  304. }
  305. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  306. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  307. tmp = readw(base + S3C2410_RTCCON);
  308. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  309. base + S3C2410_RTCCON);
  310. }
  311. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  312. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  313. tmp = readw(base + S3C2410_RTCCON);
  314. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  315. base + S3C2410_RTCCON);
  316. }
  317. }
  318. clk_disable(rtc_clk);
  319. }
  320. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  321. {
  322. struct rtc_device *rtc = platform_get_drvdata(dev);
  323. free_irq(s3c_rtc_alarmno, rtc);
  324. free_irq(s3c_rtc_tickno, rtc);
  325. platform_set_drvdata(dev, NULL);
  326. rtc_device_unregister(rtc);
  327. s3c_rtc_setaie(&dev->dev, 0);
  328. clk_put(rtc_clk);
  329. rtc_clk = NULL;
  330. iounmap(s3c_rtc_base);
  331. release_resource(s3c_rtc_mem);
  332. kfree(s3c_rtc_mem);
  333. return 0;
  334. }
  335. static const struct of_device_id s3c_rtc_dt_match[];
  336. static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
  337. {
  338. #ifdef CONFIG_OF
  339. if (pdev->dev.of_node) {
  340. const struct of_device_id *match;
  341. match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
  342. return match->data;
  343. }
  344. #endif
  345. return platform_get_device_id(pdev)->driver_data;
  346. }
  347. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  348. {
  349. struct rtc_device *rtc;
  350. struct rtc_time rtc_tm;
  351. struct resource *res;
  352. int ret;
  353. pr_debug("%s: probe=%p\n", __func__, pdev);
  354. /* find the IRQs */
  355. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  356. if (s3c_rtc_tickno < 0) {
  357. dev_err(&pdev->dev, "no irq for rtc tick\n");
  358. return -ENOENT;
  359. }
  360. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  361. if (s3c_rtc_alarmno < 0) {
  362. dev_err(&pdev->dev, "no irq for alarm\n");
  363. return -ENOENT;
  364. }
  365. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  366. s3c_rtc_tickno, s3c_rtc_alarmno);
  367. /* get the memory region */
  368. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  369. if (res == NULL) {
  370. dev_err(&pdev->dev, "failed to get memory region resource\n");
  371. return -ENOENT;
  372. }
  373. s3c_rtc_mem = request_mem_region(res->start, resource_size(res),
  374. pdev->name);
  375. if (s3c_rtc_mem == NULL) {
  376. dev_err(&pdev->dev, "failed to reserve memory region\n");
  377. ret = -ENOENT;
  378. goto err_nores;
  379. }
  380. s3c_rtc_base = ioremap(res->start, resource_size(res));
  381. if (s3c_rtc_base == NULL) {
  382. dev_err(&pdev->dev, "failed ioremap()\n");
  383. ret = -EINVAL;
  384. goto err_nomap;
  385. }
  386. rtc_clk = clk_get(&pdev->dev, "rtc");
  387. if (IS_ERR(rtc_clk)) {
  388. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  389. ret = PTR_ERR(rtc_clk);
  390. rtc_clk = NULL;
  391. goto err_clk;
  392. }
  393. clk_enable(rtc_clk);
  394. /* check to see if everything is setup correctly */
  395. s3c_rtc_enable(pdev, 1);
  396. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  397. readw(s3c_rtc_base + S3C2410_RTCCON));
  398. device_init_wakeup(&pdev->dev, 1);
  399. /* register RTC and exit */
  400. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  401. THIS_MODULE);
  402. if (IS_ERR(rtc)) {
  403. dev_err(&pdev->dev, "cannot attach rtc\n");
  404. ret = PTR_ERR(rtc);
  405. goto err_nortc;
  406. }
  407. s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
  408. /* Check RTC Time */
  409. s3c_rtc_gettime(NULL, &rtc_tm);
  410. if (rtc_valid_tm(&rtc_tm)) {
  411. rtc_tm.tm_year = 100;
  412. rtc_tm.tm_mon = 0;
  413. rtc_tm.tm_mday = 1;
  414. rtc_tm.tm_hour = 0;
  415. rtc_tm.tm_min = 0;
  416. rtc_tm.tm_sec = 0;
  417. s3c_rtc_settime(NULL, &rtc_tm);
  418. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  419. }
  420. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  421. rtc->max_user_freq = 32768;
  422. else
  423. rtc->max_user_freq = 128;
  424. platform_set_drvdata(pdev, rtc);
  425. s3c_rtc_setfreq(&pdev->dev, 1);
  426. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  427. IRQF_DISABLED, "s3c2410-rtc alarm", rtc);
  428. if (ret) {
  429. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  430. goto err_alarm_irq;
  431. }
  432. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  433. IRQF_DISABLED, "s3c2410-rtc tick", rtc);
  434. if (ret) {
  435. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  436. free_irq(s3c_rtc_alarmno, rtc);
  437. goto err_tick_irq;
  438. }
  439. clk_disable(rtc_clk);
  440. return 0;
  441. err_tick_irq:
  442. free_irq(s3c_rtc_alarmno, rtc);
  443. err_alarm_irq:
  444. platform_set_drvdata(pdev, NULL);
  445. rtc_device_unregister(rtc);
  446. err_nortc:
  447. s3c_rtc_enable(pdev, 0);
  448. clk_disable(rtc_clk);
  449. clk_put(rtc_clk);
  450. err_clk:
  451. iounmap(s3c_rtc_base);
  452. err_nomap:
  453. release_resource(s3c_rtc_mem);
  454. err_nores:
  455. return ret;
  456. }
  457. #ifdef CONFIG_PM
  458. /* RTC Power management control */
  459. static int ticnt_save, ticnt_en_save;
  460. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  461. {
  462. clk_enable(rtc_clk);
  463. /* save TICNT for anyone using periodic interrupts */
  464. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  465. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  466. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  467. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  468. }
  469. s3c_rtc_enable(pdev, 0);
  470. if (device_may_wakeup(&pdev->dev) && !wake_en) {
  471. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  472. wake_en = true;
  473. else
  474. dev_err(&pdev->dev, "enable_irq_wake failed\n");
  475. }
  476. clk_disable(rtc_clk);
  477. return 0;
  478. }
  479. static int s3c_rtc_resume(struct platform_device *pdev)
  480. {
  481. unsigned int tmp;
  482. clk_enable(rtc_clk);
  483. s3c_rtc_enable(pdev, 1);
  484. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  485. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  486. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  487. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  488. }
  489. if (device_may_wakeup(&pdev->dev) && wake_en) {
  490. disable_irq_wake(s3c_rtc_alarmno);
  491. wake_en = false;
  492. }
  493. clk_disable(rtc_clk);
  494. return 0;
  495. }
  496. #else
  497. #define s3c_rtc_suspend NULL
  498. #define s3c_rtc_resume NULL
  499. #endif
  500. #ifdef CONFIG_OF
  501. static const struct of_device_id s3c_rtc_dt_match[] = {
  502. {
  503. .compatible = "samsung,s3c2410-rtc"
  504. .data = TYPE_S3C2410,
  505. }, {
  506. .compatible = "samsung,s3c6410-rtc"
  507. .data = TYPE_S3C64XX,
  508. },
  509. {},
  510. };
  511. MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
  512. #else
  513. #define s3c_rtc_dt_match NULL
  514. #endif
  515. static struct platform_device_id s3c_rtc_driver_ids[] = {
  516. {
  517. .name = "s3c2410-rtc",
  518. .driver_data = TYPE_S3C2410,
  519. }, {
  520. .name = "s3c64xx-rtc",
  521. .driver_data = TYPE_S3C64XX,
  522. },
  523. { }
  524. };
  525. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  526. static struct platform_driver s3c_rtc_driver = {
  527. .probe = s3c_rtc_probe,
  528. .remove = __devexit_p(s3c_rtc_remove),
  529. .suspend = s3c_rtc_suspend,
  530. .resume = s3c_rtc_resume,
  531. .id_table = s3c_rtc_driver_ids,
  532. .driver = {
  533. .name = "s3c-rtc",
  534. .owner = THIS_MODULE,
  535. .of_match_table = s3c_rtc_dt_match,
  536. },
  537. };
  538. module_platform_driver(s3c_rtc_driver);
  539. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  540. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  541. MODULE_LICENSE("GPL");
  542. MODULE_ALIAS("platform:s3c2410-rtc");