r8152.c 94 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Version Information */
  28. #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
  29. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  30. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  31. #define MODULENAME "r8152"
  32. #define R8152_PHY_ID 32
  33. #define PLA_IDR 0xc000
  34. #define PLA_RCR 0xc010
  35. #define PLA_RMS 0xc016
  36. #define PLA_RXFIFO_CTRL0 0xc0a0
  37. #define PLA_RXFIFO_CTRL1 0xc0a4
  38. #define PLA_RXFIFO_CTRL2 0xc0a8
  39. #define PLA_DMY_REG0 0xc0b0
  40. #define PLA_FMC 0xc0b4
  41. #define PLA_CFG_WOL 0xc0b6
  42. #define PLA_TEREDO_CFG 0xc0bc
  43. #define PLA_MAR 0xcd00
  44. #define PLA_BACKUP 0xd000
  45. #define PAL_BDC_CR 0xd1a0
  46. #define PLA_TEREDO_TIMER 0xd2cc
  47. #define PLA_REALWOW_TIMER 0xd2e8
  48. #define PLA_LEDSEL 0xdd90
  49. #define PLA_LED_FEATURE 0xdd92
  50. #define PLA_PHYAR 0xde00
  51. #define PLA_BOOT_CTRL 0xe004
  52. #define PLA_GPHY_INTR_IMR 0xe022
  53. #define PLA_EEE_CR 0xe040
  54. #define PLA_EEEP_CR 0xe080
  55. #define PLA_MAC_PWR_CTRL 0xe0c0
  56. #define PLA_MAC_PWR_CTRL2 0xe0ca
  57. #define PLA_MAC_PWR_CTRL3 0xe0cc
  58. #define PLA_MAC_PWR_CTRL4 0xe0ce
  59. #define PLA_WDT6_CTRL 0xe428
  60. #define PLA_TCR0 0xe610
  61. #define PLA_TCR1 0xe612
  62. #define PLA_MTPS 0xe615
  63. #define PLA_TXFIFO_CTRL 0xe618
  64. #define PLA_RSTTALLY 0xe800
  65. #define PLA_CR 0xe813
  66. #define PLA_CRWECR 0xe81c
  67. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  68. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  69. #define PLA_CONFIG5 0xe822
  70. #define PLA_PHY_PWR 0xe84c
  71. #define PLA_OOB_CTRL 0xe84f
  72. #define PLA_CPCR 0xe854
  73. #define PLA_MISC_0 0xe858
  74. #define PLA_MISC_1 0xe85a
  75. #define PLA_OCP_GPHY_BASE 0xe86c
  76. #define PLA_TALLYCNT 0xe890
  77. #define PLA_SFF_STS_7 0xe8de
  78. #define PLA_PHYSTATUS 0xe908
  79. #define PLA_BP_BA 0xfc26
  80. #define PLA_BP_0 0xfc28
  81. #define PLA_BP_1 0xfc2a
  82. #define PLA_BP_2 0xfc2c
  83. #define PLA_BP_3 0xfc2e
  84. #define PLA_BP_4 0xfc30
  85. #define PLA_BP_5 0xfc32
  86. #define PLA_BP_6 0xfc34
  87. #define PLA_BP_7 0xfc36
  88. #define PLA_BP_EN 0xfc38
  89. #define USB_USB2PHY 0xb41e
  90. #define USB_SSPHYLINK2 0xb428
  91. #define USB_U2P3_CTRL 0xb460
  92. #define USB_CSR_DUMMY1 0xb464
  93. #define USB_CSR_DUMMY2 0xb466
  94. #define USB_DEV_STAT 0xb808
  95. #define USB_CONNECT_TIMER 0xcbf8
  96. #define USB_BURST_SIZE 0xcfc0
  97. #define USB_USB_CTRL 0xd406
  98. #define USB_PHY_CTRL 0xd408
  99. #define USB_TX_AGG 0xd40a
  100. #define USB_RX_BUF_TH 0xd40c
  101. #define USB_USB_TIMER 0xd428
  102. #define USB_RX_EARLY_TIMEOUT 0xd42c
  103. #define USB_RX_EARLY_SIZE 0xd42e
  104. #define USB_PM_CTRL_STATUS 0xd432
  105. #define USB_TX_DMA 0xd434
  106. #define USB_TOLERANCE 0xd490
  107. #define USB_LPM_CTRL 0xd41a
  108. #define USB_UPS_CTRL 0xd800
  109. #define USB_MISC_0 0xd81a
  110. #define USB_POWER_CUT 0xd80a
  111. #define USB_AFE_CTRL2 0xd824
  112. #define USB_WDT11_CTRL 0xe43c
  113. #define USB_BP_BA 0xfc26
  114. #define USB_BP_0 0xfc28
  115. #define USB_BP_1 0xfc2a
  116. #define USB_BP_2 0xfc2c
  117. #define USB_BP_3 0xfc2e
  118. #define USB_BP_4 0xfc30
  119. #define USB_BP_5 0xfc32
  120. #define USB_BP_6 0xfc34
  121. #define USB_BP_7 0xfc36
  122. #define USB_BP_EN 0xfc38
  123. /* OCP Registers */
  124. #define OCP_ALDPS_CONFIG 0x2010
  125. #define OCP_EEE_CONFIG1 0x2080
  126. #define OCP_EEE_CONFIG2 0x2092
  127. #define OCP_EEE_CONFIG3 0x2094
  128. #define OCP_BASE_MII 0xa400
  129. #define OCP_EEE_AR 0xa41a
  130. #define OCP_EEE_DATA 0xa41c
  131. #define OCP_PHY_STATUS 0xa420
  132. #define OCP_POWER_CFG 0xa430
  133. #define OCP_EEE_CFG 0xa432
  134. #define OCP_SRAM_ADDR 0xa436
  135. #define OCP_SRAM_DATA 0xa438
  136. #define OCP_DOWN_SPEED 0xa442
  137. #define OCP_EEE_ABLE 0xa5c4
  138. #define OCP_EEE_ADV 0xa5d0
  139. #define OCP_EEE_LPABLE 0xa5d2
  140. #define OCP_ADC_CFG 0xbc06
  141. /* SRAM Register */
  142. #define SRAM_LPF_CFG 0x8012
  143. #define SRAM_10M_AMP1 0x8080
  144. #define SRAM_10M_AMP2 0x8082
  145. #define SRAM_IMPEDANCE 0x8084
  146. /* PLA_RCR */
  147. #define RCR_AAP 0x00000001
  148. #define RCR_APM 0x00000002
  149. #define RCR_AM 0x00000004
  150. #define RCR_AB 0x00000008
  151. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  152. /* PLA_RXFIFO_CTRL0 */
  153. #define RXFIFO_THR1_NORMAL 0x00080002
  154. #define RXFIFO_THR1_OOB 0x01800003
  155. /* PLA_RXFIFO_CTRL1 */
  156. #define RXFIFO_THR2_FULL 0x00000060
  157. #define RXFIFO_THR2_HIGH 0x00000038
  158. #define RXFIFO_THR2_OOB 0x0000004a
  159. #define RXFIFO_THR2_NORMAL 0x00a0
  160. /* PLA_RXFIFO_CTRL2 */
  161. #define RXFIFO_THR3_FULL 0x00000078
  162. #define RXFIFO_THR3_HIGH 0x00000048
  163. #define RXFIFO_THR3_OOB 0x0000005a
  164. #define RXFIFO_THR3_NORMAL 0x0110
  165. /* PLA_TXFIFO_CTRL */
  166. #define TXFIFO_THR_NORMAL 0x00400008
  167. #define TXFIFO_THR_NORMAL2 0x01000008
  168. /* PLA_DMY_REG0 */
  169. #define ECM_ALDPS 0x0002
  170. /* PLA_FMC */
  171. #define FMC_FCR_MCU_EN 0x0001
  172. /* PLA_EEEP_CR */
  173. #define EEEP_CR_EEEP_TX 0x0002
  174. /* PLA_WDT6_CTRL */
  175. #define WDT6_SET_MODE 0x0010
  176. /* PLA_TCR0 */
  177. #define TCR0_TX_EMPTY 0x0800
  178. #define TCR0_AUTO_FIFO 0x0080
  179. /* PLA_TCR1 */
  180. #define VERSION_MASK 0x7cf0
  181. /* PLA_MTPS */
  182. #define MTPS_JUMBO (12 * 1024 / 64)
  183. #define MTPS_DEFAULT (6 * 1024 / 64)
  184. /* PLA_RSTTALLY */
  185. #define TALLY_RESET 0x0001
  186. /* PLA_CR */
  187. #define CR_RST 0x10
  188. #define CR_RE 0x08
  189. #define CR_TE 0x04
  190. /* PLA_CRWECR */
  191. #define CRWECR_NORAML 0x00
  192. #define CRWECR_CONFIG 0xc0
  193. /* PLA_OOB_CTRL */
  194. #define NOW_IS_OOB 0x80
  195. #define TXFIFO_EMPTY 0x20
  196. #define RXFIFO_EMPTY 0x10
  197. #define LINK_LIST_READY 0x02
  198. #define DIS_MCU_CLROOB 0x01
  199. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  200. /* PLA_MISC_1 */
  201. #define RXDY_GATED_EN 0x0008
  202. /* PLA_SFF_STS_7 */
  203. #define RE_INIT_LL 0x8000
  204. #define MCU_BORW_EN 0x4000
  205. /* PLA_CPCR */
  206. #define CPCR_RX_VLAN 0x0040
  207. /* PLA_CFG_WOL */
  208. #define MAGIC_EN 0x0001
  209. /* PLA_TEREDO_CFG */
  210. #define TEREDO_SEL 0x8000
  211. #define TEREDO_WAKE_MASK 0x7f00
  212. #define TEREDO_RS_EVENT_MASK 0x00fe
  213. #define OOB_TEREDO_EN 0x0001
  214. /* PAL_BDC_CR */
  215. #define ALDPS_PROXY_MODE 0x0001
  216. /* PLA_CONFIG34 */
  217. #define LINK_ON_WAKE_EN 0x0010
  218. #define LINK_OFF_WAKE_EN 0x0008
  219. /* PLA_CONFIG5 */
  220. #define BWF_EN 0x0040
  221. #define MWF_EN 0x0020
  222. #define UWF_EN 0x0010
  223. #define LAN_WAKE_EN 0x0002
  224. /* PLA_LED_FEATURE */
  225. #define LED_MODE_MASK 0x0700
  226. /* PLA_PHY_PWR */
  227. #define TX_10M_IDLE_EN 0x0080
  228. #define PFM_PWM_SWITCH 0x0040
  229. /* PLA_MAC_PWR_CTRL */
  230. #define D3_CLK_GATED_EN 0x00004000
  231. #define MCU_CLK_RATIO 0x07010f07
  232. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  233. #define ALDPS_SPDWN_RATIO 0x0f87
  234. /* PLA_MAC_PWR_CTRL2 */
  235. #define EEE_SPDWN_RATIO 0x8007
  236. /* PLA_MAC_PWR_CTRL3 */
  237. #define PKT_AVAIL_SPDWN_EN 0x0100
  238. #define SUSPEND_SPDWN_EN 0x0004
  239. #define U1U2_SPDWN_EN 0x0002
  240. #define L1_SPDWN_EN 0x0001
  241. /* PLA_MAC_PWR_CTRL4 */
  242. #define PWRSAVE_SPDWN_EN 0x1000
  243. #define RXDV_SPDWN_EN 0x0800
  244. #define TX10MIDLE_EN 0x0100
  245. #define TP100_SPDWN_EN 0x0020
  246. #define TP500_SPDWN_EN 0x0010
  247. #define TP1000_SPDWN_EN 0x0008
  248. #define EEE_SPDWN_EN 0x0001
  249. /* PLA_GPHY_INTR_IMR */
  250. #define GPHY_STS_MSK 0x0001
  251. #define SPEED_DOWN_MSK 0x0002
  252. #define SPDWN_RXDV_MSK 0x0004
  253. #define SPDWN_LINKCHG_MSK 0x0008
  254. /* PLA_PHYAR */
  255. #define PHYAR_FLAG 0x80000000
  256. /* PLA_EEE_CR */
  257. #define EEE_RX_EN 0x0001
  258. #define EEE_TX_EN 0x0002
  259. /* PLA_BOOT_CTRL */
  260. #define AUTOLOAD_DONE 0x0002
  261. /* USB_USB2PHY */
  262. #define USB2PHY_SUSPEND 0x0001
  263. #define USB2PHY_L1 0x0002
  264. /* USB_SSPHYLINK2 */
  265. #define pwd_dn_scale_mask 0x3ffe
  266. #define pwd_dn_scale(x) ((x) << 1)
  267. /* USB_CSR_DUMMY1 */
  268. #define DYNAMIC_BURST 0x0001
  269. /* USB_CSR_DUMMY2 */
  270. #define EP4_FULL_FC 0x0001
  271. /* USB_DEV_STAT */
  272. #define STAT_SPEED_MASK 0x0006
  273. #define STAT_SPEED_HIGH 0x0000
  274. #define STAT_SPEED_FULL 0x0002
  275. /* USB_TX_AGG */
  276. #define TX_AGG_MAX_THRESHOLD 0x03
  277. /* USB_RX_BUF_TH */
  278. #define RX_THR_SUPPER 0x0c350180
  279. #define RX_THR_HIGH 0x7a120180
  280. #define RX_THR_SLOW 0xffff0180
  281. /* USB_TX_DMA */
  282. #define TEST_MODE_DISABLE 0x00000001
  283. #define TX_SIZE_ADJUST1 0x00000100
  284. /* USB_UPS_CTRL */
  285. #define POWER_CUT 0x0100
  286. /* USB_PM_CTRL_STATUS */
  287. #define RESUME_INDICATE 0x0001
  288. /* USB_USB_CTRL */
  289. #define RX_AGG_DISABLE 0x0010
  290. /* USB_U2P3_CTRL */
  291. #define U2P3_ENABLE 0x0001
  292. /* USB_POWER_CUT */
  293. #define PWR_EN 0x0001
  294. #define PHASE2_EN 0x0008
  295. /* USB_MISC_0 */
  296. #define PCUT_STATUS 0x0001
  297. /* USB_RX_EARLY_TIMEOUT */
  298. #define COALESCE_SUPER 85000U
  299. #define COALESCE_HIGH 250000U
  300. #define COALESCE_SLOW 524280U
  301. /* USB_WDT11_CTRL */
  302. #define TIMER11_EN 0x0001
  303. /* USB_LPM_CTRL */
  304. /* bit 4 ~ 5: fifo empty boundary */
  305. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  306. /* bit 2 ~ 3: LMP timer */
  307. #define LPM_TIMER_MASK 0x0c
  308. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  309. #define LPM_TIMER_500US 0x0c /* 500 us */
  310. #define ROK_EXIT_LPM 0x02
  311. /* USB_AFE_CTRL2 */
  312. #define SEN_VAL_MASK 0xf800
  313. #define SEN_VAL_NORMAL 0xa000
  314. #define SEL_RXIDLE 0x0100
  315. /* OCP_ALDPS_CONFIG */
  316. #define ENPWRSAVE 0x8000
  317. #define ENPDNPS 0x0200
  318. #define LINKENA 0x0100
  319. #define DIS_SDSAVE 0x0010
  320. /* OCP_PHY_STATUS */
  321. #define PHY_STAT_MASK 0x0007
  322. #define PHY_STAT_LAN_ON 3
  323. #define PHY_STAT_PWRDN 5
  324. /* OCP_POWER_CFG */
  325. #define EEE_CLKDIV_EN 0x8000
  326. #define EN_ALDPS 0x0004
  327. #define EN_10M_PLLOFF 0x0001
  328. /* OCP_EEE_CONFIG1 */
  329. #define RG_TXLPI_MSK_HFDUP 0x8000
  330. #define RG_MATCLR_EN 0x4000
  331. #define EEE_10_CAP 0x2000
  332. #define EEE_NWAY_EN 0x1000
  333. #define TX_QUIET_EN 0x0200
  334. #define RX_QUIET_EN 0x0100
  335. #define sd_rise_time_mask 0x0070
  336. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  337. #define RG_RXLPI_MSK_HFDUP 0x0008
  338. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  339. /* OCP_EEE_CONFIG2 */
  340. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  341. #define RG_DACQUIET_EN 0x0400
  342. #define RG_LDVQUIET_EN 0x0200
  343. #define RG_CKRSEL 0x0020
  344. #define RG_EEEPRG_EN 0x0010
  345. /* OCP_EEE_CONFIG3 */
  346. #define fast_snr_mask 0xff80
  347. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  348. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  349. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  350. /* OCP_EEE_AR */
  351. /* bit[15:14] function */
  352. #define FUN_ADDR 0x0000
  353. #define FUN_DATA 0x4000
  354. /* bit[4:0] device addr */
  355. /* OCP_EEE_CFG */
  356. #define CTAP_SHORT_EN 0x0040
  357. #define EEE10_EN 0x0010
  358. /* OCP_DOWN_SPEED */
  359. #define EN_10M_BGOFF 0x0080
  360. /* OCP_ADC_CFG */
  361. #define CKADSEL_L 0x0100
  362. #define ADC_EN 0x0080
  363. #define EN_EMI_L 0x0040
  364. /* SRAM_LPF_CFG */
  365. #define LPF_AUTO_TUNE 0x8000
  366. /* SRAM_10M_AMP1 */
  367. #define GDAC_IB_UPALL 0x0008
  368. /* SRAM_10M_AMP2 */
  369. #define AMP_DN 0x0200
  370. /* SRAM_IMPEDANCE */
  371. #define RX_DRIVING_MASK 0x6000
  372. enum rtl_register_content {
  373. _1000bps = 0x10,
  374. _100bps = 0x08,
  375. _10bps = 0x04,
  376. LINK_STATUS = 0x02,
  377. FULL_DUP = 0x01,
  378. };
  379. #define RTL8152_MAX_TX 4
  380. #define RTL8152_MAX_RX 10
  381. #define INTBUFSIZE 2
  382. #define CRC_SIZE 4
  383. #define TX_ALIGN 4
  384. #define RX_ALIGN 8
  385. #define INTR_LINK 0x0004
  386. #define RTL8152_REQT_READ 0xc0
  387. #define RTL8152_REQT_WRITE 0x40
  388. #define RTL8152_REQ_GET_REGS 0x05
  389. #define RTL8152_REQ_SET_REGS 0x05
  390. #define BYTE_EN_DWORD 0xff
  391. #define BYTE_EN_WORD 0x33
  392. #define BYTE_EN_BYTE 0x11
  393. #define BYTE_EN_SIX_BYTES 0x3f
  394. #define BYTE_EN_START_MASK 0x0f
  395. #define BYTE_EN_END_MASK 0xf0
  396. #define RTL8153_MAX_PACKET 9216 /* 9K */
  397. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  398. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  399. #define RTL8153_RMS RTL8153_MAX_PACKET
  400. #define RTL8152_TX_TIMEOUT (5 * HZ)
  401. #define RTL8152_NAPI_WEIGHT 64
  402. /* rtl8152 flags */
  403. enum rtl8152_flags {
  404. RTL8152_UNPLUG = 0,
  405. RTL8152_SET_RX_MODE,
  406. WORK_ENABLE,
  407. RTL8152_LINK_CHG,
  408. SELECTIVE_SUSPEND,
  409. PHY_RESET,
  410. SCHEDULE_NAPI,
  411. };
  412. /* Define these values to match your device */
  413. #define VENDOR_ID_REALTEK 0x0bda
  414. #define VENDOR_ID_SAMSUNG 0x04e8
  415. #define VENDOR_ID_LENOVO 0x17ef
  416. #define VENDOR_ID_NVIDIA 0x0955
  417. #define MCU_TYPE_PLA 0x0100
  418. #define MCU_TYPE_USB 0x0000
  419. struct tally_counter {
  420. __le64 tx_packets;
  421. __le64 rx_packets;
  422. __le64 tx_errors;
  423. __le32 rx_errors;
  424. __le16 rx_missed;
  425. __le16 align_errors;
  426. __le32 tx_one_collision;
  427. __le32 tx_multi_collision;
  428. __le64 rx_unicast;
  429. __le64 rx_broadcast;
  430. __le32 rx_multicast;
  431. __le16 tx_aborted;
  432. __le16 tx_underrun;
  433. };
  434. struct rx_desc {
  435. __le32 opts1;
  436. #define RX_LEN_MASK 0x7fff
  437. __le32 opts2;
  438. #define RD_UDP_CS BIT(23)
  439. #define RD_TCP_CS BIT(22)
  440. #define RD_IPV6_CS BIT(20)
  441. #define RD_IPV4_CS BIT(19)
  442. __le32 opts3;
  443. #define IPF BIT(23) /* IP checksum fail */
  444. #define UDPF BIT(22) /* UDP checksum fail */
  445. #define TCPF BIT(21) /* TCP checksum fail */
  446. #define RX_VLAN_TAG BIT(16)
  447. __le32 opts4;
  448. __le32 opts5;
  449. __le32 opts6;
  450. };
  451. struct tx_desc {
  452. __le32 opts1;
  453. #define TX_FS BIT(31) /* First segment of a packet */
  454. #define TX_LS BIT(30) /* Final segment of a packet */
  455. #define GTSENDV4 BIT(28)
  456. #define GTSENDV6 BIT(27)
  457. #define GTTCPHO_SHIFT 18
  458. #define GTTCPHO_MAX 0x7fU
  459. #define TX_LEN_MAX 0x3ffffU
  460. __le32 opts2;
  461. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  462. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  463. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  464. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  465. #define MSS_SHIFT 17
  466. #define MSS_MAX 0x7ffU
  467. #define TCPHO_SHIFT 17
  468. #define TCPHO_MAX 0x7ffU
  469. #define TX_VLAN_TAG BIT(16)
  470. };
  471. struct r8152;
  472. struct rx_agg {
  473. struct list_head list;
  474. struct urb *urb;
  475. struct r8152 *context;
  476. void *buffer;
  477. void *head;
  478. };
  479. struct tx_agg {
  480. struct list_head list;
  481. struct urb *urb;
  482. struct r8152 *context;
  483. void *buffer;
  484. void *head;
  485. u32 skb_num;
  486. u32 skb_len;
  487. };
  488. struct r8152 {
  489. unsigned long flags;
  490. struct usb_device *udev;
  491. struct napi_struct napi;
  492. struct usb_interface *intf;
  493. struct net_device *netdev;
  494. struct urb *intr_urb;
  495. struct tx_agg tx_info[RTL8152_MAX_TX];
  496. struct rx_agg rx_info[RTL8152_MAX_RX];
  497. struct list_head rx_done, tx_free;
  498. struct sk_buff_head tx_queue, rx_queue;
  499. spinlock_t rx_lock, tx_lock;
  500. struct delayed_work schedule;
  501. struct mii_if_info mii;
  502. struct mutex control; /* use for hw setting */
  503. struct rtl_ops {
  504. void (*init)(struct r8152 *);
  505. int (*enable)(struct r8152 *);
  506. void (*disable)(struct r8152 *);
  507. void (*up)(struct r8152 *);
  508. void (*down)(struct r8152 *);
  509. void (*unload)(struct r8152 *);
  510. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  511. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  512. } rtl_ops;
  513. int intr_interval;
  514. u32 saved_wolopts;
  515. u32 msg_enable;
  516. u32 tx_qlen;
  517. u32 coalesce;
  518. u16 ocp_base;
  519. u8 *intr_buff;
  520. u8 version;
  521. };
  522. enum rtl_version {
  523. RTL_VER_UNKNOWN = 0,
  524. RTL_VER_01,
  525. RTL_VER_02,
  526. RTL_VER_03,
  527. RTL_VER_04,
  528. RTL_VER_05,
  529. RTL_VER_MAX
  530. };
  531. enum tx_csum_stat {
  532. TX_CSUM_SUCCESS = 0,
  533. TX_CSUM_TSO,
  534. TX_CSUM_NONE
  535. };
  536. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  537. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  538. */
  539. static const int multicast_filter_limit = 32;
  540. static unsigned int agg_buf_sz = 16384;
  541. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  542. VLAN_ETH_HLEN - VLAN_HLEN)
  543. static
  544. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  545. {
  546. int ret;
  547. void *tmp;
  548. tmp = kmalloc(size, GFP_KERNEL);
  549. if (!tmp)
  550. return -ENOMEM;
  551. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  552. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  553. value, index, tmp, size, 500);
  554. memcpy(data, tmp, size);
  555. kfree(tmp);
  556. return ret;
  557. }
  558. static
  559. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  560. {
  561. int ret;
  562. void *tmp;
  563. tmp = kmemdup(data, size, GFP_KERNEL);
  564. if (!tmp)
  565. return -ENOMEM;
  566. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  567. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  568. value, index, tmp, size, 500);
  569. kfree(tmp);
  570. return ret;
  571. }
  572. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  573. void *data, u16 type)
  574. {
  575. u16 limit = 64;
  576. int ret = 0;
  577. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  578. return -ENODEV;
  579. /* both size and indix must be 4 bytes align */
  580. if ((size & 3) || !size || (index & 3) || !data)
  581. return -EPERM;
  582. if ((u32)index + (u32)size > 0xffff)
  583. return -EPERM;
  584. while (size) {
  585. if (size > limit) {
  586. ret = get_registers(tp, index, type, limit, data);
  587. if (ret < 0)
  588. break;
  589. index += limit;
  590. data += limit;
  591. size -= limit;
  592. } else {
  593. ret = get_registers(tp, index, type, size, data);
  594. if (ret < 0)
  595. break;
  596. index += size;
  597. data += size;
  598. size = 0;
  599. break;
  600. }
  601. }
  602. if (ret == -ENODEV)
  603. set_bit(RTL8152_UNPLUG, &tp->flags);
  604. return ret;
  605. }
  606. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  607. u16 size, void *data, u16 type)
  608. {
  609. int ret;
  610. u16 byteen_start, byteen_end, byen;
  611. u16 limit = 512;
  612. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  613. return -ENODEV;
  614. /* both size and indix must be 4 bytes align */
  615. if ((size & 3) || !size || (index & 3) || !data)
  616. return -EPERM;
  617. if ((u32)index + (u32)size > 0xffff)
  618. return -EPERM;
  619. byteen_start = byteen & BYTE_EN_START_MASK;
  620. byteen_end = byteen & BYTE_EN_END_MASK;
  621. byen = byteen_start | (byteen_start << 4);
  622. ret = set_registers(tp, index, type | byen, 4, data);
  623. if (ret < 0)
  624. goto error1;
  625. index += 4;
  626. data += 4;
  627. size -= 4;
  628. if (size) {
  629. size -= 4;
  630. while (size) {
  631. if (size > limit) {
  632. ret = set_registers(tp, index,
  633. type | BYTE_EN_DWORD,
  634. limit, data);
  635. if (ret < 0)
  636. goto error1;
  637. index += limit;
  638. data += limit;
  639. size -= limit;
  640. } else {
  641. ret = set_registers(tp, index,
  642. type | BYTE_EN_DWORD,
  643. size, data);
  644. if (ret < 0)
  645. goto error1;
  646. index += size;
  647. data += size;
  648. size = 0;
  649. break;
  650. }
  651. }
  652. byen = byteen_end | (byteen_end >> 4);
  653. ret = set_registers(tp, index, type | byen, 4, data);
  654. if (ret < 0)
  655. goto error1;
  656. }
  657. error1:
  658. if (ret == -ENODEV)
  659. set_bit(RTL8152_UNPLUG, &tp->flags);
  660. return ret;
  661. }
  662. static inline
  663. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  664. {
  665. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  666. }
  667. static inline
  668. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  669. {
  670. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  671. }
  672. static inline
  673. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  674. {
  675. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  676. }
  677. static inline
  678. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  679. {
  680. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  681. }
  682. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  683. {
  684. __le32 data;
  685. generic_ocp_read(tp, index, sizeof(data), &data, type);
  686. return __le32_to_cpu(data);
  687. }
  688. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  689. {
  690. __le32 tmp = __cpu_to_le32(data);
  691. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  692. }
  693. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  694. {
  695. u32 data;
  696. __le32 tmp;
  697. u8 shift = index & 2;
  698. index &= ~3;
  699. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  700. data = __le32_to_cpu(tmp);
  701. data >>= (shift * 8);
  702. data &= 0xffff;
  703. return (u16)data;
  704. }
  705. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  706. {
  707. u32 mask = 0xffff;
  708. __le32 tmp;
  709. u16 byen = BYTE_EN_WORD;
  710. u8 shift = index & 2;
  711. data &= mask;
  712. if (index & 2) {
  713. byen <<= shift;
  714. mask <<= (shift * 8);
  715. data <<= (shift * 8);
  716. index &= ~3;
  717. }
  718. tmp = __cpu_to_le32(data);
  719. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  720. }
  721. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  722. {
  723. u32 data;
  724. __le32 tmp;
  725. u8 shift = index & 3;
  726. index &= ~3;
  727. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  728. data = __le32_to_cpu(tmp);
  729. data >>= (shift * 8);
  730. data &= 0xff;
  731. return (u8)data;
  732. }
  733. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  734. {
  735. u32 mask = 0xff;
  736. __le32 tmp;
  737. u16 byen = BYTE_EN_BYTE;
  738. u8 shift = index & 3;
  739. data &= mask;
  740. if (index & 3) {
  741. byen <<= shift;
  742. mask <<= (shift * 8);
  743. data <<= (shift * 8);
  744. index &= ~3;
  745. }
  746. tmp = __cpu_to_le32(data);
  747. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  748. }
  749. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  750. {
  751. u16 ocp_base, ocp_index;
  752. ocp_base = addr & 0xf000;
  753. if (ocp_base != tp->ocp_base) {
  754. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  755. tp->ocp_base = ocp_base;
  756. }
  757. ocp_index = (addr & 0x0fff) | 0xb000;
  758. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  759. }
  760. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  761. {
  762. u16 ocp_base, ocp_index;
  763. ocp_base = addr & 0xf000;
  764. if (ocp_base != tp->ocp_base) {
  765. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  766. tp->ocp_base = ocp_base;
  767. }
  768. ocp_index = (addr & 0x0fff) | 0xb000;
  769. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  770. }
  771. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  772. {
  773. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  774. }
  775. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  776. {
  777. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  778. }
  779. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  780. {
  781. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  782. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  783. }
  784. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  785. {
  786. struct r8152 *tp = netdev_priv(netdev);
  787. int ret;
  788. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  789. return -ENODEV;
  790. if (phy_id != R8152_PHY_ID)
  791. return -EINVAL;
  792. ret = r8152_mdio_read(tp, reg);
  793. return ret;
  794. }
  795. static
  796. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  797. {
  798. struct r8152 *tp = netdev_priv(netdev);
  799. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  800. return;
  801. if (phy_id != R8152_PHY_ID)
  802. return;
  803. r8152_mdio_write(tp, reg, val);
  804. }
  805. static int
  806. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  807. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  808. {
  809. struct r8152 *tp = netdev_priv(netdev);
  810. struct sockaddr *addr = p;
  811. int ret = -EADDRNOTAVAIL;
  812. if (!is_valid_ether_addr(addr->sa_data))
  813. goto out1;
  814. ret = usb_autopm_get_interface(tp->intf);
  815. if (ret < 0)
  816. goto out1;
  817. mutex_lock(&tp->control);
  818. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  819. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  820. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  821. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  822. mutex_unlock(&tp->control);
  823. usb_autopm_put_interface(tp->intf);
  824. out1:
  825. return ret;
  826. }
  827. static int set_ethernet_addr(struct r8152 *tp)
  828. {
  829. struct net_device *dev = tp->netdev;
  830. struct sockaddr sa;
  831. int ret;
  832. if (tp->version == RTL_VER_01)
  833. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  834. else
  835. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  836. if (ret < 0) {
  837. netif_err(tp, probe, dev, "Get ether addr fail\n");
  838. } else if (!is_valid_ether_addr(sa.sa_data)) {
  839. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  840. sa.sa_data);
  841. eth_hw_addr_random(dev);
  842. ether_addr_copy(sa.sa_data, dev->dev_addr);
  843. ret = rtl8152_set_mac_address(dev, &sa);
  844. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  845. sa.sa_data);
  846. } else {
  847. if (tp->version == RTL_VER_01)
  848. ether_addr_copy(dev->dev_addr, sa.sa_data);
  849. else
  850. ret = rtl8152_set_mac_address(dev, &sa);
  851. }
  852. return ret;
  853. }
  854. static void read_bulk_callback(struct urb *urb)
  855. {
  856. struct net_device *netdev;
  857. int status = urb->status;
  858. struct rx_agg *agg;
  859. struct r8152 *tp;
  860. agg = urb->context;
  861. if (!agg)
  862. return;
  863. tp = agg->context;
  864. if (!tp)
  865. return;
  866. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  867. return;
  868. if (!test_bit(WORK_ENABLE, &tp->flags))
  869. return;
  870. netdev = tp->netdev;
  871. /* When link down, the driver would cancel all bulks. */
  872. /* This avoid the re-submitting bulk */
  873. if (!netif_carrier_ok(netdev))
  874. return;
  875. usb_mark_last_busy(tp->udev);
  876. switch (status) {
  877. case 0:
  878. if (urb->actual_length < ETH_ZLEN)
  879. break;
  880. spin_lock(&tp->rx_lock);
  881. list_add_tail(&agg->list, &tp->rx_done);
  882. spin_unlock(&tp->rx_lock);
  883. napi_schedule(&tp->napi);
  884. return;
  885. case -ESHUTDOWN:
  886. set_bit(RTL8152_UNPLUG, &tp->flags);
  887. netif_device_detach(tp->netdev);
  888. return;
  889. case -ENOENT:
  890. return; /* the urb is in unlink state */
  891. case -ETIME:
  892. if (net_ratelimit())
  893. netdev_warn(netdev, "maybe reset is needed?\n");
  894. break;
  895. default:
  896. if (net_ratelimit())
  897. netdev_warn(netdev, "Rx status %d\n", status);
  898. break;
  899. }
  900. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  901. }
  902. static void write_bulk_callback(struct urb *urb)
  903. {
  904. struct net_device_stats *stats;
  905. struct net_device *netdev;
  906. struct tx_agg *agg;
  907. struct r8152 *tp;
  908. int status = urb->status;
  909. agg = urb->context;
  910. if (!agg)
  911. return;
  912. tp = agg->context;
  913. if (!tp)
  914. return;
  915. netdev = tp->netdev;
  916. stats = &netdev->stats;
  917. if (status) {
  918. if (net_ratelimit())
  919. netdev_warn(netdev, "Tx status %d\n", status);
  920. stats->tx_errors += agg->skb_num;
  921. } else {
  922. stats->tx_packets += agg->skb_num;
  923. stats->tx_bytes += agg->skb_len;
  924. }
  925. spin_lock(&tp->tx_lock);
  926. list_add_tail(&agg->list, &tp->tx_free);
  927. spin_unlock(&tp->tx_lock);
  928. usb_autopm_put_interface_async(tp->intf);
  929. if (!netif_carrier_ok(netdev))
  930. return;
  931. if (!test_bit(WORK_ENABLE, &tp->flags))
  932. return;
  933. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  934. return;
  935. if (!skb_queue_empty(&tp->tx_queue))
  936. napi_schedule(&tp->napi);
  937. }
  938. static void intr_callback(struct urb *urb)
  939. {
  940. struct r8152 *tp;
  941. __le16 *d;
  942. int status = urb->status;
  943. int res;
  944. tp = urb->context;
  945. if (!tp)
  946. return;
  947. if (!test_bit(WORK_ENABLE, &tp->flags))
  948. return;
  949. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  950. return;
  951. switch (status) {
  952. case 0: /* success */
  953. break;
  954. case -ECONNRESET: /* unlink */
  955. case -ESHUTDOWN:
  956. netif_device_detach(tp->netdev);
  957. case -ENOENT:
  958. case -EPROTO:
  959. netif_info(tp, intr, tp->netdev,
  960. "Stop submitting intr, status %d\n", status);
  961. return;
  962. case -EOVERFLOW:
  963. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  964. goto resubmit;
  965. /* -EPIPE: should clear the halt */
  966. default:
  967. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  968. goto resubmit;
  969. }
  970. d = urb->transfer_buffer;
  971. if (INTR_LINK & __le16_to_cpu(d[0])) {
  972. if (!netif_carrier_ok(tp->netdev)) {
  973. set_bit(RTL8152_LINK_CHG, &tp->flags);
  974. schedule_delayed_work(&tp->schedule, 0);
  975. }
  976. } else {
  977. if (netif_carrier_ok(tp->netdev)) {
  978. set_bit(RTL8152_LINK_CHG, &tp->flags);
  979. schedule_delayed_work(&tp->schedule, 0);
  980. }
  981. }
  982. resubmit:
  983. res = usb_submit_urb(urb, GFP_ATOMIC);
  984. if (res == -ENODEV) {
  985. set_bit(RTL8152_UNPLUG, &tp->flags);
  986. netif_device_detach(tp->netdev);
  987. } else if (res) {
  988. netif_err(tp, intr, tp->netdev,
  989. "can't resubmit intr, status %d\n", res);
  990. }
  991. }
  992. static inline void *rx_agg_align(void *data)
  993. {
  994. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  995. }
  996. static inline void *tx_agg_align(void *data)
  997. {
  998. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  999. }
  1000. static void free_all_mem(struct r8152 *tp)
  1001. {
  1002. int i;
  1003. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1004. usb_free_urb(tp->rx_info[i].urb);
  1005. tp->rx_info[i].urb = NULL;
  1006. kfree(tp->rx_info[i].buffer);
  1007. tp->rx_info[i].buffer = NULL;
  1008. tp->rx_info[i].head = NULL;
  1009. }
  1010. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1011. usb_free_urb(tp->tx_info[i].urb);
  1012. tp->tx_info[i].urb = NULL;
  1013. kfree(tp->tx_info[i].buffer);
  1014. tp->tx_info[i].buffer = NULL;
  1015. tp->tx_info[i].head = NULL;
  1016. }
  1017. usb_free_urb(tp->intr_urb);
  1018. tp->intr_urb = NULL;
  1019. kfree(tp->intr_buff);
  1020. tp->intr_buff = NULL;
  1021. }
  1022. static int alloc_all_mem(struct r8152 *tp)
  1023. {
  1024. struct net_device *netdev = tp->netdev;
  1025. struct usb_interface *intf = tp->intf;
  1026. struct usb_host_interface *alt = intf->cur_altsetting;
  1027. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1028. struct urb *urb;
  1029. int node, i;
  1030. u8 *buf;
  1031. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1032. spin_lock_init(&tp->rx_lock);
  1033. spin_lock_init(&tp->tx_lock);
  1034. INIT_LIST_HEAD(&tp->tx_free);
  1035. skb_queue_head_init(&tp->tx_queue);
  1036. skb_queue_head_init(&tp->rx_queue);
  1037. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1038. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1039. if (!buf)
  1040. goto err1;
  1041. if (buf != rx_agg_align(buf)) {
  1042. kfree(buf);
  1043. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1044. node);
  1045. if (!buf)
  1046. goto err1;
  1047. }
  1048. urb = usb_alloc_urb(0, GFP_KERNEL);
  1049. if (!urb) {
  1050. kfree(buf);
  1051. goto err1;
  1052. }
  1053. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1054. tp->rx_info[i].context = tp;
  1055. tp->rx_info[i].urb = urb;
  1056. tp->rx_info[i].buffer = buf;
  1057. tp->rx_info[i].head = rx_agg_align(buf);
  1058. }
  1059. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1060. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1061. if (!buf)
  1062. goto err1;
  1063. if (buf != tx_agg_align(buf)) {
  1064. kfree(buf);
  1065. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1066. node);
  1067. if (!buf)
  1068. goto err1;
  1069. }
  1070. urb = usb_alloc_urb(0, GFP_KERNEL);
  1071. if (!urb) {
  1072. kfree(buf);
  1073. goto err1;
  1074. }
  1075. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1076. tp->tx_info[i].context = tp;
  1077. tp->tx_info[i].urb = urb;
  1078. tp->tx_info[i].buffer = buf;
  1079. tp->tx_info[i].head = tx_agg_align(buf);
  1080. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1081. }
  1082. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1083. if (!tp->intr_urb)
  1084. goto err1;
  1085. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1086. if (!tp->intr_buff)
  1087. goto err1;
  1088. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1089. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1090. tp->intr_buff, INTBUFSIZE, intr_callback,
  1091. tp, tp->intr_interval);
  1092. return 0;
  1093. err1:
  1094. free_all_mem(tp);
  1095. return -ENOMEM;
  1096. }
  1097. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1098. {
  1099. struct tx_agg *agg = NULL;
  1100. unsigned long flags;
  1101. if (list_empty(&tp->tx_free))
  1102. return NULL;
  1103. spin_lock_irqsave(&tp->tx_lock, flags);
  1104. if (!list_empty(&tp->tx_free)) {
  1105. struct list_head *cursor;
  1106. cursor = tp->tx_free.next;
  1107. list_del_init(cursor);
  1108. agg = list_entry(cursor, struct tx_agg, list);
  1109. }
  1110. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1111. return agg;
  1112. }
  1113. /* r8152_csum_workaround()
  1114. * The hw limites the value the transport offset. When the offset is out of the
  1115. * range, calculate the checksum by sw.
  1116. */
  1117. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1118. struct sk_buff_head *list)
  1119. {
  1120. if (skb_shinfo(skb)->gso_size) {
  1121. netdev_features_t features = tp->netdev->features;
  1122. struct sk_buff_head seg_list;
  1123. struct sk_buff *segs, *nskb;
  1124. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1125. segs = skb_gso_segment(skb, features);
  1126. if (IS_ERR(segs) || !segs)
  1127. goto drop;
  1128. __skb_queue_head_init(&seg_list);
  1129. do {
  1130. nskb = segs;
  1131. segs = segs->next;
  1132. nskb->next = NULL;
  1133. __skb_queue_tail(&seg_list, nskb);
  1134. } while (segs);
  1135. skb_queue_splice(&seg_list, list);
  1136. dev_kfree_skb(skb);
  1137. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1138. if (skb_checksum_help(skb) < 0)
  1139. goto drop;
  1140. __skb_queue_head(list, skb);
  1141. } else {
  1142. struct net_device_stats *stats;
  1143. drop:
  1144. stats = &tp->netdev->stats;
  1145. stats->tx_dropped++;
  1146. dev_kfree_skb(skb);
  1147. }
  1148. }
  1149. /* msdn_giant_send_check()
  1150. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1151. * packet length for IPv6 TCP large packets.
  1152. */
  1153. static int msdn_giant_send_check(struct sk_buff *skb)
  1154. {
  1155. const struct ipv6hdr *ipv6h;
  1156. struct tcphdr *th;
  1157. int ret;
  1158. ret = skb_cow_head(skb, 0);
  1159. if (ret)
  1160. return ret;
  1161. ipv6h = ipv6_hdr(skb);
  1162. th = tcp_hdr(skb);
  1163. th->check = 0;
  1164. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1165. return ret;
  1166. }
  1167. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1168. {
  1169. if (skb_vlan_tag_present(skb)) {
  1170. u32 opts2;
  1171. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1172. desc->opts2 |= cpu_to_le32(opts2);
  1173. }
  1174. }
  1175. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1176. {
  1177. u32 opts2 = le32_to_cpu(desc->opts2);
  1178. if (opts2 & RX_VLAN_TAG)
  1179. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1180. swab16(opts2 & 0xffff));
  1181. }
  1182. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1183. struct sk_buff *skb, u32 len, u32 transport_offset)
  1184. {
  1185. u32 mss = skb_shinfo(skb)->gso_size;
  1186. u32 opts1, opts2 = 0;
  1187. int ret = TX_CSUM_SUCCESS;
  1188. WARN_ON_ONCE(len > TX_LEN_MAX);
  1189. opts1 = len | TX_FS | TX_LS;
  1190. if (mss) {
  1191. if (transport_offset > GTTCPHO_MAX) {
  1192. netif_warn(tp, tx_err, tp->netdev,
  1193. "Invalid transport offset 0x%x for TSO\n",
  1194. transport_offset);
  1195. ret = TX_CSUM_TSO;
  1196. goto unavailable;
  1197. }
  1198. switch (vlan_get_protocol(skb)) {
  1199. case htons(ETH_P_IP):
  1200. opts1 |= GTSENDV4;
  1201. break;
  1202. case htons(ETH_P_IPV6):
  1203. if (msdn_giant_send_check(skb)) {
  1204. ret = TX_CSUM_TSO;
  1205. goto unavailable;
  1206. }
  1207. opts1 |= GTSENDV6;
  1208. break;
  1209. default:
  1210. WARN_ON_ONCE(1);
  1211. break;
  1212. }
  1213. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1214. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1215. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1216. u8 ip_protocol;
  1217. if (transport_offset > TCPHO_MAX) {
  1218. netif_warn(tp, tx_err, tp->netdev,
  1219. "Invalid transport offset 0x%x\n",
  1220. transport_offset);
  1221. ret = TX_CSUM_NONE;
  1222. goto unavailable;
  1223. }
  1224. switch (vlan_get_protocol(skb)) {
  1225. case htons(ETH_P_IP):
  1226. opts2 |= IPV4_CS;
  1227. ip_protocol = ip_hdr(skb)->protocol;
  1228. break;
  1229. case htons(ETH_P_IPV6):
  1230. opts2 |= IPV6_CS;
  1231. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1232. break;
  1233. default:
  1234. ip_protocol = IPPROTO_RAW;
  1235. break;
  1236. }
  1237. if (ip_protocol == IPPROTO_TCP)
  1238. opts2 |= TCP_CS;
  1239. else if (ip_protocol == IPPROTO_UDP)
  1240. opts2 |= UDP_CS;
  1241. else
  1242. WARN_ON_ONCE(1);
  1243. opts2 |= transport_offset << TCPHO_SHIFT;
  1244. }
  1245. desc->opts2 = cpu_to_le32(opts2);
  1246. desc->opts1 = cpu_to_le32(opts1);
  1247. unavailable:
  1248. return ret;
  1249. }
  1250. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1251. {
  1252. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1253. int remain, ret;
  1254. u8 *tx_data;
  1255. __skb_queue_head_init(&skb_head);
  1256. spin_lock(&tx_queue->lock);
  1257. skb_queue_splice_init(tx_queue, &skb_head);
  1258. spin_unlock(&tx_queue->lock);
  1259. tx_data = agg->head;
  1260. agg->skb_num = 0;
  1261. agg->skb_len = 0;
  1262. remain = agg_buf_sz;
  1263. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1264. struct tx_desc *tx_desc;
  1265. struct sk_buff *skb;
  1266. unsigned int len;
  1267. u32 offset;
  1268. skb = __skb_dequeue(&skb_head);
  1269. if (!skb)
  1270. break;
  1271. len = skb->len + sizeof(*tx_desc);
  1272. if (len > remain) {
  1273. __skb_queue_head(&skb_head, skb);
  1274. break;
  1275. }
  1276. tx_data = tx_agg_align(tx_data);
  1277. tx_desc = (struct tx_desc *)tx_data;
  1278. offset = (u32)skb_transport_offset(skb);
  1279. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1280. r8152_csum_workaround(tp, skb, &skb_head);
  1281. continue;
  1282. }
  1283. rtl_tx_vlan_tag(tx_desc, skb);
  1284. tx_data += sizeof(*tx_desc);
  1285. len = skb->len;
  1286. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1287. struct net_device_stats *stats = &tp->netdev->stats;
  1288. stats->tx_dropped++;
  1289. dev_kfree_skb_any(skb);
  1290. tx_data -= sizeof(*tx_desc);
  1291. continue;
  1292. }
  1293. tx_data += len;
  1294. agg->skb_len += len;
  1295. agg->skb_num++;
  1296. dev_kfree_skb_any(skb);
  1297. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1298. }
  1299. if (!skb_queue_empty(&skb_head)) {
  1300. spin_lock(&tx_queue->lock);
  1301. skb_queue_splice(&skb_head, tx_queue);
  1302. spin_unlock(&tx_queue->lock);
  1303. }
  1304. netif_tx_lock(tp->netdev);
  1305. if (netif_queue_stopped(tp->netdev) &&
  1306. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1307. netif_wake_queue(tp->netdev);
  1308. netif_tx_unlock(tp->netdev);
  1309. ret = usb_autopm_get_interface_async(tp->intf);
  1310. if (ret < 0)
  1311. goto out_tx_fill;
  1312. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1313. agg->head, (int)(tx_data - (u8 *)agg->head),
  1314. (usb_complete_t)write_bulk_callback, agg);
  1315. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1316. if (ret < 0)
  1317. usb_autopm_put_interface_async(tp->intf);
  1318. out_tx_fill:
  1319. return ret;
  1320. }
  1321. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1322. {
  1323. u8 checksum = CHECKSUM_NONE;
  1324. u32 opts2, opts3;
  1325. if (tp->version == RTL_VER_01)
  1326. goto return_result;
  1327. opts2 = le32_to_cpu(rx_desc->opts2);
  1328. opts3 = le32_to_cpu(rx_desc->opts3);
  1329. if (opts2 & RD_IPV4_CS) {
  1330. if (opts3 & IPF)
  1331. checksum = CHECKSUM_NONE;
  1332. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1333. checksum = CHECKSUM_NONE;
  1334. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1335. checksum = CHECKSUM_NONE;
  1336. else
  1337. checksum = CHECKSUM_UNNECESSARY;
  1338. } else if (RD_IPV6_CS) {
  1339. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1340. checksum = CHECKSUM_UNNECESSARY;
  1341. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1342. checksum = CHECKSUM_UNNECESSARY;
  1343. }
  1344. return_result:
  1345. return checksum;
  1346. }
  1347. static int rx_bottom(struct r8152 *tp, int budget)
  1348. {
  1349. unsigned long flags;
  1350. struct list_head *cursor, *next, rx_queue;
  1351. int ret = 0, work_done = 0;
  1352. if (!skb_queue_empty(&tp->rx_queue)) {
  1353. while (work_done < budget) {
  1354. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1355. struct net_device *netdev = tp->netdev;
  1356. struct net_device_stats *stats = &netdev->stats;
  1357. unsigned int pkt_len;
  1358. if (!skb)
  1359. break;
  1360. pkt_len = skb->len;
  1361. napi_gro_receive(&tp->napi, skb);
  1362. work_done++;
  1363. stats->rx_packets++;
  1364. stats->rx_bytes += pkt_len;
  1365. }
  1366. }
  1367. if (list_empty(&tp->rx_done))
  1368. goto out1;
  1369. INIT_LIST_HEAD(&rx_queue);
  1370. spin_lock_irqsave(&tp->rx_lock, flags);
  1371. list_splice_init(&tp->rx_done, &rx_queue);
  1372. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1373. list_for_each_safe(cursor, next, &rx_queue) {
  1374. struct rx_desc *rx_desc;
  1375. struct rx_agg *agg;
  1376. int len_used = 0;
  1377. struct urb *urb;
  1378. u8 *rx_data;
  1379. list_del_init(cursor);
  1380. agg = list_entry(cursor, struct rx_agg, list);
  1381. urb = agg->urb;
  1382. if (urb->actual_length < ETH_ZLEN)
  1383. goto submit;
  1384. rx_desc = agg->head;
  1385. rx_data = agg->head;
  1386. len_used += sizeof(struct rx_desc);
  1387. while (urb->actual_length > len_used) {
  1388. struct net_device *netdev = tp->netdev;
  1389. struct net_device_stats *stats = &netdev->stats;
  1390. unsigned int pkt_len;
  1391. struct sk_buff *skb;
  1392. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1393. if (pkt_len < ETH_ZLEN)
  1394. break;
  1395. len_used += pkt_len;
  1396. if (urb->actual_length < len_used)
  1397. break;
  1398. pkt_len -= CRC_SIZE;
  1399. rx_data += sizeof(struct rx_desc);
  1400. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1401. if (!skb) {
  1402. stats->rx_dropped++;
  1403. goto find_next_rx;
  1404. }
  1405. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1406. memcpy(skb->data, rx_data, pkt_len);
  1407. skb_put(skb, pkt_len);
  1408. skb->protocol = eth_type_trans(skb, netdev);
  1409. rtl_rx_vlan_tag(rx_desc, skb);
  1410. if (work_done < budget) {
  1411. napi_gro_receive(&tp->napi, skb);
  1412. work_done++;
  1413. stats->rx_packets++;
  1414. stats->rx_bytes += pkt_len;
  1415. } else {
  1416. __skb_queue_tail(&tp->rx_queue, skb);
  1417. }
  1418. find_next_rx:
  1419. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1420. rx_desc = (struct rx_desc *)rx_data;
  1421. len_used = (int)(rx_data - (u8 *)agg->head);
  1422. len_used += sizeof(struct rx_desc);
  1423. }
  1424. submit:
  1425. if (!ret) {
  1426. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1427. } else {
  1428. urb->actual_length = 0;
  1429. list_add_tail(&agg->list, next);
  1430. }
  1431. }
  1432. if (!list_empty(&rx_queue)) {
  1433. spin_lock_irqsave(&tp->rx_lock, flags);
  1434. list_splice_tail(&rx_queue, &tp->rx_done);
  1435. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1436. }
  1437. out1:
  1438. return work_done;
  1439. }
  1440. static void tx_bottom(struct r8152 *tp)
  1441. {
  1442. int res;
  1443. do {
  1444. struct tx_agg *agg;
  1445. if (skb_queue_empty(&tp->tx_queue))
  1446. break;
  1447. agg = r8152_get_tx_agg(tp);
  1448. if (!agg)
  1449. break;
  1450. res = r8152_tx_agg_fill(tp, agg);
  1451. if (res) {
  1452. struct net_device *netdev = tp->netdev;
  1453. if (res == -ENODEV) {
  1454. set_bit(RTL8152_UNPLUG, &tp->flags);
  1455. netif_device_detach(netdev);
  1456. } else {
  1457. struct net_device_stats *stats = &netdev->stats;
  1458. unsigned long flags;
  1459. netif_warn(tp, tx_err, netdev,
  1460. "failed tx_urb %d\n", res);
  1461. stats->tx_dropped += agg->skb_num;
  1462. spin_lock_irqsave(&tp->tx_lock, flags);
  1463. list_add_tail(&agg->list, &tp->tx_free);
  1464. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1465. }
  1466. }
  1467. } while (res == 0);
  1468. }
  1469. static void bottom_half(struct r8152 *tp)
  1470. {
  1471. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1472. return;
  1473. if (!test_bit(WORK_ENABLE, &tp->flags))
  1474. return;
  1475. /* When link down, the driver would cancel all bulks. */
  1476. /* This avoid the re-submitting bulk */
  1477. if (!netif_carrier_ok(tp->netdev))
  1478. return;
  1479. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1480. tx_bottom(tp);
  1481. }
  1482. static int r8152_poll(struct napi_struct *napi, int budget)
  1483. {
  1484. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1485. int work_done;
  1486. work_done = rx_bottom(tp, budget);
  1487. bottom_half(tp);
  1488. if (work_done < budget) {
  1489. napi_complete(napi);
  1490. if (!list_empty(&tp->rx_done))
  1491. napi_schedule(napi);
  1492. }
  1493. return work_done;
  1494. }
  1495. static
  1496. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1497. {
  1498. int ret;
  1499. /* The rx would be stopped, so skip submitting */
  1500. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1501. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1502. return 0;
  1503. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1504. agg->head, agg_buf_sz,
  1505. (usb_complete_t)read_bulk_callback, agg);
  1506. ret = usb_submit_urb(agg->urb, mem_flags);
  1507. if (ret == -ENODEV) {
  1508. set_bit(RTL8152_UNPLUG, &tp->flags);
  1509. netif_device_detach(tp->netdev);
  1510. } else if (ret) {
  1511. struct urb *urb = agg->urb;
  1512. unsigned long flags;
  1513. urb->actual_length = 0;
  1514. spin_lock_irqsave(&tp->rx_lock, flags);
  1515. list_add_tail(&agg->list, &tp->rx_done);
  1516. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1517. netif_err(tp, rx_err, tp->netdev,
  1518. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1519. napi_schedule(&tp->napi);
  1520. }
  1521. return ret;
  1522. }
  1523. static void rtl_drop_queued_tx(struct r8152 *tp)
  1524. {
  1525. struct net_device_stats *stats = &tp->netdev->stats;
  1526. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1527. struct sk_buff *skb;
  1528. if (skb_queue_empty(tx_queue))
  1529. return;
  1530. __skb_queue_head_init(&skb_head);
  1531. spin_lock_bh(&tx_queue->lock);
  1532. skb_queue_splice_init(tx_queue, &skb_head);
  1533. spin_unlock_bh(&tx_queue->lock);
  1534. while ((skb = __skb_dequeue(&skb_head))) {
  1535. dev_kfree_skb(skb);
  1536. stats->tx_dropped++;
  1537. }
  1538. }
  1539. static void rtl8152_tx_timeout(struct net_device *netdev)
  1540. {
  1541. struct r8152 *tp = netdev_priv(netdev);
  1542. int i;
  1543. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1544. for (i = 0; i < RTL8152_MAX_TX; i++)
  1545. usb_unlink_urb(tp->tx_info[i].urb);
  1546. }
  1547. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1548. {
  1549. struct r8152 *tp = netdev_priv(netdev);
  1550. if (netif_carrier_ok(netdev)) {
  1551. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1552. schedule_delayed_work(&tp->schedule, 0);
  1553. }
  1554. }
  1555. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1556. {
  1557. struct r8152 *tp = netdev_priv(netdev);
  1558. u32 mc_filter[2]; /* Multicast hash filter */
  1559. __le32 tmp[2];
  1560. u32 ocp_data;
  1561. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1562. netif_stop_queue(netdev);
  1563. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1564. ocp_data &= ~RCR_ACPT_ALL;
  1565. ocp_data |= RCR_AB | RCR_APM;
  1566. if (netdev->flags & IFF_PROMISC) {
  1567. /* Unconditionally log net taps. */
  1568. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1569. ocp_data |= RCR_AM | RCR_AAP;
  1570. mc_filter[1] = 0xffffffff;
  1571. mc_filter[0] = 0xffffffff;
  1572. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1573. (netdev->flags & IFF_ALLMULTI)) {
  1574. /* Too many to filter perfectly -- accept all multicasts. */
  1575. ocp_data |= RCR_AM;
  1576. mc_filter[1] = 0xffffffff;
  1577. mc_filter[0] = 0xffffffff;
  1578. } else {
  1579. struct netdev_hw_addr *ha;
  1580. mc_filter[1] = 0;
  1581. mc_filter[0] = 0;
  1582. netdev_for_each_mc_addr(ha, netdev) {
  1583. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1584. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1585. ocp_data |= RCR_AM;
  1586. }
  1587. }
  1588. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1589. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1590. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1591. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1592. netif_wake_queue(netdev);
  1593. }
  1594. static netdev_features_t
  1595. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1596. netdev_features_t features)
  1597. {
  1598. u32 mss = skb_shinfo(skb)->gso_size;
  1599. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1600. int offset = skb_transport_offset(skb);
  1601. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1602. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1603. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1604. features &= ~NETIF_F_GSO_MASK;
  1605. return features;
  1606. }
  1607. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1608. struct net_device *netdev)
  1609. {
  1610. struct r8152 *tp = netdev_priv(netdev);
  1611. skb_tx_timestamp(skb);
  1612. skb_queue_tail(&tp->tx_queue, skb);
  1613. if (!list_empty(&tp->tx_free)) {
  1614. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1615. set_bit(SCHEDULE_NAPI, &tp->flags);
  1616. schedule_delayed_work(&tp->schedule, 0);
  1617. } else {
  1618. usb_mark_last_busy(tp->udev);
  1619. napi_schedule(&tp->napi);
  1620. }
  1621. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1622. netif_stop_queue(netdev);
  1623. }
  1624. return NETDEV_TX_OK;
  1625. }
  1626. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1627. {
  1628. u32 ocp_data;
  1629. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1630. ocp_data &= ~FMC_FCR_MCU_EN;
  1631. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1632. ocp_data |= FMC_FCR_MCU_EN;
  1633. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1634. }
  1635. static void rtl8152_nic_reset(struct r8152 *tp)
  1636. {
  1637. int i;
  1638. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1639. for (i = 0; i < 1000; i++) {
  1640. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1641. break;
  1642. usleep_range(100, 400);
  1643. }
  1644. }
  1645. static void set_tx_qlen(struct r8152 *tp)
  1646. {
  1647. struct net_device *netdev = tp->netdev;
  1648. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1649. sizeof(struct tx_desc));
  1650. }
  1651. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1652. {
  1653. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1654. }
  1655. static void rtl_set_eee_plus(struct r8152 *tp)
  1656. {
  1657. u32 ocp_data;
  1658. u8 speed;
  1659. speed = rtl8152_get_speed(tp);
  1660. if (speed & _10bps) {
  1661. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1662. ocp_data |= EEEP_CR_EEEP_TX;
  1663. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1664. } else {
  1665. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1666. ocp_data &= ~EEEP_CR_EEEP_TX;
  1667. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1668. }
  1669. }
  1670. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1671. {
  1672. u32 ocp_data;
  1673. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1674. if (enable)
  1675. ocp_data |= RXDY_GATED_EN;
  1676. else
  1677. ocp_data &= ~RXDY_GATED_EN;
  1678. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1679. }
  1680. static int rtl_start_rx(struct r8152 *tp)
  1681. {
  1682. int i, ret = 0;
  1683. napi_disable(&tp->napi);
  1684. INIT_LIST_HEAD(&tp->rx_done);
  1685. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1686. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1687. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1688. if (ret)
  1689. break;
  1690. }
  1691. napi_enable(&tp->napi);
  1692. if (ret && ++i < RTL8152_MAX_RX) {
  1693. struct list_head rx_queue;
  1694. unsigned long flags;
  1695. INIT_LIST_HEAD(&rx_queue);
  1696. do {
  1697. struct rx_agg *agg = &tp->rx_info[i++];
  1698. struct urb *urb = agg->urb;
  1699. urb->actual_length = 0;
  1700. list_add_tail(&agg->list, &rx_queue);
  1701. } while (i < RTL8152_MAX_RX);
  1702. spin_lock_irqsave(&tp->rx_lock, flags);
  1703. list_splice_tail(&rx_queue, &tp->rx_done);
  1704. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1705. }
  1706. return ret;
  1707. }
  1708. static int rtl_stop_rx(struct r8152 *tp)
  1709. {
  1710. int i;
  1711. for (i = 0; i < RTL8152_MAX_RX; i++)
  1712. usb_kill_urb(tp->rx_info[i].urb);
  1713. while (!skb_queue_empty(&tp->rx_queue))
  1714. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1715. return 0;
  1716. }
  1717. static int rtl_enable(struct r8152 *tp)
  1718. {
  1719. u32 ocp_data;
  1720. r8152b_reset_packet_filter(tp);
  1721. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1722. ocp_data |= CR_RE | CR_TE;
  1723. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1724. rxdy_gated_en(tp, false);
  1725. return 0;
  1726. }
  1727. static int rtl8152_enable(struct r8152 *tp)
  1728. {
  1729. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1730. return -ENODEV;
  1731. set_tx_qlen(tp);
  1732. rtl_set_eee_plus(tp);
  1733. return rtl_enable(tp);
  1734. }
  1735. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1736. {
  1737. u32 ocp_data = tp->coalesce / 8;
  1738. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1739. }
  1740. static void r8153_set_rx_early_size(struct r8152 *tp)
  1741. {
  1742. u32 mtu = tp->netdev->mtu;
  1743. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1744. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1745. }
  1746. static int rtl8153_enable(struct r8152 *tp)
  1747. {
  1748. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1749. return -ENODEV;
  1750. set_tx_qlen(tp);
  1751. rtl_set_eee_plus(tp);
  1752. r8153_set_rx_early_timeout(tp);
  1753. r8153_set_rx_early_size(tp);
  1754. return rtl_enable(tp);
  1755. }
  1756. static void rtl_disable(struct r8152 *tp)
  1757. {
  1758. u32 ocp_data;
  1759. int i;
  1760. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1761. rtl_drop_queued_tx(tp);
  1762. return;
  1763. }
  1764. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1765. ocp_data &= ~RCR_ACPT_ALL;
  1766. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1767. rtl_drop_queued_tx(tp);
  1768. for (i = 0; i < RTL8152_MAX_TX; i++)
  1769. usb_kill_urb(tp->tx_info[i].urb);
  1770. rxdy_gated_en(tp, true);
  1771. for (i = 0; i < 1000; i++) {
  1772. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1773. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1774. break;
  1775. usleep_range(1000, 2000);
  1776. }
  1777. for (i = 0; i < 1000; i++) {
  1778. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1779. break;
  1780. usleep_range(1000, 2000);
  1781. }
  1782. rtl_stop_rx(tp);
  1783. rtl8152_nic_reset(tp);
  1784. }
  1785. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1786. {
  1787. u32 ocp_data;
  1788. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1789. if (enable)
  1790. ocp_data |= POWER_CUT;
  1791. else
  1792. ocp_data &= ~POWER_CUT;
  1793. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1794. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1795. ocp_data &= ~RESUME_INDICATE;
  1796. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1797. }
  1798. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1799. {
  1800. u32 ocp_data;
  1801. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1802. if (enable)
  1803. ocp_data |= CPCR_RX_VLAN;
  1804. else
  1805. ocp_data &= ~CPCR_RX_VLAN;
  1806. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1807. }
  1808. static int rtl8152_set_features(struct net_device *dev,
  1809. netdev_features_t features)
  1810. {
  1811. netdev_features_t changed = features ^ dev->features;
  1812. struct r8152 *tp = netdev_priv(dev);
  1813. int ret;
  1814. ret = usb_autopm_get_interface(tp->intf);
  1815. if (ret < 0)
  1816. goto out;
  1817. mutex_lock(&tp->control);
  1818. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1819. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1820. rtl_rx_vlan_en(tp, true);
  1821. else
  1822. rtl_rx_vlan_en(tp, false);
  1823. }
  1824. mutex_unlock(&tp->control);
  1825. usb_autopm_put_interface(tp->intf);
  1826. out:
  1827. return ret;
  1828. }
  1829. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1830. static u32 __rtl_get_wol(struct r8152 *tp)
  1831. {
  1832. u32 ocp_data;
  1833. u32 wolopts = 0;
  1834. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1835. if (!(ocp_data & LAN_WAKE_EN))
  1836. return 0;
  1837. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1838. if (ocp_data & LINK_ON_WAKE_EN)
  1839. wolopts |= WAKE_PHY;
  1840. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1841. if (ocp_data & UWF_EN)
  1842. wolopts |= WAKE_UCAST;
  1843. if (ocp_data & BWF_EN)
  1844. wolopts |= WAKE_BCAST;
  1845. if (ocp_data & MWF_EN)
  1846. wolopts |= WAKE_MCAST;
  1847. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1848. if (ocp_data & MAGIC_EN)
  1849. wolopts |= WAKE_MAGIC;
  1850. return wolopts;
  1851. }
  1852. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1853. {
  1854. u32 ocp_data;
  1855. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1856. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1857. ocp_data &= ~LINK_ON_WAKE_EN;
  1858. if (wolopts & WAKE_PHY)
  1859. ocp_data |= LINK_ON_WAKE_EN;
  1860. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1861. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1862. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1863. if (wolopts & WAKE_UCAST)
  1864. ocp_data |= UWF_EN;
  1865. if (wolopts & WAKE_BCAST)
  1866. ocp_data |= BWF_EN;
  1867. if (wolopts & WAKE_MCAST)
  1868. ocp_data |= MWF_EN;
  1869. if (wolopts & WAKE_ANY)
  1870. ocp_data |= LAN_WAKE_EN;
  1871. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1872. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1873. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1874. ocp_data &= ~MAGIC_EN;
  1875. if (wolopts & WAKE_MAGIC)
  1876. ocp_data |= MAGIC_EN;
  1877. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1878. if (wolopts & WAKE_ANY)
  1879. device_set_wakeup_enable(&tp->udev->dev, true);
  1880. else
  1881. device_set_wakeup_enable(&tp->udev->dev, false);
  1882. }
  1883. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1884. {
  1885. if (enable) {
  1886. u32 ocp_data;
  1887. __rtl_set_wol(tp, WAKE_ANY);
  1888. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1889. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1890. ocp_data |= LINK_OFF_WAKE_EN;
  1891. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1892. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1893. } else {
  1894. __rtl_set_wol(tp, tp->saved_wolopts);
  1895. }
  1896. }
  1897. static void rtl_phy_reset(struct r8152 *tp)
  1898. {
  1899. u16 data;
  1900. int i;
  1901. clear_bit(PHY_RESET, &tp->flags);
  1902. data = r8152_mdio_read(tp, MII_BMCR);
  1903. /* don't reset again before the previous one complete */
  1904. if (data & BMCR_RESET)
  1905. return;
  1906. data |= BMCR_RESET;
  1907. r8152_mdio_write(tp, MII_BMCR, data);
  1908. for (i = 0; i < 50; i++) {
  1909. msleep(20);
  1910. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1911. break;
  1912. }
  1913. }
  1914. static void r8153_teredo_off(struct r8152 *tp)
  1915. {
  1916. u32 ocp_data;
  1917. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1918. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1919. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1920. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1921. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1922. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1923. }
  1924. static void r8152b_disable_aldps(struct r8152 *tp)
  1925. {
  1926. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1927. msleep(20);
  1928. }
  1929. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1930. {
  1931. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1932. LINKENA | DIS_SDSAVE);
  1933. }
  1934. static void rtl8152_disable(struct r8152 *tp)
  1935. {
  1936. r8152b_disable_aldps(tp);
  1937. rtl_disable(tp);
  1938. r8152b_enable_aldps(tp);
  1939. }
  1940. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1941. {
  1942. u16 data;
  1943. data = r8152_mdio_read(tp, MII_BMCR);
  1944. if (data & BMCR_PDOWN) {
  1945. data &= ~BMCR_PDOWN;
  1946. r8152_mdio_write(tp, MII_BMCR, data);
  1947. }
  1948. set_bit(PHY_RESET, &tp->flags);
  1949. }
  1950. static void r8152b_exit_oob(struct r8152 *tp)
  1951. {
  1952. u32 ocp_data;
  1953. int i;
  1954. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1955. ocp_data &= ~RCR_ACPT_ALL;
  1956. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1957. rxdy_gated_en(tp, true);
  1958. r8153_teredo_off(tp);
  1959. r8152b_hw_phy_cfg(tp);
  1960. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1961. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1962. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1963. ocp_data &= ~NOW_IS_OOB;
  1964. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1965. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1966. ocp_data &= ~MCU_BORW_EN;
  1967. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1968. for (i = 0; i < 1000; i++) {
  1969. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1970. if (ocp_data & LINK_LIST_READY)
  1971. break;
  1972. usleep_range(1000, 2000);
  1973. }
  1974. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1975. ocp_data |= RE_INIT_LL;
  1976. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1977. for (i = 0; i < 1000; i++) {
  1978. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1979. if (ocp_data & LINK_LIST_READY)
  1980. break;
  1981. usleep_range(1000, 2000);
  1982. }
  1983. rtl8152_nic_reset(tp);
  1984. /* rx share fifo credit full threshold */
  1985. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1986. if (tp->udev->speed == USB_SPEED_FULL ||
  1987. tp->udev->speed == USB_SPEED_LOW) {
  1988. /* rx share fifo credit near full threshold */
  1989. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1990. RXFIFO_THR2_FULL);
  1991. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1992. RXFIFO_THR3_FULL);
  1993. } else {
  1994. /* rx share fifo credit near full threshold */
  1995. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1996. RXFIFO_THR2_HIGH);
  1997. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1998. RXFIFO_THR3_HIGH);
  1999. }
  2000. /* TX share fifo free credit full threshold */
  2001. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2002. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2003. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2004. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2005. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2006. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2007. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2008. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2009. ocp_data |= TCR0_AUTO_FIFO;
  2010. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2011. }
  2012. static void r8152b_enter_oob(struct r8152 *tp)
  2013. {
  2014. u32 ocp_data;
  2015. int i;
  2016. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2017. ocp_data &= ~NOW_IS_OOB;
  2018. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2019. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2020. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2021. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2022. rtl_disable(tp);
  2023. for (i = 0; i < 1000; i++) {
  2024. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2025. if (ocp_data & LINK_LIST_READY)
  2026. break;
  2027. usleep_range(1000, 2000);
  2028. }
  2029. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2030. ocp_data |= RE_INIT_LL;
  2031. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2032. for (i = 0; i < 1000; i++) {
  2033. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2034. if (ocp_data & LINK_LIST_READY)
  2035. break;
  2036. usleep_range(1000, 2000);
  2037. }
  2038. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2039. rtl_rx_vlan_en(tp, true);
  2040. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2041. ocp_data |= ALDPS_PROXY_MODE;
  2042. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2043. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2044. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2045. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2046. rxdy_gated_en(tp, false);
  2047. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2048. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2049. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2050. }
  2051. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2052. {
  2053. u32 ocp_data;
  2054. u16 data;
  2055. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2056. data = r8152_mdio_read(tp, MII_BMCR);
  2057. if (data & BMCR_PDOWN) {
  2058. data &= ~BMCR_PDOWN;
  2059. r8152_mdio_write(tp, MII_BMCR, data);
  2060. }
  2061. if (tp->version == RTL_VER_03) {
  2062. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2063. data &= ~CTAP_SHORT_EN;
  2064. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2065. }
  2066. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2067. data |= EEE_CLKDIV_EN;
  2068. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2069. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2070. data |= EN_10M_BGOFF;
  2071. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2072. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2073. data |= EN_10M_PLLOFF;
  2074. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2075. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2076. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2077. ocp_data |= PFM_PWM_SWITCH;
  2078. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2079. /* Enable LPF corner auto tune */
  2080. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2081. /* Adjust 10M Amplitude */
  2082. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2083. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2084. set_bit(PHY_RESET, &tp->flags);
  2085. }
  2086. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2087. {
  2088. u8 u1u2[8];
  2089. if (enable)
  2090. memset(u1u2, 0xff, sizeof(u1u2));
  2091. else
  2092. memset(u1u2, 0x00, sizeof(u1u2));
  2093. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2094. }
  2095. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2096. {
  2097. u32 ocp_data;
  2098. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2099. if (enable)
  2100. ocp_data |= U2P3_ENABLE;
  2101. else
  2102. ocp_data &= ~U2P3_ENABLE;
  2103. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2104. }
  2105. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2106. {
  2107. u32 ocp_data;
  2108. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2109. if (enable)
  2110. ocp_data |= PWR_EN | PHASE2_EN;
  2111. else
  2112. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2113. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2114. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2115. ocp_data &= ~PCUT_STATUS;
  2116. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2117. }
  2118. static void r8153_first_init(struct r8152 *tp)
  2119. {
  2120. u32 ocp_data;
  2121. int i;
  2122. rxdy_gated_en(tp, true);
  2123. r8153_teredo_off(tp);
  2124. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2125. ocp_data &= ~RCR_ACPT_ALL;
  2126. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2127. r8153_hw_phy_cfg(tp);
  2128. rtl8152_nic_reset(tp);
  2129. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2130. ocp_data &= ~NOW_IS_OOB;
  2131. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2132. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2133. ocp_data &= ~MCU_BORW_EN;
  2134. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2135. for (i = 0; i < 1000; i++) {
  2136. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2137. if (ocp_data & LINK_LIST_READY)
  2138. break;
  2139. usleep_range(1000, 2000);
  2140. }
  2141. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2142. ocp_data |= RE_INIT_LL;
  2143. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2144. for (i = 0; i < 1000; i++) {
  2145. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2146. if (ocp_data & LINK_LIST_READY)
  2147. break;
  2148. usleep_range(1000, 2000);
  2149. }
  2150. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2151. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2152. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2153. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2154. ocp_data |= TCR0_AUTO_FIFO;
  2155. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2156. rtl8152_nic_reset(tp);
  2157. /* rx share fifo credit full threshold */
  2158. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2159. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2160. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2161. /* TX share fifo free credit full threshold */
  2162. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2163. /* rx aggregation */
  2164. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2165. ocp_data &= ~RX_AGG_DISABLE;
  2166. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2167. }
  2168. static void r8153_enter_oob(struct r8152 *tp)
  2169. {
  2170. u32 ocp_data;
  2171. int i;
  2172. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2173. ocp_data &= ~NOW_IS_OOB;
  2174. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2175. rtl_disable(tp);
  2176. for (i = 0; i < 1000; i++) {
  2177. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2178. if (ocp_data & LINK_LIST_READY)
  2179. break;
  2180. usleep_range(1000, 2000);
  2181. }
  2182. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2183. ocp_data |= RE_INIT_LL;
  2184. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2185. for (i = 0; i < 1000; i++) {
  2186. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2187. if (ocp_data & LINK_LIST_READY)
  2188. break;
  2189. usleep_range(1000, 2000);
  2190. }
  2191. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2192. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2193. ocp_data &= ~TEREDO_WAKE_MASK;
  2194. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2195. rtl_rx_vlan_en(tp, true);
  2196. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2197. ocp_data |= ALDPS_PROXY_MODE;
  2198. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2199. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2200. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2201. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2202. rxdy_gated_en(tp, false);
  2203. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2204. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2205. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2206. }
  2207. static void r8153_disable_aldps(struct r8152 *tp)
  2208. {
  2209. u16 data;
  2210. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2211. data &= ~EN_ALDPS;
  2212. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2213. msleep(20);
  2214. }
  2215. static void r8153_enable_aldps(struct r8152 *tp)
  2216. {
  2217. u16 data;
  2218. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2219. data |= EN_ALDPS;
  2220. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2221. }
  2222. static void rtl8153_disable(struct r8152 *tp)
  2223. {
  2224. r8153_disable_aldps(tp);
  2225. rtl_disable(tp);
  2226. r8153_enable_aldps(tp);
  2227. }
  2228. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2229. {
  2230. u16 bmcr, anar, gbcr;
  2231. int ret = 0;
  2232. cancel_delayed_work_sync(&tp->schedule);
  2233. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2234. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2235. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2236. if (tp->mii.supports_gmii) {
  2237. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2238. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2239. } else {
  2240. gbcr = 0;
  2241. }
  2242. if (autoneg == AUTONEG_DISABLE) {
  2243. if (speed == SPEED_10) {
  2244. bmcr = 0;
  2245. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2246. } else if (speed == SPEED_100) {
  2247. bmcr = BMCR_SPEED100;
  2248. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2249. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2250. bmcr = BMCR_SPEED1000;
  2251. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2252. } else {
  2253. ret = -EINVAL;
  2254. goto out;
  2255. }
  2256. if (duplex == DUPLEX_FULL)
  2257. bmcr |= BMCR_FULLDPLX;
  2258. } else {
  2259. if (speed == SPEED_10) {
  2260. if (duplex == DUPLEX_FULL)
  2261. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2262. else
  2263. anar |= ADVERTISE_10HALF;
  2264. } else if (speed == SPEED_100) {
  2265. if (duplex == DUPLEX_FULL) {
  2266. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2267. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2268. } else {
  2269. anar |= ADVERTISE_10HALF;
  2270. anar |= ADVERTISE_100HALF;
  2271. }
  2272. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2273. if (duplex == DUPLEX_FULL) {
  2274. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2275. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2276. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2277. } else {
  2278. anar |= ADVERTISE_10HALF;
  2279. anar |= ADVERTISE_100HALF;
  2280. gbcr |= ADVERTISE_1000HALF;
  2281. }
  2282. } else {
  2283. ret = -EINVAL;
  2284. goto out;
  2285. }
  2286. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2287. }
  2288. if (test_bit(PHY_RESET, &tp->flags))
  2289. bmcr |= BMCR_RESET;
  2290. if (tp->mii.supports_gmii)
  2291. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2292. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2293. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2294. if (test_bit(PHY_RESET, &tp->flags)) {
  2295. int i;
  2296. clear_bit(PHY_RESET, &tp->flags);
  2297. for (i = 0; i < 50; i++) {
  2298. msleep(20);
  2299. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2300. break;
  2301. }
  2302. }
  2303. out:
  2304. return ret;
  2305. }
  2306. static void rtl8152_up(struct r8152 *tp)
  2307. {
  2308. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2309. return;
  2310. r8152b_disable_aldps(tp);
  2311. r8152b_exit_oob(tp);
  2312. r8152b_enable_aldps(tp);
  2313. }
  2314. static void rtl8152_down(struct r8152 *tp)
  2315. {
  2316. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2317. rtl_drop_queued_tx(tp);
  2318. return;
  2319. }
  2320. r8152_power_cut_en(tp, false);
  2321. r8152b_disable_aldps(tp);
  2322. r8152b_enter_oob(tp);
  2323. r8152b_enable_aldps(tp);
  2324. }
  2325. static void rtl8153_up(struct r8152 *tp)
  2326. {
  2327. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2328. return;
  2329. r8153_disable_aldps(tp);
  2330. r8153_first_init(tp);
  2331. r8153_enable_aldps(tp);
  2332. }
  2333. static void rtl8153_down(struct r8152 *tp)
  2334. {
  2335. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2336. rtl_drop_queued_tx(tp);
  2337. return;
  2338. }
  2339. r8153_u1u2en(tp, false);
  2340. r8153_power_cut_en(tp, false);
  2341. r8153_disable_aldps(tp);
  2342. r8153_enter_oob(tp);
  2343. r8153_enable_aldps(tp);
  2344. }
  2345. static void set_carrier(struct r8152 *tp)
  2346. {
  2347. struct net_device *netdev = tp->netdev;
  2348. u8 speed;
  2349. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  2350. speed = rtl8152_get_speed(tp);
  2351. if (speed & LINK_STATUS) {
  2352. if (!netif_carrier_ok(netdev)) {
  2353. tp->rtl_ops.enable(tp);
  2354. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2355. netif_carrier_on(netdev);
  2356. rtl_start_rx(tp);
  2357. }
  2358. } else {
  2359. if (netif_carrier_ok(netdev)) {
  2360. netif_carrier_off(netdev);
  2361. napi_disable(&tp->napi);
  2362. tp->rtl_ops.disable(tp);
  2363. napi_enable(&tp->napi);
  2364. }
  2365. }
  2366. }
  2367. static void rtl_work_func_t(struct work_struct *work)
  2368. {
  2369. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2370. /* If the device is unplugged or !netif_running(), the workqueue
  2371. * doesn't need to wake the device, and could return directly.
  2372. */
  2373. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2374. return;
  2375. if (usb_autopm_get_interface(tp->intf) < 0)
  2376. return;
  2377. if (!test_bit(WORK_ENABLE, &tp->flags))
  2378. goto out1;
  2379. if (!mutex_trylock(&tp->control)) {
  2380. schedule_delayed_work(&tp->schedule, 0);
  2381. goto out1;
  2382. }
  2383. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  2384. set_carrier(tp);
  2385. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2386. _rtl8152_set_rx_mode(tp->netdev);
  2387. /* don't schedule napi before linking */
  2388. if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
  2389. netif_carrier_ok(tp->netdev)) {
  2390. clear_bit(SCHEDULE_NAPI, &tp->flags);
  2391. napi_schedule(&tp->napi);
  2392. }
  2393. if (test_bit(PHY_RESET, &tp->flags))
  2394. rtl_phy_reset(tp);
  2395. mutex_unlock(&tp->control);
  2396. out1:
  2397. usb_autopm_put_interface(tp->intf);
  2398. }
  2399. static int rtl8152_open(struct net_device *netdev)
  2400. {
  2401. struct r8152 *tp = netdev_priv(netdev);
  2402. int res = 0;
  2403. res = alloc_all_mem(tp);
  2404. if (res)
  2405. goto out;
  2406. netif_carrier_off(netdev);
  2407. res = usb_autopm_get_interface(tp->intf);
  2408. if (res < 0) {
  2409. free_all_mem(tp);
  2410. goto out;
  2411. }
  2412. mutex_lock(&tp->control);
  2413. /* The WORK_ENABLE may be set when autoresume occurs */
  2414. if (test_bit(WORK_ENABLE, &tp->flags)) {
  2415. clear_bit(WORK_ENABLE, &tp->flags);
  2416. usb_kill_urb(tp->intr_urb);
  2417. cancel_delayed_work_sync(&tp->schedule);
  2418. /* disable the tx/rx, if the workqueue has enabled them. */
  2419. if (netif_carrier_ok(netdev))
  2420. tp->rtl_ops.disable(tp);
  2421. }
  2422. tp->rtl_ops.up(tp);
  2423. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2424. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2425. DUPLEX_FULL);
  2426. netif_carrier_off(netdev);
  2427. netif_start_queue(netdev);
  2428. set_bit(WORK_ENABLE, &tp->flags);
  2429. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2430. if (res) {
  2431. if (res == -ENODEV)
  2432. netif_device_detach(tp->netdev);
  2433. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2434. res);
  2435. free_all_mem(tp);
  2436. } else {
  2437. napi_enable(&tp->napi);
  2438. }
  2439. mutex_unlock(&tp->control);
  2440. usb_autopm_put_interface(tp->intf);
  2441. out:
  2442. return res;
  2443. }
  2444. static int rtl8152_close(struct net_device *netdev)
  2445. {
  2446. struct r8152 *tp = netdev_priv(netdev);
  2447. int res = 0;
  2448. napi_disable(&tp->napi);
  2449. clear_bit(WORK_ENABLE, &tp->flags);
  2450. usb_kill_urb(tp->intr_urb);
  2451. cancel_delayed_work_sync(&tp->schedule);
  2452. netif_stop_queue(netdev);
  2453. res = usb_autopm_get_interface(tp->intf);
  2454. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2455. rtl_drop_queued_tx(tp);
  2456. rtl_stop_rx(tp);
  2457. } else {
  2458. mutex_lock(&tp->control);
  2459. /* The autosuspend may have been enabled and wouldn't
  2460. * be disable when autoresume occurs, because the
  2461. * netif_running() would be false.
  2462. */
  2463. rtl_runtime_suspend_enable(tp, false);
  2464. tp->rtl_ops.down(tp);
  2465. mutex_unlock(&tp->control);
  2466. usb_autopm_put_interface(tp->intf);
  2467. }
  2468. free_all_mem(tp);
  2469. return res;
  2470. }
  2471. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2472. {
  2473. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2474. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2475. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2476. }
  2477. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2478. {
  2479. u16 data;
  2480. r8152_mmd_indirect(tp, dev, reg);
  2481. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2482. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2483. return data;
  2484. }
  2485. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2486. {
  2487. r8152_mmd_indirect(tp, dev, reg);
  2488. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2489. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2490. }
  2491. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2492. {
  2493. u16 config1, config2, config3;
  2494. u32 ocp_data;
  2495. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2496. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2497. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2498. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2499. if (enable) {
  2500. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2501. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2502. config1 |= sd_rise_time(1);
  2503. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2504. config3 |= fast_snr(42);
  2505. } else {
  2506. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2507. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2508. RX_QUIET_EN);
  2509. config1 |= sd_rise_time(7);
  2510. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2511. config3 |= fast_snr(511);
  2512. }
  2513. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2514. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2515. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2516. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2517. }
  2518. static void r8152b_enable_eee(struct r8152 *tp)
  2519. {
  2520. r8152_eee_en(tp, true);
  2521. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2522. }
  2523. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2524. {
  2525. u32 ocp_data;
  2526. u16 config;
  2527. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2528. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2529. if (enable) {
  2530. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2531. config |= EEE10_EN;
  2532. } else {
  2533. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2534. config &= ~EEE10_EN;
  2535. }
  2536. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2537. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2538. }
  2539. static void r8153_enable_eee(struct r8152 *tp)
  2540. {
  2541. r8153_eee_en(tp, true);
  2542. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2543. }
  2544. static void r8152b_enable_fc(struct r8152 *tp)
  2545. {
  2546. u16 anar;
  2547. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2548. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2549. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2550. }
  2551. static void rtl_tally_reset(struct r8152 *tp)
  2552. {
  2553. u32 ocp_data;
  2554. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2555. ocp_data |= TALLY_RESET;
  2556. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2557. }
  2558. static void r8152b_init(struct r8152 *tp)
  2559. {
  2560. u32 ocp_data;
  2561. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2562. return;
  2563. r8152b_disable_aldps(tp);
  2564. if (tp->version == RTL_VER_01) {
  2565. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2566. ocp_data &= ~LED_MODE_MASK;
  2567. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2568. }
  2569. r8152_power_cut_en(tp, false);
  2570. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2571. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2572. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2573. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2574. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2575. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2576. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2577. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2578. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2579. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2580. r8152b_enable_eee(tp);
  2581. r8152b_enable_aldps(tp);
  2582. r8152b_enable_fc(tp);
  2583. rtl_tally_reset(tp);
  2584. /* enable rx aggregation */
  2585. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2586. ocp_data &= ~RX_AGG_DISABLE;
  2587. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2588. }
  2589. static void r8153_init(struct r8152 *tp)
  2590. {
  2591. u32 ocp_data;
  2592. int i;
  2593. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2594. return;
  2595. r8153_disable_aldps(tp);
  2596. r8153_u1u2en(tp, false);
  2597. for (i = 0; i < 500; i++) {
  2598. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2599. AUTOLOAD_DONE)
  2600. break;
  2601. msleep(20);
  2602. }
  2603. for (i = 0; i < 500; i++) {
  2604. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2605. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2606. break;
  2607. msleep(20);
  2608. }
  2609. r8153_u2p3en(tp, false);
  2610. if (tp->version == RTL_VER_04) {
  2611. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2612. ocp_data &= ~pwd_dn_scale_mask;
  2613. ocp_data |= pwd_dn_scale(96);
  2614. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2615. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2616. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2617. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2618. } else if (tp->version == RTL_VER_05) {
  2619. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2620. ocp_data &= ~ECM_ALDPS;
  2621. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2622. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2623. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2624. ocp_data &= ~DYNAMIC_BURST;
  2625. else
  2626. ocp_data |= DYNAMIC_BURST;
  2627. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2628. }
  2629. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2630. ocp_data |= EP4_FULL_FC;
  2631. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2632. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2633. ocp_data &= ~TIMER11_EN;
  2634. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2635. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2636. ocp_data &= ~LED_MODE_MASK;
  2637. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2638. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2639. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2640. ocp_data |= LPM_TIMER_500MS;
  2641. else
  2642. ocp_data |= LPM_TIMER_500US;
  2643. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2644. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2645. ocp_data &= ~SEN_VAL_MASK;
  2646. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2647. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2648. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2649. r8153_power_cut_en(tp, false);
  2650. r8153_u1u2en(tp, true);
  2651. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2652. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2653. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2654. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2655. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2656. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2657. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2658. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2659. EEE_SPDWN_EN);
  2660. r8153_enable_eee(tp);
  2661. r8153_enable_aldps(tp);
  2662. r8152b_enable_fc(tp);
  2663. rtl_tally_reset(tp);
  2664. }
  2665. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2666. {
  2667. struct r8152 *tp = usb_get_intfdata(intf);
  2668. struct net_device *netdev = tp->netdev;
  2669. int ret = 0;
  2670. mutex_lock(&tp->control);
  2671. if (PMSG_IS_AUTO(message)) {
  2672. if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
  2673. ret = -EBUSY;
  2674. goto out1;
  2675. }
  2676. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2677. } else {
  2678. netif_device_detach(netdev);
  2679. }
  2680. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2681. clear_bit(WORK_ENABLE, &tp->flags);
  2682. usb_kill_urb(tp->intr_urb);
  2683. napi_disable(&tp->napi);
  2684. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2685. rtl_stop_rx(tp);
  2686. rtl_runtime_suspend_enable(tp, true);
  2687. } else {
  2688. cancel_delayed_work_sync(&tp->schedule);
  2689. tp->rtl_ops.down(tp);
  2690. }
  2691. napi_enable(&tp->napi);
  2692. }
  2693. out1:
  2694. mutex_unlock(&tp->control);
  2695. return ret;
  2696. }
  2697. static int rtl8152_resume(struct usb_interface *intf)
  2698. {
  2699. struct r8152 *tp = usb_get_intfdata(intf);
  2700. mutex_lock(&tp->control);
  2701. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2702. tp->rtl_ops.init(tp);
  2703. netif_device_attach(tp->netdev);
  2704. }
  2705. if (netif_running(tp->netdev)) {
  2706. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2707. rtl_runtime_suspend_enable(tp, false);
  2708. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2709. set_bit(WORK_ENABLE, &tp->flags);
  2710. if (netif_carrier_ok(tp->netdev))
  2711. rtl_start_rx(tp);
  2712. } else {
  2713. tp->rtl_ops.up(tp);
  2714. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2715. tp->mii.supports_gmii ?
  2716. SPEED_1000 : SPEED_100,
  2717. DUPLEX_FULL);
  2718. netif_carrier_off(tp->netdev);
  2719. set_bit(WORK_ENABLE, &tp->flags);
  2720. }
  2721. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2722. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2723. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2724. }
  2725. mutex_unlock(&tp->control);
  2726. return 0;
  2727. }
  2728. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2729. {
  2730. struct r8152 *tp = netdev_priv(dev);
  2731. if (usb_autopm_get_interface(tp->intf) < 0)
  2732. return;
  2733. mutex_lock(&tp->control);
  2734. wol->supported = WAKE_ANY;
  2735. wol->wolopts = __rtl_get_wol(tp);
  2736. mutex_unlock(&tp->control);
  2737. usb_autopm_put_interface(tp->intf);
  2738. }
  2739. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2740. {
  2741. struct r8152 *tp = netdev_priv(dev);
  2742. int ret;
  2743. ret = usb_autopm_get_interface(tp->intf);
  2744. if (ret < 0)
  2745. goto out_set_wol;
  2746. mutex_lock(&tp->control);
  2747. __rtl_set_wol(tp, wol->wolopts);
  2748. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2749. mutex_unlock(&tp->control);
  2750. usb_autopm_put_interface(tp->intf);
  2751. out_set_wol:
  2752. return ret;
  2753. }
  2754. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2755. {
  2756. struct r8152 *tp = netdev_priv(dev);
  2757. return tp->msg_enable;
  2758. }
  2759. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2760. {
  2761. struct r8152 *tp = netdev_priv(dev);
  2762. tp->msg_enable = value;
  2763. }
  2764. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2765. struct ethtool_drvinfo *info)
  2766. {
  2767. struct r8152 *tp = netdev_priv(netdev);
  2768. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2769. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2770. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2771. }
  2772. static
  2773. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2774. {
  2775. struct r8152 *tp = netdev_priv(netdev);
  2776. int ret;
  2777. if (!tp->mii.mdio_read)
  2778. return -EOPNOTSUPP;
  2779. ret = usb_autopm_get_interface(tp->intf);
  2780. if (ret < 0)
  2781. goto out;
  2782. mutex_lock(&tp->control);
  2783. ret = mii_ethtool_gset(&tp->mii, cmd);
  2784. mutex_unlock(&tp->control);
  2785. usb_autopm_put_interface(tp->intf);
  2786. out:
  2787. return ret;
  2788. }
  2789. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2790. {
  2791. struct r8152 *tp = netdev_priv(dev);
  2792. int ret;
  2793. ret = usb_autopm_get_interface(tp->intf);
  2794. if (ret < 0)
  2795. goto out;
  2796. mutex_lock(&tp->control);
  2797. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2798. mutex_unlock(&tp->control);
  2799. usb_autopm_put_interface(tp->intf);
  2800. out:
  2801. return ret;
  2802. }
  2803. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2804. "tx_packets",
  2805. "rx_packets",
  2806. "tx_errors",
  2807. "rx_errors",
  2808. "rx_missed",
  2809. "align_errors",
  2810. "tx_single_collisions",
  2811. "tx_multi_collisions",
  2812. "rx_unicast",
  2813. "rx_broadcast",
  2814. "rx_multicast",
  2815. "tx_aborted",
  2816. "tx_underrun",
  2817. };
  2818. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2819. {
  2820. switch (sset) {
  2821. case ETH_SS_STATS:
  2822. return ARRAY_SIZE(rtl8152_gstrings);
  2823. default:
  2824. return -EOPNOTSUPP;
  2825. }
  2826. }
  2827. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2828. struct ethtool_stats *stats, u64 *data)
  2829. {
  2830. struct r8152 *tp = netdev_priv(dev);
  2831. struct tally_counter tally;
  2832. if (usb_autopm_get_interface(tp->intf) < 0)
  2833. return;
  2834. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2835. usb_autopm_put_interface(tp->intf);
  2836. data[0] = le64_to_cpu(tally.tx_packets);
  2837. data[1] = le64_to_cpu(tally.rx_packets);
  2838. data[2] = le64_to_cpu(tally.tx_errors);
  2839. data[3] = le32_to_cpu(tally.rx_errors);
  2840. data[4] = le16_to_cpu(tally.rx_missed);
  2841. data[5] = le16_to_cpu(tally.align_errors);
  2842. data[6] = le32_to_cpu(tally.tx_one_collision);
  2843. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2844. data[8] = le64_to_cpu(tally.rx_unicast);
  2845. data[9] = le64_to_cpu(tally.rx_broadcast);
  2846. data[10] = le32_to_cpu(tally.rx_multicast);
  2847. data[11] = le16_to_cpu(tally.tx_aborted);
  2848. data[12] = le16_to_cpu(tally.tx_underrun);
  2849. }
  2850. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2851. {
  2852. switch (stringset) {
  2853. case ETH_SS_STATS:
  2854. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2855. break;
  2856. }
  2857. }
  2858. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2859. {
  2860. u32 ocp_data, lp, adv, supported = 0;
  2861. u16 val;
  2862. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2863. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2864. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2865. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2866. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2867. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2868. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2869. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2870. eee->eee_enabled = !!ocp_data;
  2871. eee->eee_active = !!(supported & adv & lp);
  2872. eee->supported = supported;
  2873. eee->advertised = adv;
  2874. eee->lp_advertised = lp;
  2875. return 0;
  2876. }
  2877. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2878. {
  2879. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2880. r8152_eee_en(tp, eee->eee_enabled);
  2881. if (!eee->eee_enabled)
  2882. val = 0;
  2883. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2884. return 0;
  2885. }
  2886. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2887. {
  2888. u32 ocp_data, lp, adv, supported = 0;
  2889. u16 val;
  2890. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  2891. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2892. val = ocp_reg_read(tp, OCP_EEE_ADV);
  2893. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2894. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  2895. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2896. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2897. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2898. eee->eee_enabled = !!ocp_data;
  2899. eee->eee_active = !!(supported & adv & lp);
  2900. eee->supported = supported;
  2901. eee->advertised = adv;
  2902. eee->lp_advertised = lp;
  2903. return 0;
  2904. }
  2905. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2906. {
  2907. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2908. r8153_eee_en(tp, eee->eee_enabled);
  2909. if (!eee->eee_enabled)
  2910. val = 0;
  2911. ocp_reg_write(tp, OCP_EEE_ADV, val);
  2912. return 0;
  2913. }
  2914. static int
  2915. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  2916. {
  2917. struct r8152 *tp = netdev_priv(net);
  2918. int ret;
  2919. ret = usb_autopm_get_interface(tp->intf);
  2920. if (ret < 0)
  2921. goto out;
  2922. mutex_lock(&tp->control);
  2923. ret = tp->rtl_ops.eee_get(tp, edata);
  2924. mutex_unlock(&tp->control);
  2925. usb_autopm_put_interface(tp->intf);
  2926. out:
  2927. return ret;
  2928. }
  2929. static int
  2930. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  2931. {
  2932. struct r8152 *tp = netdev_priv(net);
  2933. int ret;
  2934. ret = usb_autopm_get_interface(tp->intf);
  2935. if (ret < 0)
  2936. goto out;
  2937. mutex_lock(&tp->control);
  2938. ret = tp->rtl_ops.eee_set(tp, edata);
  2939. if (!ret)
  2940. ret = mii_nway_restart(&tp->mii);
  2941. mutex_unlock(&tp->control);
  2942. usb_autopm_put_interface(tp->intf);
  2943. out:
  2944. return ret;
  2945. }
  2946. static int rtl8152_nway_reset(struct net_device *dev)
  2947. {
  2948. struct r8152 *tp = netdev_priv(dev);
  2949. int ret;
  2950. ret = usb_autopm_get_interface(tp->intf);
  2951. if (ret < 0)
  2952. goto out;
  2953. mutex_lock(&tp->control);
  2954. ret = mii_nway_restart(&tp->mii);
  2955. mutex_unlock(&tp->control);
  2956. usb_autopm_put_interface(tp->intf);
  2957. out:
  2958. return ret;
  2959. }
  2960. static int rtl8152_get_coalesce(struct net_device *netdev,
  2961. struct ethtool_coalesce *coalesce)
  2962. {
  2963. struct r8152 *tp = netdev_priv(netdev);
  2964. switch (tp->version) {
  2965. case RTL_VER_01:
  2966. case RTL_VER_02:
  2967. return -EOPNOTSUPP;
  2968. default:
  2969. break;
  2970. }
  2971. coalesce->rx_coalesce_usecs = tp->coalesce;
  2972. return 0;
  2973. }
  2974. static int rtl8152_set_coalesce(struct net_device *netdev,
  2975. struct ethtool_coalesce *coalesce)
  2976. {
  2977. struct r8152 *tp = netdev_priv(netdev);
  2978. int ret;
  2979. switch (tp->version) {
  2980. case RTL_VER_01:
  2981. case RTL_VER_02:
  2982. return -EOPNOTSUPP;
  2983. default:
  2984. break;
  2985. }
  2986. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  2987. return -EINVAL;
  2988. ret = usb_autopm_get_interface(tp->intf);
  2989. if (ret < 0)
  2990. return ret;
  2991. mutex_lock(&tp->control);
  2992. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  2993. tp->coalesce = coalesce->rx_coalesce_usecs;
  2994. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  2995. r8153_set_rx_early_timeout(tp);
  2996. }
  2997. mutex_unlock(&tp->control);
  2998. usb_autopm_put_interface(tp->intf);
  2999. return ret;
  3000. }
  3001. static struct ethtool_ops ops = {
  3002. .get_drvinfo = rtl8152_get_drvinfo,
  3003. .get_settings = rtl8152_get_settings,
  3004. .set_settings = rtl8152_set_settings,
  3005. .get_link = ethtool_op_get_link,
  3006. .nway_reset = rtl8152_nway_reset,
  3007. .get_msglevel = rtl8152_get_msglevel,
  3008. .set_msglevel = rtl8152_set_msglevel,
  3009. .get_wol = rtl8152_get_wol,
  3010. .set_wol = rtl8152_set_wol,
  3011. .get_strings = rtl8152_get_strings,
  3012. .get_sset_count = rtl8152_get_sset_count,
  3013. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3014. .get_coalesce = rtl8152_get_coalesce,
  3015. .set_coalesce = rtl8152_set_coalesce,
  3016. .get_eee = rtl_ethtool_get_eee,
  3017. .set_eee = rtl_ethtool_set_eee,
  3018. };
  3019. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3020. {
  3021. struct r8152 *tp = netdev_priv(netdev);
  3022. struct mii_ioctl_data *data = if_mii(rq);
  3023. int res;
  3024. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3025. return -ENODEV;
  3026. res = usb_autopm_get_interface(tp->intf);
  3027. if (res < 0)
  3028. goto out;
  3029. switch (cmd) {
  3030. case SIOCGMIIPHY:
  3031. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3032. break;
  3033. case SIOCGMIIREG:
  3034. mutex_lock(&tp->control);
  3035. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3036. mutex_unlock(&tp->control);
  3037. break;
  3038. case SIOCSMIIREG:
  3039. if (!capable(CAP_NET_ADMIN)) {
  3040. res = -EPERM;
  3041. break;
  3042. }
  3043. mutex_lock(&tp->control);
  3044. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3045. mutex_unlock(&tp->control);
  3046. break;
  3047. default:
  3048. res = -EOPNOTSUPP;
  3049. }
  3050. usb_autopm_put_interface(tp->intf);
  3051. out:
  3052. return res;
  3053. }
  3054. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3055. {
  3056. struct r8152 *tp = netdev_priv(dev);
  3057. int ret;
  3058. switch (tp->version) {
  3059. case RTL_VER_01:
  3060. case RTL_VER_02:
  3061. return eth_change_mtu(dev, new_mtu);
  3062. default:
  3063. break;
  3064. }
  3065. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3066. return -EINVAL;
  3067. ret = usb_autopm_get_interface(tp->intf);
  3068. if (ret < 0)
  3069. return ret;
  3070. mutex_lock(&tp->control);
  3071. dev->mtu = new_mtu;
  3072. if (netif_running(dev) && netif_carrier_ok(dev))
  3073. r8153_set_rx_early_size(tp);
  3074. mutex_unlock(&tp->control);
  3075. usb_autopm_put_interface(tp->intf);
  3076. return ret;
  3077. }
  3078. static const struct net_device_ops rtl8152_netdev_ops = {
  3079. .ndo_open = rtl8152_open,
  3080. .ndo_stop = rtl8152_close,
  3081. .ndo_do_ioctl = rtl8152_ioctl,
  3082. .ndo_start_xmit = rtl8152_start_xmit,
  3083. .ndo_tx_timeout = rtl8152_tx_timeout,
  3084. .ndo_set_features = rtl8152_set_features,
  3085. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3086. .ndo_set_mac_address = rtl8152_set_mac_address,
  3087. .ndo_change_mtu = rtl8152_change_mtu,
  3088. .ndo_validate_addr = eth_validate_addr,
  3089. .ndo_features_check = rtl8152_features_check,
  3090. };
  3091. static void r8152b_get_version(struct r8152 *tp)
  3092. {
  3093. u32 ocp_data;
  3094. u16 version;
  3095. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3096. version = (u16)(ocp_data & VERSION_MASK);
  3097. switch (version) {
  3098. case 0x4c00:
  3099. tp->version = RTL_VER_01;
  3100. break;
  3101. case 0x4c10:
  3102. tp->version = RTL_VER_02;
  3103. break;
  3104. case 0x5c00:
  3105. tp->version = RTL_VER_03;
  3106. tp->mii.supports_gmii = 1;
  3107. break;
  3108. case 0x5c10:
  3109. tp->version = RTL_VER_04;
  3110. tp->mii.supports_gmii = 1;
  3111. break;
  3112. case 0x5c20:
  3113. tp->version = RTL_VER_05;
  3114. tp->mii.supports_gmii = 1;
  3115. break;
  3116. default:
  3117. netif_info(tp, probe, tp->netdev,
  3118. "Unknown version 0x%04x\n", version);
  3119. break;
  3120. }
  3121. }
  3122. static void rtl8152_unload(struct r8152 *tp)
  3123. {
  3124. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3125. return;
  3126. if (tp->version != RTL_VER_01)
  3127. r8152_power_cut_en(tp, true);
  3128. }
  3129. static void rtl8153_unload(struct r8152 *tp)
  3130. {
  3131. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3132. return;
  3133. r8153_power_cut_en(tp, false);
  3134. }
  3135. static int rtl_ops_init(struct r8152 *tp)
  3136. {
  3137. struct rtl_ops *ops = &tp->rtl_ops;
  3138. int ret = 0;
  3139. switch (tp->version) {
  3140. case RTL_VER_01:
  3141. case RTL_VER_02:
  3142. ops->init = r8152b_init;
  3143. ops->enable = rtl8152_enable;
  3144. ops->disable = rtl8152_disable;
  3145. ops->up = rtl8152_up;
  3146. ops->down = rtl8152_down;
  3147. ops->unload = rtl8152_unload;
  3148. ops->eee_get = r8152_get_eee;
  3149. ops->eee_set = r8152_set_eee;
  3150. break;
  3151. case RTL_VER_03:
  3152. case RTL_VER_04:
  3153. case RTL_VER_05:
  3154. ops->init = r8153_init;
  3155. ops->enable = rtl8153_enable;
  3156. ops->disable = rtl8153_disable;
  3157. ops->up = rtl8153_up;
  3158. ops->down = rtl8153_down;
  3159. ops->unload = rtl8153_unload;
  3160. ops->eee_get = r8153_get_eee;
  3161. ops->eee_set = r8153_set_eee;
  3162. break;
  3163. default:
  3164. ret = -ENODEV;
  3165. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3166. break;
  3167. }
  3168. return ret;
  3169. }
  3170. static int rtl8152_probe(struct usb_interface *intf,
  3171. const struct usb_device_id *id)
  3172. {
  3173. struct usb_device *udev = interface_to_usbdev(intf);
  3174. struct r8152 *tp;
  3175. struct net_device *netdev;
  3176. int ret;
  3177. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3178. usb_driver_set_configuration(udev, 1);
  3179. return -ENODEV;
  3180. }
  3181. usb_reset_device(udev);
  3182. netdev = alloc_etherdev(sizeof(struct r8152));
  3183. if (!netdev) {
  3184. dev_err(&intf->dev, "Out of memory\n");
  3185. return -ENOMEM;
  3186. }
  3187. SET_NETDEV_DEV(netdev, &intf->dev);
  3188. tp = netdev_priv(netdev);
  3189. tp->msg_enable = 0x7FFF;
  3190. tp->udev = udev;
  3191. tp->netdev = netdev;
  3192. tp->intf = intf;
  3193. r8152b_get_version(tp);
  3194. ret = rtl_ops_init(tp);
  3195. if (ret)
  3196. goto out;
  3197. mutex_init(&tp->control);
  3198. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3199. netdev->netdev_ops = &rtl8152_netdev_ops;
  3200. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3201. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3202. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3203. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3204. NETIF_F_HW_VLAN_CTAG_TX;
  3205. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3206. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3207. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3208. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3209. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3210. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3211. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3212. netdev->ethtool_ops = &ops;
  3213. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3214. tp->mii.dev = netdev;
  3215. tp->mii.mdio_read = read_mii_word;
  3216. tp->mii.mdio_write = write_mii_word;
  3217. tp->mii.phy_id_mask = 0x3f;
  3218. tp->mii.reg_num_mask = 0x1f;
  3219. tp->mii.phy_id = R8152_PHY_ID;
  3220. switch (udev->speed) {
  3221. case USB_SPEED_SUPER:
  3222. tp->coalesce = COALESCE_SUPER;
  3223. break;
  3224. case USB_SPEED_HIGH:
  3225. tp->coalesce = COALESCE_HIGH;
  3226. break;
  3227. default:
  3228. tp->coalesce = COALESCE_SLOW;
  3229. break;
  3230. }
  3231. intf->needs_remote_wakeup = 1;
  3232. tp->rtl_ops.init(tp);
  3233. set_ethernet_addr(tp);
  3234. usb_set_intfdata(intf, tp);
  3235. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3236. ret = register_netdev(netdev);
  3237. if (ret != 0) {
  3238. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3239. goto out1;
  3240. }
  3241. tp->saved_wolopts = __rtl_get_wol(tp);
  3242. if (tp->saved_wolopts)
  3243. device_set_wakeup_enable(&udev->dev, true);
  3244. else
  3245. device_set_wakeup_enable(&udev->dev, false);
  3246. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3247. return 0;
  3248. out1:
  3249. netif_napi_del(&tp->napi);
  3250. usb_set_intfdata(intf, NULL);
  3251. out:
  3252. free_netdev(netdev);
  3253. return ret;
  3254. }
  3255. static void rtl8152_disconnect(struct usb_interface *intf)
  3256. {
  3257. struct r8152 *tp = usb_get_intfdata(intf);
  3258. usb_set_intfdata(intf, NULL);
  3259. if (tp) {
  3260. struct usb_device *udev = tp->udev;
  3261. if (udev->state == USB_STATE_NOTATTACHED)
  3262. set_bit(RTL8152_UNPLUG, &tp->flags);
  3263. netif_napi_del(&tp->napi);
  3264. unregister_netdev(tp->netdev);
  3265. tp->rtl_ops.unload(tp);
  3266. free_netdev(tp->netdev);
  3267. }
  3268. }
  3269. #define REALTEK_USB_DEVICE(vend, prod) \
  3270. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3271. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3272. .idVendor = (vend), \
  3273. .idProduct = (prod), \
  3274. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3275. }, \
  3276. { \
  3277. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3278. USB_DEVICE_ID_MATCH_DEVICE, \
  3279. .idVendor = (vend), \
  3280. .idProduct = (prod), \
  3281. .bInterfaceClass = USB_CLASS_COMM, \
  3282. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3283. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3284. /* table of devices that work with this driver */
  3285. static struct usb_device_id rtl8152_table[] = {
  3286. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3287. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3288. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3289. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3290. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3291. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3292. {}
  3293. };
  3294. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3295. static struct usb_driver rtl8152_driver = {
  3296. .name = MODULENAME,
  3297. .id_table = rtl8152_table,
  3298. .probe = rtl8152_probe,
  3299. .disconnect = rtl8152_disconnect,
  3300. .suspend = rtl8152_suspend,
  3301. .resume = rtl8152_resume,
  3302. .reset_resume = rtl8152_resume,
  3303. .supports_autosuspend = 1,
  3304. .disable_hub_initiated_lpm = 1,
  3305. };
  3306. module_usb_driver(rtl8152_driver);
  3307. MODULE_AUTHOR(DRIVER_AUTHOR);
  3308. MODULE_DESCRIPTION(DRIVER_DESC);
  3309. MODULE_LICENSE("GPL");