net2280.h 11 KB

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  1. /*
  2. * NetChip 2280 high/full speed USB device controller.
  3. * Unlike many such controllers, this one talks PCI.
  4. */
  5. /*
  6. * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
  7. * Copyright (C) 2003 David Brownell
  8. * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #include <linux/usb/net2280.h>
  16. #include <linux/usb/usb338x.h>
  17. /*-------------------------------------------------------------------------*/
  18. #ifdef __KERNEL__
  19. /* indexed registers [11.10] are accessed indirectly
  20. * caller must own the device lock.
  21. */
  22. static inline u32 get_idx_reg(struct net2280_regs __iomem *regs, u32 index)
  23. {
  24. writel(index, &regs->idxaddr);
  25. /* NOTE: synchs device/cpu memory views */
  26. return readl(&regs->idxdata);
  27. }
  28. static inline void
  29. set_idx_reg(struct net2280_regs __iomem *regs, u32 index, u32 value)
  30. {
  31. writel(index, &regs->idxaddr);
  32. writel(value, &regs->idxdata);
  33. /* posted, may not be visible yet */
  34. }
  35. #endif /* __KERNEL__ */
  36. #define PCI_VENDOR_ID_PLX_LEGACY 0x17cc
  37. #define PLX_LEGACY BIT(0)
  38. #define PLX_2280 BIT(1)
  39. #define PLX_SUPERSPEED BIT(2)
  40. #define REG_DIAG 0x0
  41. #define RETRY_COUNTER 16
  42. #define FORCE_PCI_SERR 11
  43. #define FORCE_PCI_INTERRUPT 10
  44. #define FORCE_USB_INTERRUPT 9
  45. #define FORCE_CPU_INTERRUPT 8
  46. #define ILLEGAL_BYTE_ENABLES 5
  47. #define FAST_TIMES 4
  48. #define FORCE_RECEIVE_ERROR 2
  49. #define FORCE_TRANSMIT_CRC_ERROR 0
  50. #define REG_FRAME 0x02 /* from last sof */
  51. #define REG_CHIPREV 0x03 /* in bcd */
  52. #define REG_HS_NAK_RATE 0x0a /* NAK per N uframes */
  53. #define CHIPREV_1 0x0100
  54. #define CHIPREV_1A 0x0110
  55. /* DEFECT 7374 */
  56. #define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS 200
  57. #define DEFECT_7374_PROCESSOR_WAIT_TIME 10
  58. /* ep0 max packet size */
  59. #define EP0_SS_MAX_PACKET_SIZE 0x200
  60. #define EP0_HS_MAX_PACKET_SIZE 0x40
  61. #ifdef __KERNEL__
  62. /*-------------------------------------------------------------------------*/
  63. /* [8.3] for scatter/gather i/o
  64. * use struct net2280_dma_regs bitfields
  65. */
  66. struct net2280_dma {
  67. __le32 dmacount;
  68. __le32 dmaaddr; /* the buffer */
  69. __le32 dmadesc; /* next dma descriptor */
  70. __le32 _reserved;
  71. } __aligned(16);
  72. /*-------------------------------------------------------------------------*/
  73. /* DRIVER DATA STRUCTURES and UTILITIES */
  74. struct net2280_ep {
  75. struct usb_ep ep;
  76. struct net2280_ep_regs __iomem *cfg;
  77. struct net2280_ep_regs __iomem *regs;
  78. struct net2280_dma_regs __iomem *dma;
  79. struct net2280_dma *dummy;
  80. struct usb338x_fifo_regs __iomem *fiforegs;
  81. dma_addr_t td_dma; /* of dummy */
  82. struct net2280 *dev;
  83. unsigned long irqs;
  84. /* analogous to a host-side qh */
  85. struct list_head queue;
  86. const struct usb_endpoint_descriptor *desc;
  87. unsigned num : 8,
  88. fifo_size : 12,
  89. in_fifo_validate : 1,
  90. out_overflow : 1,
  91. stopped : 1,
  92. wedged : 1,
  93. is_in : 1,
  94. is_iso : 1,
  95. responded : 1;
  96. };
  97. static inline void allow_status(struct net2280_ep *ep)
  98. {
  99. /* ep0 only */
  100. writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
  101. BIT(CLEAR_NAK_OUT_PACKETS) |
  102. BIT(CLEAR_NAK_OUT_PACKETS_MODE),
  103. &ep->regs->ep_rsp);
  104. ep->stopped = 1;
  105. }
  106. static inline void allow_status_338x(struct net2280_ep *ep)
  107. {
  108. /*
  109. * Control Status Phase Handshake was set by the chip when the setup
  110. * packet arrived. While set, the chip automatically NAKs the host's
  111. * Status Phase tokens.
  112. */
  113. writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
  114. ep->stopped = 1;
  115. /* TD 9.9 Halt Endpoint test. TD 9.22 set feature test. */
  116. ep->responded = 0;
  117. }
  118. struct net2280_request {
  119. struct usb_request req;
  120. struct net2280_dma *td;
  121. dma_addr_t td_dma;
  122. struct list_head queue;
  123. unsigned mapped : 1,
  124. valid : 1;
  125. };
  126. struct net2280 {
  127. /* each pci device provides one gadget, several endpoints */
  128. struct usb_gadget gadget;
  129. spinlock_t lock;
  130. struct net2280_ep ep[9];
  131. struct usb_gadget_driver *driver;
  132. unsigned enabled : 1,
  133. protocol_stall : 1,
  134. softconnect : 1,
  135. got_irq : 1,
  136. region:1,
  137. u1_enable:1,
  138. u2_enable:1,
  139. ltm_enable:1,
  140. wakeup_enable:1,
  141. addressed_state:1,
  142. bug7734_patched:1;
  143. u16 chiprev;
  144. int enhanced_mode;
  145. int n_ep;
  146. kernel_ulong_t quirks;
  147. /* pci state used to access those endpoints */
  148. struct pci_dev *pdev;
  149. struct net2280_regs __iomem *regs;
  150. struct net2280_usb_regs __iomem *usb;
  151. struct usb338x_usb_ext_regs __iomem *usb_ext;
  152. struct net2280_pci_regs __iomem *pci;
  153. struct net2280_dma_regs __iomem *dma;
  154. struct net2280_dep_regs __iomem *dep;
  155. struct net2280_ep_regs __iomem *epregs;
  156. struct usb338x_fifo_regs __iomem *fiforegs;
  157. struct usb338x_ll_regs __iomem *llregs;
  158. struct usb338x_ll_lfps_regs __iomem *ll_lfps_regs;
  159. struct usb338x_ll_tsn_regs __iomem *ll_tsn_regs;
  160. struct usb338x_ll_chi_regs __iomem *ll_chicken_reg;
  161. struct usb338x_pl_regs __iomem *plregs;
  162. struct pci_pool *requests;
  163. /* statistics...*/
  164. };
  165. static inline void set_halt(struct net2280_ep *ep)
  166. {
  167. /* ep0 and bulk/intr endpoints */
  168. writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
  169. /* set NAK_OUT for erratum 0114 */
  170. ((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) |
  171. BIT(SET_ENDPOINT_HALT),
  172. &ep->regs->ep_rsp);
  173. }
  174. static inline void clear_halt(struct net2280_ep *ep)
  175. {
  176. /* ep0 and bulk/intr endpoints */
  177. writel(BIT(CLEAR_ENDPOINT_HALT) |
  178. BIT(CLEAR_ENDPOINT_TOGGLE) |
  179. /*
  180. * unless the gadget driver left a short packet in the
  181. * fifo, this reverses the erratum 0114 workaround.
  182. */
  183. ((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS),
  184. &ep->regs->ep_rsp);
  185. }
  186. /*
  187. * FSM value for Defect 7374 (U1U2 Test) is managed in
  188. * chip's SCRATCH register:
  189. */
  190. #define DEFECT7374_FSM_FIELD 28
  191. /* Waiting for Control Read:
  192. * - A transition to this state indicates a fresh USB connection,
  193. * before the first Setup Packet. The connection speed is not
  194. * known. Firmware is waiting for the first Control Read.
  195. * - Starting state: This state can be thought of as the FSM's typical
  196. * starting state.
  197. * - Tip: Upon the first SS Control Read the FSM never
  198. * returns to this state.
  199. */
  200. #define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD)
  201. /* Non-SS Control Read:
  202. * - A transition to this state indicates detection of the first HS
  203. * or FS Control Read.
  204. * - Tip: Upon the first SS Control Read the FSM never
  205. * returns to this state.
  206. */
  207. #define DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
  208. /* SS Control Read:
  209. * - A transition to this state indicates detection of the
  210. * first SS Control Read.
  211. * - This state indicates workaround completion. Workarounds no longer
  212. * need to be applied (as long as the chip remains powered up).
  213. * - Tip: Once in this state the FSM state does not change (until
  214. * the chip's power is lost and restored).
  215. * - This can be thought of as the final state of the FSM;
  216. * the FSM 'locks-up' in this state until the chip loses power.
  217. */
  218. #define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
  219. #ifdef USE_RDK_LEDS
  220. static inline void net2280_led_init(struct net2280 *dev)
  221. {
  222. /* LED3 (green) is on during USB activity. note erratum 0113. */
  223. writel(BIT(GPIO3_LED_SELECT) |
  224. BIT(GPIO3_OUTPUT_ENABLE) |
  225. BIT(GPIO2_OUTPUT_ENABLE) |
  226. BIT(GPIO1_OUTPUT_ENABLE) |
  227. BIT(GPIO0_OUTPUT_ENABLE),
  228. &dev->regs->gpioctl);
  229. }
  230. /* indicate speed with bi-color LED 0/1 */
  231. static inline
  232. void net2280_led_speed(struct net2280 *dev, enum usb_device_speed speed)
  233. {
  234. u32 val = readl(&dev->regs->gpioctl);
  235. switch (speed) {
  236. case USB_SPEED_SUPER: /* green + red */
  237. val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA);
  238. break;
  239. case USB_SPEED_HIGH: /* green */
  240. val &= ~BIT(GPIO0_DATA);
  241. val |= BIT(GPIO1_DATA);
  242. break;
  243. case USB_SPEED_FULL: /* red */
  244. val &= ~BIT(GPIO1_DATA);
  245. val |= BIT(GPIO0_DATA);
  246. break;
  247. default: /* (off/black) */
  248. val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA));
  249. break;
  250. }
  251. writel(val, &dev->regs->gpioctl);
  252. }
  253. /* indicate power with LED 2 */
  254. static inline void net2280_led_active(struct net2280 *dev, int is_active)
  255. {
  256. u32 val = readl(&dev->regs->gpioctl);
  257. /* FIXME this LED never seems to turn on.*/
  258. if (is_active)
  259. val |= GPIO2_DATA;
  260. else
  261. val &= ~GPIO2_DATA;
  262. writel(val, &dev->regs->gpioctl);
  263. }
  264. static inline void net2280_led_shutdown(struct net2280 *dev)
  265. {
  266. /* turn off all four GPIO*_DATA bits */
  267. writel(readl(&dev->regs->gpioctl) & ~0x0f,
  268. &dev->regs->gpioctl);
  269. }
  270. #else
  271. #define net2280_led_init(dev) do { } while (0)
  272. #define net2280_led_speed(dev, speed) do { } while (0)
  273. #define net2280_led_shutdown(dev) do { } while (0)
  274. #endif
  275. /*-------------------------------------------------------------------------*/
  276. #define ep_dbg(ndev, fmt, args...) \
  277. dev_dbg((&((ndev)->pdev->dev)), fmt, ##args)
  278. #define ep_vdbg(ndev, fmt, args...) \
  279. dev_vdbg((&((ndev)->pdev->dev)), fmt, ##args)
  280. #define ep_info(ndev, fmt, args...) \
  281. dev_info((&((ndev)->pdev->dev)), fmt, ##args)
  282. #define ep_warn(ndev, fmt, args...) \
  283. dev_warn((&((ndev)->pdev->dev)), fmt, ##args)
  284. #define ep_err(ndev, fmt, args...) \
  285. dev_err((&((ndev)->pdev->dev)), fmt, ##args)
  286. /*-------------------------------------------------------------------------*/
  287. static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
  288. {
  289. if (ep->dev->pdev->vendor == 0x17cc)
  290. writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
  291. else{
  292. u32 tmp = readl(&ep->cfg->ep_cfg) &
  293. (~(0x07 << EP_FIFO_BYTE_COUNT));
  294. writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
  295. }
  296. }
  297. static inline void start_out_naking(struct net2280_ep *ep)
  298. {
  299. /* NOTE: hardware races lurk here, and PING protocol issues */
  300. writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
  301. /* synch with device */
  302. readl(&ep->regs->ep_rsp);
  303. }
  304. static inline void stop_out_naking(struct net2280_ep *ep)
  305. {
  306. u32 tmp;
  307. tmp = readl(&ep->regs->ep_stat);
  308. if ((tmp & BIT(NAK_OUT_PACKETS)) != 0)
  309. writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
  310. }
  311. static inline void set_max_speed(struct net2280_ep *ep, u32 max)
  312. {
  313. u32 reg;
  314. static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
  315. 0x50, 0x20, 0x70, 0x40, 0x90 };
  316. if (ep->dev->enhanced_mode)
  317. reg = ep_enhanced[ep->num];
  318. else{
  319. reg = (ep->num + 1) * 0x10;
  320. if (ep->dev->gadget.speed != USB_SPEED_HIGH)
  321. reg += 1;
  322. }
  323. set_idx_reg(ep->dev->regs, reg, max);
  324. }
  325. #endif /* __KERNEL__ */