kfd_device.c 15 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. */
  22. #include <linux/amd-iommu.h>
  23. #include <linux/bsearch.h>
  24. #include <linux/pci.h>
  25. #include <linux/slab.h>
  26. #include "kfd_priv.h"
  27. #include "kfd_device_queue_manager.h"
  28. #include "kfd_pm4_headers.h"
  29. #define MQD_SIZE_ALIGNED 768
  30. static const struct kfd_device_info kaveri_device_info = {
  31. .asic_family = CHIP_KAVERI,
  32. .max_pasid_bits = 16,
  33. /* max num of queues for KV.TODO should be a dynamic value */
  34. .max_no_of_hqd = 24,
  35. .ih_ring_entry_size = 4 * sizeof(uint32_t),
  36. .event_interrupt_class = &event_interrupt_class_cik,
  37. .num_of_watch_points = 4,
  38. .mqd_size_aligned = MQD_SIZE_ALIGNED
  39. };
  40. static const struct kfd_device_info carrizo_device_info = {
  41. .asic_family = CHIP_CARRIZO,
  42. .max_pasid_bits = 16,
  43. /* max num of queues for CZ.TODO should be a dynamic value */
  44. .max_no_of_hqd = 24,
  45. .ih_ring_entry_size = 4 * sizeof(uint32_t),
  46. .event_interrupt_class = &event_interrupt_class_cik,
  47. .num_of_watch_points = 4,
  48. .mqd_size_aligned = MQD_SIZE_ALIGNED
  49. };
  50. struct kfd_deviceid {
  51. unsigned short did;
  52. const struct kfd_device_info *device_info;
  53. };
  54. /* Please keep this sorted by increasing device id. */
  55. static const struct kfd_deviceid supported_devices[] = {
  56. { 0x1304, &kaveri_device_info }, /* Kaveri */
  57. { 0x1305, &kaveri_device_info }, /* Kaveri */
  58. { 0x1306, &kaveri_device_info }, /* Kaveri */
  59. { 0x1307, &kaveri_device_info }, /* Kaveri */
  60. { 0x1309, &kaveri_device_info }, /* Kaveri */
  61. { 0x130A, &kaveri_device_info }, /* Kaveri */
  62. { 0x130B, &kaveri_device_info }, /* Kaveri */
  63. { 0x130C, &kaveri_device_info }, /* Kaveri */
  64. { 0x130D, &kaveri_device_info }, /* Kaveri */
  65. { 0x130E, &kaveri_device_info }, /* Kaveri */
  66. { 0x130F, &kaveri_device_info }, /* Kaveri */
  67. { 0x1310, &kaveri_device_info }, /* Kaveri */
  68. { 0x1311, &kaveri_device_info }, /* Kaveri */
  69. { 0x1312, &kaveri_device_info }, /* Kaveri */
  70. { 0x1313, &kaveri_device_info }, /* Kaveri */
  71. { 0x1315, &kaveri_device_info }, /* Kaveri */
  72. { 0x1316, &kaveri_device_info }, /* Kaveri */
  73. { 0x1317, &kaveri_device_info }, /* Kaveri */
  74. { 0x1318, &kaveri_device_info }, /* Kaveri */
  75. { 0x131B, &kaveri_device_info }, /* Kaveri */
  76. { 0x131C, &kaveri_device_info }, /* Kaveri */
  77. { 0x131D, &kaveri_device_info } /* Kaveri */
  78. };
  79. static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  80. unsigned int chunk_size);
  81. static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
  82. static const struct kfd_device_info *lookup_device_info(unsigned short did)
  83. {
  84. size_t i;
  85. for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
  86. if (supported_devices[i].did == did) {
  87. BUG_ON(supported_devices[i].device_info == NULL);
  88. return supported_devices[i].device_info;
  89. }
  90. }
  91. return NULL;
  92. }
  93. struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
  94. struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
  95. {
  96. struct kfd_dev *kfd;
  97. const struct kfd_device_info *device_info =
  98. lookup_device_info(pdev->device);
  99. if (!device_info)
  100. return NULL;
  101. kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
  102. if (!kfd)
  103. return NULL;
  104. kfd->kgd = kgd;
  105. kfd->device_info = device_info;
  106. kfd->pdev = pdev;
  107. kfd->init_complete = false;
  108. kfd->kfd2kgd = f2g;
  109. mutex_init(&kfd->doorbell_mutex);
  110. memset(&kfd->doorbell_available_index, 0,
  111. sizeof(kfd->doorbell_available_index));
  112. return kfd;
  113. }
  114. static bool device_iommu_pasid_init(struct kfd_dev *kfd)
  115. {
  116. const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP |
  117. AMD_IOMMU_DEVICE_FLAG_PRI_SUP |
  118. AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
  119. struct amd_iommu_device_info iommu_info;
  120. unsigned int pasid_limit;
  121. int err;
  122. err = amd_iommu_device_info(kfd->pdev, &iommu_info);
  123. if (err < 0) {
  124. dev_err(kfd_device,
  125. "error getting iommu info. is the iommu enabled?\n");
  126. return false;
  127. }
  128. if ((iommu_info.flags & required_iommu_flags) != required_iommu_flags) {
  129. dev_err(kfd_device, "error required iommu flags ats(%i), pri(%i), pasid(%i)\n",
  130. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0,
  131. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0,
  132. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) != 0);
  133. return false;
  134. }
  135. pasid_limit = min_t(unsigned int,
  136. (unsigned int)1 << kfd->device_info->max_pasid_bits,
  137. iommu_info.max_pasids);
  138. /*
  139. * last pasid is used for kernel queues doorbells
  140. * in the future the last pasid might be used for a kernel thread.
  141. */
  142. pasid_limit = min_t(unsigned int,
  143. pasid_limit,
  144. kfd->doorbell_process_limit - 1);
  145. err = amd_iommu_init_device(kfd->pdev, pasid_limit);
  146. if (err < 0) {
  147. dev_err(kfd_device, "error initializing iommu device\n");
  148. return false;
  149. }
  150. if (!kfd_set_pasid_limit(pasid_limit)) {
  151. dev_err(kfd_device, "error setting pasid limit\n");
  152. amd_iommu_free_device(kfd->pdev);
  153. return false;
  154. }
  155. return true;
  156. }
  157. static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid)
  158. {
  159. struct kfd_dev *dev = kfd_device_by_pci_dev(pdev);
  160. if (dev)
  161. kfd_unbind_process_from_device(dev, pasid);
  162. }
  163. /*
  164. * This function called by IOMMU driver on PPR failure
  165. */
  166. static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid,
  167. unsigned long address, u16 flags)
  168. {
  169. struct kfd_dev *dev;
  170. dev_warn(kfd_device,
  171. "Invalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%X",
  172. PCI_BUS_NUM(pdev->devfn),
  173. PCI_SLOT(pdev->devfn),
  174. PCI_FUNC(pdev->devfn),
  175. pasid,
  176. address,
  177. flags);
  178. dev = kfd_device_by_pci_dev(pdev);
  179. BUG_ON(dev == NULL);
  180. kfd_signal_iommu_event(dev, pasid, address,
  181. flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC);
  182. return AMD_IOMMU_INV_PRI_RSP_INVALID;
  183. }
  184. bool kgd2kfd_device_init(struct kfd_dev *kfd,
  185. const struct kgd2kfd_shared_resources *gpu_resources)
  186. {
  187. unsigned int size;
  188. kfd->shared_resources = *gpu_resources;
  189. /* calculate max size of mqds needed for queues */
  190. size = max_num_of_queues_per_device *
  191. kfd->device_info->mqd_size_aligned;
  192. /*
  193. * calculate max size of runlist packet.
  194. * There can be only 2 packets at once
  195. */
  196. size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_map_process) +
  197. max_num_of_queues_per_device *
  198. sizeof(struct pm4_map_queues) + sizeof(struct pm4_runlist)) * 2;
  199. /* Add size of HIQ & DIQ */
  200. size += KFD_KERNEL_QUEUE_SIZE * 2;
  201. /* add another 512KB for all other allocations on gart (HPD, fences) */
  202. size += 512 * 1024;
  203. if (kfd->kfd2kgd->init_gtt_mem_allocation(
  204. kfd->kgd, size, &kfd->gtt_mem,
  205. &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){
  206. dev_err(kfd_device,
  207. "Could not allocate %d bytes for device (%x:%x)\n",
  208. size, kfd->pdev->vendor, kfd->pdev->device);
  209. goto out;
  210. }
  211. dev_info(kfd_device,
  212. "Allocated %d bytes on gart for device(%x:%x)\n",
  213. size, kfd->pdev->vendor, kfd->pdev->device);
  214. /* Initialize GTT sa with 512 byte chunk size */
  215. if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
  216. dev_err(kfd_device,
  217. "Error initializing gtt sub-allocator\n");
  218. goto kfd_gtt_sa_init_error;
  219. }
  220. kfd_doorbell_init(kfd);
  221. if (kfd_topology_add_device(kfd) != 0) {
  222. dev_err(kfd_device,
  223. "Error adding device (%x:%x) to topology\n",
  224. kfd->pdev->vendor, kfd->pdev->device);
  225. goto kfd_topology_add_device_error;
  226. }
  227. if (kfd_interrupt_init(kfd)) {
  228. dev_err(kfd_device,
  229. "Error initializing interrupts for device (%x:%x)\n",
  230. kfd->pdev->vendor, kfd->pdev->device);
  231. goto kfd_interrupt_error;
  232. }
  233. if (!device_iommu_pasid_init(kfd)) {
  234. dev_err(kfd_device,
  235. "Error initializing iommuv2 for device (%x:%x)\n",
  236. kfd->pdev->vendor, kfd->pdev->device);
  237. goto device_iommu_pasid_error;
  238. }
  239. amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
  240. iommu_pasid_shutdown_callback);
  241. amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
  242. kfd->dqm = device_queue_manager_init(kfd);
  243. if (!kfd->dqm) {
  244. dev_err(kfd_device,
  245. "Error initializing queue manager for device (%x:%x)\n",
  246. kfd->pdev->vendor, kfd->pdev->device);
  247. goto device_queue_manager_error;
  248. }
  249. if (kfd->dqm->ops.start(kfd->dqm) != 0) {
  250. dev_err(kfd_device,
  251. "Error starting queuen manager for device (%x:%x)\n",
  252. kfd->pdev->vendor, kfd->pdev->device);
  253. goto dqm_start_error;
  254. }
  255. kfd->dbgmgr = NULL;
  256. kfd->init_complete = true;
  257. dev_info(kfd_device, "added device (%x:%x)\n", kfd->pdev->vendor,
  258. kfd->pdev->device);
  259. pr_debug("kfd: Starting kfd with the following scheduling policy %d\n",
  260. sched_policy);
  261. goto out;
  262. dqm_start_error:
  263. device_queue_manager_uninit(kfd->dqm);
  264. device_queue_manager_error:
  265. amd_iommu_free_device(kfd->pdev);
  266. device_iommu_pasid_error:
  267. kfd_interrupt_exit(kfd);
  268. kfd_interrupt_error:
  269. kfd_topology_remove_device(kfd);
  270. kfd_topology_add_device_error:
  271. kfd_gtt_sa_fini(kfd);
  272. kfd_gtt_sa_init_error:
  273. kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
  274. dev_err(kfd_device,
  275. "device (%x:%x) NOT added due to errors\n",
  276. kfd->pdev->vendor, kfd->pdev->device);
  277. out:
  278. return kfd->init_complete;
  279. }
  280. void kgd2kfd_device_exit(struct kfd_dev *kfd)
  281. {
  282. if (kfd->init_complete) {
  283. device_queue_manager_uninit(kfd->dqm);
  284. amd_iommu_free_device(kfd->pdev);
  285. kfd_interrupt_exit(kfd);
  286. kfd_topology_remove_device(kfd);
  287. kfd_gtt_sa_fini(kfd);
  288. kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
  289. }
  290. kfree(kfd);
  291. }
  292. void kgd2kfd_suspend(struct kfd_dev *kfd)
  293. {
  294. BUG_ON(kfd == NULL);
  295. if (kfd->init_complete) {
  296. kfd->dqm->ops.stop(kfd->dqm);
  297. amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
  298. amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
  299. amd_iommu_free_device(kfd->pdev);
  300. }
  301. }
  302. int kgd2kfd_resume(struct kfd_dev *kfd)
  303. {
  304. unsigned int pasid_limit;
  305. int err;
  306. BUG_ON(kfd == NULL);
  307. pasid_limit = kfd_get_pasid_limit();
  308. if (kfd->init_complete) {
  309. err = amd_iommu_init_device(kfd->pdev, pasid_limit);
  310. if (err < 0)
  311. return -ENXIO;
  312. amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
  313. iommu_pasid_shutdown_callback);
  314. amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
  315. kfd->dqm->ops.start(kfd->dqm);
  316. }
  317. return 0;
  318. }
  319. /* This is called directly from KGD at ISR. */
  320. void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
  321. {
  322. if (!kfd->init_complete)
  323. return;
  324. spin_lock(&kfd->interrupt_lock);
  325. if (kfd->interrupts_active
  326. && interrupt_is_wanted(kfd, ih_ring_entry)
  327. && enqueue_ih_ring_entry(kfd, ih_ring_entry))
  328. schedule_work(&kfd->interrupt_work);
  329. spin_unlock(&kfd->interrupt_lock);
  330. }
  331. static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  332. unsigned int chunk_size)
  333. {
  334. unsigned int num_of_bits;
  335. BUG_ON(!kfd);
  336. BUG_ON(!kfd->gtt_mem);
  337. BUG_ON(buf_size < chunk_size);
  338. BUG_ON(buf_size == 0);
  339. BUG_ON(chunk_size == 0);
  340. kfd->gtt_sa_chunk_size = chunk_size;
  341. kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
  342. num_of_bits = kfd->gtt_sa_num_of_chunks / BITS_PER_BYTE;
  343. BUG_ON(num_of_bits == 0);
  344. kfd->gtt_sa_bitmap = kzalloc(num_of_bits, GFP_KERNEL);
  345. if (!kfd->gtt_sa_bitmap)
  346. return -ENOMEM;
  347. pr_debug("kfd: gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
  348. kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
  349. mutex_init(&kfd->gtt_sa_lock);
  350. return 0;
  351. }
  352. static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
  353. {
  354. mutex_destroy(&kfd->gtt_sa_lock);
  355. kfree(kfd->gtt_sa_bitmap);
  356. }
  357. static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
  358. unsigned int bit_num,
  359. unsigned int chunk_size)
  360. {
  361. return start_addr + bit_num * chunk_size;
  362. }
  363. static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
  364. unsigned int bit_num,
  365. unsigned int chunk_size)
  366. {
  367. return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
  368. }
  369. int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
  370. struct kfd_mem_obj **mem_obj)
  371. {
  372. unsigned int found, start_search, cur_size;
  373. BUG_ON(!kfd);
  374. if (size == 0)
  375. return -EINVAL;
  376. if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
  377. return -ENOMEM;
  378. *mem_obj = kmalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
  379. if ((*mem_obj) == NULL)
  380. return -ENOMEM;
  381. pr_debug("kfd: allocated mem_obj = %p for size = %d\n", *mem_obj, size);
  382. start_search = 0;
  383. mutex_lock(&kfd->gtt_sa_lock);
  384. kfd_gtt_restart_search:
  385. /* Find the first chunk that is free */
  386. found = find_next_zero_bit(kfd->gtt_sa_bitmap,
  387. kfd->gtt_sa_num_of_chunks,
  388. start_search);
  389. pr_debug("kfd: found = %d\n", found);
  390. /* If there wasn't any free chunk, bail out */
  391. if (found == kfd->gtt_sa_num_of_chunks)
  392. goto kfd_gtt_no_free_chunk;
  393. /* Update fields of mem_obj */
  394. (*mem_obj)->range_start = found;
  395. (*mem_obj)->range_end = found;
  396. (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
  397. kfd->gtt_start_gpu_addr,
  398. found,
  399. kfd->gtt_sa_chunk_size);
  400. (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
  401. kfd->gtt_start_cpu_ptr,
  402. found,
  403. kfd->gtt_sa_chunk_size);
  404. pr_debug("kfd: gpu_addr = %p, cpu_addr = %p\n",
  405. (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
  406. /* If we need only one chunk, mark it as allocated and get out */
  407. if (size <= kfd->gtt_sa_chunk_size) {
  408. pr_debug("kfd: single bit\n");
  409. set_bit(found, kfd->gtt_sa_bitmap);
  410. goto kfd_gtt_out;
  411. }
  412. /* Otherwise, try to see if we have enough contiguous chunks */
  413. cur_size = size - kfd->gtt_sa_chunk_size;
  414. do {
  415. (*mem_obj)->range_end =
  416. find_next_zero_bit(kfd->gtt_sa_bitmap,
  417. kfd->gtt_sa_num_of_chunks, ++found);
  418. /*
  419. * If next free chunk is not contiguous than we need to
  420. * restart our search from the last free chunk we found (which
  421. * wasn't contiguous to the previous ones
  422. */
  423. if ((*mem_obj)->range_end != found) {
  424. start_search = found;
  425. goto kfd_gtt_restart_search;
  426. }
  427. /*
  428. * If we reached end of buffer, bail out with error
  429. */
  430. if (found == kfd->gtt_sa_num_of_chunks)
  431. goto kfd_gtt_no_free_chunk;
  432. /* Check if we don't need another chunk */
  433. if (cur_size <= kfd->gtt_sa_chunk_size)
  434. cur_size = 0;
  435. else
  436. cur_size -= kfd->gtt_sa_chunk_size;
  437. } while (cur_size > 0);
  438. pr_debug("kfd: range_start = %d, range_end = %d\n",
  439. (*mem_obj)->range_start, (*mem_obj)->range_end);
  440. /* Mark the chunks as allocated */
  441. for (found = (*mem_obj)->range_start;
  442. found <= (*mem_obj)->range_end;
  443. found++)
  444. set_bit(found, kfd->gtt_sa_bitmap);
  445. kfd_gtt_out:
  446. mutex_unlock(&kfd->gtt_sa_lock);
  447. return 0;
  448. kfd_gtt_no_free_chunk:
  449. pr_debug("kfd: allocation failed with mem_obj = %p\n", mem_obj);
  450. mutex_unlock(&kfd->gtt_sa_lock);
  451. kfree(mem_obj);
  452. return -ENOMEM;
  453. }
  454. int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
  455. {
  456. unsigned int bit;
  457. BUG_ON(!kfd);
  458. /* Act like kfree when trying to free a NULL object */
  459. if (!mem_obj)
  460. return 0;
  461. pr_debug("kfd: free mem_obj = %p, range_start = %d, range_end = %d\n",
  462. mem_obj, mem_obj->range_start, mem_obj->range_end);
  463. mutex_lock(&kfd->gtt_sa_lock);
  464. /* Mark the chunks as free */
  465. for (bit = mem_obj->range_start;
  466. bit <= mem_obj->range_end;
  467. bit++)
  468. clear_bit(bit, kfd->gtt_sa_bitmap);
  469. mutex_unlock(&kfd->gtt_sa_lock);
  470. kfree(mem_obj);
  471. return 0;
  472. }