| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111 |
- /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * Based on "omap4.dtsi"
- */
- #include "dra7.dtsi"
- / {
- compatible = "ti,dra722", "ti,dra72", "ti,dra7";
- aliases {
- rproc0 = &ipu1;
- rproc1 = &ipu2;
- rproc2 = &dsp1;
- };
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupt-parent = <&wakeupgen>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- };
- ocp {
- cal: cal@4845b000 {
- compatible = "ti,dra72-cal";
- ti,hwmods = "cal";
- reg = <0x4845B000 0x400>,
- <0x4845B800 0x40>,
- <0x4845B900 0x40>;
- reg-names = "cal_top",
- "cal_rx_core0",
- "cal_rx_core1";
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- syscon-camerrx = <&scm_conf 0xE94>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- csi2_0: port@0 {
- reg = <0>;
- };
- csi2_1: port@1 {
- reg = <1>;
- };
- };
- };
- };
- };
- &scm {
- dra72_vip_mux: pinmux@4a002e8c {
- compatible = "pinctrl-single";
- reg = <0xe8c 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7f>;
- };
- };
- &dss {
- reg = <0x58000000 0x80>,
- <0x58004054 0x4>,
- <0x58004300 0x20>;
- reg-names = "dss", "pll1_clkctrl", "pll1";
- clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
- <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
- clock-names = "fck", "video1_clk";
- };
- &mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- ti,mbox-tx = <6 2 2>;
- ti,mbox-rx = <4 2 2>;
- status = "disabled";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- ti,mbox-tx = <5 2 2>;
- ti,mbox-rx = <1 2 2>;
- status = "disabled";
- };
- };
- &mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- ti,mbox-tx = <6 2 2>;
- ti,mbox-rx = <4 2 2>;
- status = "disabled";
- };
- };
- &pcie1_rc {
- compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
- };
- &pcie1_ep {
- compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
- };
- &pcie2_rc {
- compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
- };
|