pci-me.c 12 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2003-2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/kernel.h>
  19. #include <linux/device.h>
  20. #include <linux/fs.h>
  21. #include <linux/errno.h>
  22. #include <linux/types.h>
  23. #include <linux/fcntl.h>
  24. #include <linux/pci.h>
  25. #include <linux/poll.h>
  26. #include <linux/ioctl.h>
  27. #include <linux/cdev.h>
  28. #include <linux/sched.h>
  29. #include <linux/uuid.h>
  30. #include <linux/compat.h>
  31. #include <linux/jiffies.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/mei.h>
  35. #include "mei_dev.h"
  36. #include "client.h"
  37. #include "hw-me-regs.h"
  38. #include "hw-me.h"
  39. /* mei_pci_tbl - PCI Device ID Table */
  40. static const struct pci_device_id mei_me_pci_tbl[] = {
  41. {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
  42. {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
  43. {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
  44. {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
  45. {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
  46. {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
  47. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
  48. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
  49. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
  50. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
  51. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
  52. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
  53. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
  54. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
  55. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
  56. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
  57. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
  58. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
  59. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
  60. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
  61. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
  62. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
  63. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
  64. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
  65. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
  66. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
  67. {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
  68. {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
  69. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
  70. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
  71. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
  72. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
  73. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
  74. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
  75. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
  76. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
  77. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
  78. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
  79. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
  80. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_cfg)},
  81. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_cfg)},
  82. /* required last entry */
  83. {0, }
  84. };
  85. MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
  86. #ifdef CONFIG_PM
  87. static inline void mei_me_set_pm_domain(struct mei_device *dev);
  88. static inline void mei_me_unset_pm_domain(struct mei_device *dev);
  89. #else
  90. static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
  91. static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
  92. #endif /* CONFIG_PM */
  93. /**
  94. * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
  95. *
  96. * @pdev: PCI device structure
  97. * @cfg: per generation config
  98. *
  99. * Return: true if ME Interface is valid, false otherwise
  100. */
  101. static bool mei_me_quirk_probe(struct pci_dev *pdev,
  102. const struct mei_cfg *cfg)
  103. {
  104. if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
  105. dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
  106. return false;
  107. }
  108. return true;
  109. }
  110. /**
  111. * mei_me_probe - Device Initialization Routine
  112. *
  113. * @pdev: PCI device structure
  114. * @ent: entry in kcs_pci_tbl
  115. *
  116. * Return: 0 on success, <0 on failure.
  117. */
  118. static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  119. {
  120. const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
  121. struct mei_device *dev;
  122. struct mei_me_hw *hw;
  123. unsigned int irqflags;
  124. int err;
  125. if (!mei_me_quirk_probe(pdev, cfg))
  126. return -ENODEV;
  127. /* enable pci dev */
  128. err = pci_enable_device(pdev);
  129. if (err) {
  130. dev_err(&pdev->dev, "failed to enable pci device.\n");
  131. goto end;
  132. }
  133. /* set PCI host mastering */
  134. pci_set_master(pdev);
  135. /* pci request regions for mei driver */
  136. err = pci_request_regions(pdev, KBUILD_MODNAME);
  137. if (err) {
  138. dev_err(&pdev->dev, "failed to get pci regions.\n");
  139. goto disable_device;
  140. }
  141. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
  142. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  143. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  144. if (err)
  145. err = dma_set_coherent_mask(&pdev->dev,
  146. DMA_BIT_MASK(32));
  147. }
  148. if (err) {
  149. dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
  150. goto release_regions;
  151. }
  152. /* allocates and initializes the mei dev structure */
  153. dev = mei_me_dev_init(pdev, cfg);
  154. if (!dev) {
  155. err = -ENOMEM;
  156. goto release_regions;
  157. }
  158. hw = to_me_hw(dev);
  159. /* mapping IO device memory */
  160. hw->mem_addr = pci_iomap(pdev, 0, 0);
  161. if (!hw->mem_addr) {
  162. dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
  163. err = -ENOMEM;
  164. goto free_device;
  165. }
  166. pci_enable_msi(pdev);
  167. /* request and enable interrupt */
  168. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  169. err = request_threaded_irq(pdev->irq,
  170. mei_me_irq_quick_handler,
  171. mei_me_irq_thread_handler,
  172. irqflags, KBUILD_MODNAME, dev);
  173. if (err) {
  174. dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
  175. pdev->irq);
  176. goto disable_msi;
  177. }
  178. if (mei_start(dev)) {
  179. dev_err(&pdev->dev, "init hw failure.\n");
  180. err = -ENODEV;
  181. goto release_irq;
  182. }
  183. pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
  184. pm_runtime_use_autosuspend(&pdev->dev);
  185. err = mei_register(dev, &pdev->dev);
  186. if (err)
  187. goto release_irq;
  188. pci_set_drvdata(pdev, dev);
  189. schedule_delayed_work(&dev->timer_work, HZ);
  190. /*
  191. * For not wake-able HW runtime pm framework
  192. * can't be used on pci device level.
  193. * Use domain runtime pm callbacks instead.
  194. */
  195. if (!pci_dev_run_wake(pdev))
  196. mei_me_set_pm_domain(dev);
  197. if (mei_pg_is_enabled(dev))
  198. pm_runtime_put_noidle(&pdev->dev);
  199. dev_dbg(&pdev->dev, "initialization successful.\n");
  200. return 0;
  201. release_irq:
  202. mei_cancel_work(dev);
  203. mei_disable_interrupts(dev);
  204. free_irq(pdev->irq, dev);
  205. disable_msi:
  206. pci_disable_msi(pdev);
  207. pci_iounmap(pdev, hw->mem_addr);
  208. free_device:
  209. kfree(dev);
  210. release_regions:
  211. pci_release_regions(pdev);
  212. disable_device:
  213. pci_disable_device(pdev);
  214. end:
  215. dev_err(&pdev->dev, "initialization failed.\n");
  216. return err;
  217. }
  218. /**
  219. * mei_me_remove - Device Removal Routine
  220. *
  221. * @pdev: PCI device structure
  222. *
  223. * mei_remove is called by the PCI subsystem to alert the driver
  224. * that it should release a PCI device.
  225. */
  226. static void mei_me_remove(struct pci_dev *pdev)
  227. {
  228. struct mei_device *dev;
  229. struct mei_me_hw *hw;
  230. dev = pci_get_drvdata(pdev);
  231. if (!dev)
  232. return;
  233. if (mei_pg_is_enabled(dev))
  234. pm_runtime_get_noresume(&pdev->dev);
  235. hw = to_me_hw(dev);
  236. dev_dbg(&pdev->dev, "stop\n");
  237. mei_stop(dev);
  238. if (!pci_dev_run_wake(pdev))
  239. mei_me_unset_pm_domain(dev);
  240. /* disable interrupts */
  241. mei_disable_interrupts(dev);
  242. free_irq(pdev->irq, dev);
  243. pci_disable_msi(pdev);
  244. if (hw->mem_addr)
  245. pci_iounmap(pdev, hw->mem_addr);
  246. mei_deregister(dev);
  247. kfree(dev);
  248. pci_release_regions(pdev);
  249. pci_disable_device(pdev);
  250. }
  251. #ifdef CONFIG_PM_SLEEP
  252. static int mei_me_pci_suspend(struct device *device)
  253. {
  254. struct pci_dev *pdev = to_pci_dev(device);
  255. struct mei_device *dev = pci_get_drvdata(pdev);
  256. if (!dev)
  257. return -ENODEV;
  258. dev_dbg(&pdev->dev, "suspend\n");
  259. mei_stop(dev);
  260. mei_disable_interrupts(dev);
  261. free_irq(pdev->irq, dev);
  262. pci_disable_msi(pdev);
  263. return 0;
  264. }
  265. static int mei_me_pci_resume(struct device *device)
  266. {
  267. struct pci_dev *pdev = to_pci_dev(device);
  268. struct mei_device *dev;
  269. unsigned int irqflags;
  270. int err;
  271. dev = pci_get_drvdata(pdev);
  272. if (!dev)
  273. return -ENODEV;
  274. pci_enable_msi(pdev);
  275. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  276. /* request and enable interrupt */
  277. err = request_threaded_irq(pdev->irq,
  278. mei_me_irq_quick_handler,
  279. mei_me_irq_thread_handler,
  280. irqflags, KBUILD_MODNAME, dev);
  281. if (err) {
  282. dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
  283. pdev->irq);
  284. return err;
  285. }
  286. err = mei_restart(dev);
  287. if (err)
  288. return err;
  289. /* Start timer if stopped in suspend */
  290. schedule_delayed_work(&dev->timer_work, HZ);
  291. return 0;
  292. }
  293. #endif /* CONFIG_PM_SLEEP */
  294. #ifdef CONFIG_PM
  295. static int mei_me_pm_runtime_idle(struct device *device)
  296. {
  297. struct pci_dev *pdev = to_pci_dev(device);
  298. struct mei_device *dev;
  299. dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
  300. dev = pci_get_drvdata(pdev);
  301. if (!dev)
  302. return -ENODEV;
  303. if (mei_write_is_idle(dev))
  304. pm_runtime_autosuspend(device);
  305. return -EBUSY;
  306. }
  307. static int mei_me_pm_runtime_suspend(struct device *device)
  308. {
  309. struct pci_dev *pdev = to_pci_dev(device);
  310. struct mei_device *dev;
  311. int ret;
  312. dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
  313. dev = pci_get_drvdata(pdev);
  314. if (!dev)
  315. return -ENODEV;
  316. mutex_lock(&dev->device_lock);
  317. if (mei_write_is_idle(dev))
  318. ret = mei_me_pg_enter_sync(dev);
  319. else
  320. ret = -EAGAIN;
  321. mutex_unlock(&dev->device_lock);
  322. dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
  323. return ret;
  324. }
  325. static int mei_me_pm_runtime_resume(struct device *device)
  326. {
  327. struct pci_dev *pdev = to_pci_dev(device);
  328. struct mei_device *dev;
  329. int ret;
  330. dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
  331. dev = pci_get_drvdata(pdev);
  332. if (!dev)
  333. return -ENODEV;
  334. mutex_lock(&dev->device_lock);
  335. ret = mei_me_pg_exit_sync(dev);
  336. mutex_unlock(&dev->device_lock);
  337. dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
  338. return ret;
  339. }
  340. /**
  341. * mei_me_set_pm_domain - fill and set pm domain structure for device
  342. *
  343. * @dev: mei_device
  344. */
  345. static inline void mei_me_set_pm_domain(struct mei_device *dev)
  346. {
  347. struct pci_dev *pdev = to_pci_dev(dev->dev);
  348. if (pdev->dev.bus && pdev->dev.bus->pm) {
  349. dev->pg_domain.ops = *pdev->dev.bus->pm;
  350. dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
  351. dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
  352. dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
  353. pdev->dev.pm_domain = &dev->pg_domain;
  354. }
  355. }
  356. /**
  357. * mei_me_unset_pm_domain - clean pm domain structure for device
  358. *
  359. * @dev: mei_device
  360. */
  361. static inline void mei_me_unset_pm_domain(struct mei_device *dev)
  362. {
  363. /* stop using pm callbacks if any */
  364. dev->dev->pm_domain = NULL;
  365. }
  366. static const struct dev_pm_ops mei_me_pm_ops = {
  367. SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
  368. mei_me_pci_resume)
  369. SET_RUNTIME_PM_OPS(
  370. mei_me_pm_runtime_suspend,
  371. mei_me_pm_runtime_resume,
  372. mei_me_pm_runtime_idle)
  373. };
  374. #define MEI_ME_PM_OPS (&mei_me_pm_ops)
  375. #else
  376. #define MEI_ME_PM_OPS NULL
  377. #endif /* CONFIG_PM */
  378. /*
  379. * PCI driver structure
  380. */
  381. static struct pci_driver mei_me_driver = {
  382. .name = KBUILD_MODNAME,
  383. .id_table = mei_me_pci_tbl,
  384. .probe = mei_me_probe,
  385. .remove = mei_me_remove,
  386. .shutdown = mei_me_remove,
  387. .driver.pm = MEI_ME_PM_OPS,
  388. };
  389. module_pci_driver(mei_me_driver);
  390. MODULE_AUTHOR("Intel Corporation");
  391. MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
  392. MODULE_LICENSE("GPL v2");