clk-iproc.h 4.2 KB

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  1. /*
  2. * Copyright (C) 2014 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef _CLK_IPROC_H
  14. #define _CLK_IPROC_H
  15. #include <linux/kernel.h>
  16. #include <linux/list.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/slab.h>
  19. #include <linux/device.h>
  20. #include <linux/of.h>
  21. #include <linux/clk-provider.h>
  22. #define IPROC_CLK_NAME_LEN 25
  23. #define IPROC_CLK_INVALID_OFFSET 0xffffffff
  24. #define bit_mask(width) ((1 << (width)) - 1)
  25. /* clocks that should not be disabled at runtime */
  26. #define IPROC_CLK_AON BIT(0)
  27. /* PLL that requires gating through ASIU */
  28. #define IPROC_CLK_PLL_ASIU BIT(1)
  29. /* PLL that has fractional part of the NDIV */
  30. #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
  31. /*
  32. * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
  33. * of the same register following the write to flush the write transaction into
  34. * the intended register
  35. */
  36. #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
  37. /*
  38. * Some PLLs require the PLL SW override bit to be set before changes can be
  39. * applied to the PLL
  40. */
  41. #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
  42. /*
  43. * Parameters for VCO frequency configuration
  44. *
  45. * VCO frequency =
  46. * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
  47. */
  48. struct iproc_pll_vco_param {
  49. unsigned long rate;
  50. unsigned int ndiv_int;
  51. unsigned int ndiv_frac;
  52. unsigned int pdiv;
  53. };
  54. struct iproc_clk_reg_op {
  55. unsigned int offset;
  56. unsigned int shift;
  57. unsigned int width;
  58. };
  59. /*
  60. * Clock gating control at the top ASIU level
  61. */
  62. struct iproc_asiu_gate {
  63. unsigned int offset;
  64. unsigned int en_shift;
  65. };
  66. /*
  67. * Control of powering on/off of a PLL
  68. *
  69. * Before powering off a PLL, input isolation (ISO) needs to be enabled
  70. */
  71. struct iproc_pll_aon_pwr_ctrl {
  72. unsigned int offset;
  73. unsigned int pwr_width;
  74. unsigned int pwr_shift;
  75. unsigned int iso_shift;
  76. };
  77. /*
  78. * Control of the PLL reset, with Ki, Kp, and Ka parameters
  79. */
  80. struct iproc_pll_reset_ctrl {
  81. unsigned int offset;
  82. unsigned int reset_shift;
  83. unsigned int p_reset_shift;
  84. unsigned int ki_shift;
  85. unsigned int ki_width;
  86. unsigned int kp_shift;
  87. unsigned int kp_width;
  88. unsigned int ka_shift;
  89. unsigned int ka_width;
  90. };
  91. /*
  92. * To enable SW control of the PLL
  93. */
  94. struct iproc_pll_sw_ctrl {
  95. unsigned int offset;
  96. unsigned int shift;
  97. };
  98. struct iproc_pll_vco_ctrl {
  99. unsigned int u_offset;
  100. unsigned int l_offset;
  101. };
  102. /*
  103. * Main PLL control parameters
  104. */
  105. struct iproc_pll_ctrl {
  106. unsigned long flags;
  107. struct iproc_pll_aon_pwr_ctrl aon;
  108. struct iproc_asiu_gate asiu;
  109. struct iproc_pll_reset_ctrl reset;
  110. struct iproc_pll_sw_ctrl sw_ctrl;
  111. struct iproc_clk_reg_op ndiv_int;
  112. struct iproc_clk_reg_op ndiv_frac;
  113. struct iproc_clk_reg_op pdiv;
  114. struct iproc_pll_vco_ctrl vco_ctrl;
  115. struct iproc_clk_reg_op status;
  116. };
  117. /*
  118. * Controls enabling/disabling a PLL derived clock
  119. */
  120. struct iproc_clk_enable_ctrl {
  121. unsigned int offset;
  122. unsigned int enable_shift;
  123. unsigned int hold_shift;
  124. unsigned int bypass_shift;
  125. };
  126. /*
  127. * Main clock control parameters for clocks derived from the PLLs
  128. */
  129. struct iproc_clk_ctrl {
  130. unsigned int channel;
  131. unsigned long flags;
  132. struct iproc_clk_enable_ctrl enable;
  133. struct iproc_clk_reg_op mdiv;
  134. };
  135. /*
  136. * Divisor of the ASIU clocks
  137. */
  138. struct iproc_asiu_div {
  139. unsigned int offset;
  140. unsigned int en_shift;
  141. unsigned int high_shift;
  142. unsigned int high_width;
  143. unsigned int low_shift;
  144. unsigned int low_width;
  145. };
  146. void __init iproc_armpll_setup(struct device_node *node);
  147. void __init iproc_pll_clk_setup(struct device_node *node,
  148. const struct iproc_pll_ctrl *pll_ctrl,
  149. const struct iproc_pll_vco_param *vco,
  150. unsigned int num_vco_entries,
  151. const struct iproc_clk_ctrl *clk_ctrl,
  152. unsigned int num_clks);
  153. void __init iproc_asiu_setup(struct device_node *node,
  154. const struct iproc_asiu_div *div,
  155. const struct iproc_asiu_gate *gate,
  156. unsigned int num_clks);
  157. #endif /* _CLK_IPROC_H */