nvme-core.c 84 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011-2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/nvme.h>
  15. #include <linux/bitops.h>
  16. #include <linux/blkdev.h>
  17. #include <linux/blk-mq.h>
  18. #include <linux/cpu.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include <linux/fs.h>
  22. #include <linux/genhd.h>
  23. #include <linux/hdreg.h>
  24. #include <linux/idr.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/kdev_t.h>
  29. #include <linux/kthread.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list_sort.h>
  32. #include <linux/mm.h>
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/poison.h>
  37. #include <linux/ptrace.h>
  38. #include <linux/sched.h>
  39. #include <linux/slab.h>
  40. #include <linux/t10-pi.h>
  41. #include <linux/types.h>
  42. #include <scsi/sg.h>
  43. #include <asm-generic/io-64-nonatomic-lo-hi.h>
  44. #define NVME_MINORS (1U << MINORBITS)
  45. #define NVME_Q_DEPTH 1024
  46. #define NVME_AQ_DEPTH 256
  47. #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
  48. #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
  49. #define ADMIN_TIMEOUT (admin_timeout * HZ)
  50. #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
  51. static unsigned char admin_timeout = 60;
  52. module_param(admin_timeout, byte, 0644);
  53. MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  54. unsigned char nvme_io_timeout = 30;
  55. module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  56. MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  57. static unsigned char shutdown_timeout = 5;
  58. module_param(shutdown_timeout, byte, 0644);
  59. MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  60. static int nvme_major;
  61. module_param(nvme_major, int, 0);
  62. static int nvme_char_major;
  63. module_param(nvme_char_major, int, 0);
  64. static int use_threaded_interrupts;
  65. module_param(use_threaded_interrupts, int, 0);
  66. static bool use_cmb_sqes = true;
  67. module_param(use_cmb_sqes, bool, 0644);
  68. MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  69. static DEFINE_SPINLOCK(dev_list_lock);
  70. static LIST_HEAD(dev_list);
  71. static struct task_struct *nvme_thread;
  72. static struct workqueue_struct *nvme_workq;
  73. static wait_queue_head_t nvme_kthread_wait;
  74. static struct class *nvme_class;
  75. static void nvme_reset_failed_dev(struct work_struct *ws);
  76. static int nvme_reset(struct nvme_dev *dev);
  77. static int nvme_process_cq(struct nvme_queue *nvmeq);
  78. struct async_cmd_info {
  79. struct kthread_work work;
  80. struct kthread_worker *worker;
  81. struct request *req;
  82. u32 result;
  83. int status;
  84. void *ctx;
  85. };
  86. /*
  87. * An NVM Express queue. Each device has at least two (one for admin
  88. * commands and one for I/O commands).
  89. */
  90. struct nvme_queue {
  91. struct device *q_dmadev;
  92. struct nvme_dev *dev;
  93. char irqname[24]; /* nvme4294967295-65535\0 */
  94. spinlock_t q_lock;
  95. struct nvme_command *sq_cmds;
  96. struct nvme_command __iomem *sq_cmds_io;
  97. volatile struct nvme_completion *cqes;
  98. struct blk_mq_tags **tags;
  99. dma_addr_t sq_dma_addr;
  100. dma_addr_t cq_dma_addr;
  101. u32 __iomem *q_db;
  102. u16 q_depth;
  103. s16 cq_vector;
  104. u16 sq_head;
  105. u16 sq_tail;
  106. u16 cq_head;
  107. u16 qid;
  108. u8 cq_phase;
  109. u8 cqe_seen;
  110. struct async_cmd_info cmdinfo;
  111. };
  112. /*
  113. * Check we didin't inadvertently grow the command struct
  114. */
  115. static inline void _nvme_check_size(void)
  116. {
  117. BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
  118. BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
  119. BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
  120. BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
  121. BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
  122. BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
  123. BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
  124. BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
  125. BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
  126. BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
  127. BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
  128. BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
  129. }
  130. typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
  131. struct nvme_completion *);
  132. struct nvme_cmd_info {
  133. nvme_completion_fn fn;
  134. void *ctx;
  135. int aborted;
  136. struct nvme_queue *nvmeq;
  137. struct nvme_iod iod[0];
  138. };
  139. /*
  140. * Max size of iod being embedded in the request payload
  141. */
  142. #define NVME_INT_PAGES 2
  143. #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
  144. #define NVME_INT_MASK 0x01
  145. /*
  146. * Will slightly overestimate the number of pages needed. This is OK
  147. * as it only leads to a small amount of wasted memory for the lifetime of
  148. * the I/O.
  149. */
  150. static int nvme_npages(unsigned size, struct nvme_dev *dev)
  151. {
  152. unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
  153. return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
  154. }
  155. static unsigned int nvme_cmd_size(struct nvme_dev *dev)
  156. {
  157. unsigned int ret = sizeof(struct nvme_cmd_info);
  158. ret += sizeof(struct nvme_iod);
  159. ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
  160. ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
  161. return ret;
  162. }
  163. static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  164. unsigned int hctx_idx)
  165. {
  166. struct nvme_dev *dev = data;
  167. struct nvme_queue *nvmeq = dev->queues[0];
  168. WARN_ON(hctx_idx != 0);
  169. WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
  170. WARN_ON(nvmeq->tags);
  171. hctx->driver_data = nvmeq;
  172. nvmeq->tags = &dev->admin_tagset.tags[0];
  173. return 0;
  174. }
  175. static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
  176. {
  177. struct nvme_queue *nvmeq = hctx->driver_data;
  178. nvmeq->tags = NULL;
  179. }
  180. static int nvme_admin_init_request(void *data, struct request *req,
  181. unsigned int hctx_idx, unsigned int rq_idx,
  182. unsigned int numa_node)
  183. {
  184. struct nvme_dev *dev = data;
  185. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  186. struct nvme_queue *nvmeq = dev->queues[0];
  187. BUG_ON(!nvmeq);
  188. cmd->nvmeq = nvmeq;
  189. return 0;
  190. }
  191. static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  192. unsigned int hctx_idx)
  193. {
  194. struct nvme_dev *dev = data;
  195. struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
  196. if (!nvmeq->tags)
  197. nvmeq->tags = &dev->tagset.tags[hctx_idx];
  198. WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
  199. hctx->driver_data = nvmeq;
  200. return 0;
  201. }
  202. static int nvme_init_request(void *data, struct request *req,
  203. unsigned int hctx_idx, unsigned int rq_idx,
  204. unsigned int numa_node)
  205. {
  206. struct nvme_dev *dev = data;
  207. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  208. struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
  209. BUG_ON(!nvmeq);
  210. cmd->nvmeq = nvmeq;
  211. return 0;
  212. }
  213. static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
  214. nvme_completion_fn handler)
  215. {
  216. cmd->fn = handler;
  217. cmd->ctx = ctx;
  218. cmd->aborted = 0;
  219. blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
  220. }
  221. static void *iod_get_private(struct nvme_iod *iod)
  222. {
  223. return (void *) (iod->private & ~0x1UL);
  224. }
  225. /*
  226. * If bit 0 is set, the iod is embedded in the request payload.
  227. */
  228. static bool iod_should_kfree(struct nvme_iod *iod)
  229. {
  230. return (iod->private & NVME_INT_MASK) == 0;
  231. }
  232. /* Special values must be less than 0x1000 */
  233. #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
  234. #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
  235. #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
  236. #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
  237. static void special_completion(struct nvme_queue *nvmeq, void *ctx,
  238. struct nvme_completion *cqe)
  239. {
  240. if (ctx == CMD_CTX_CANCELLED)
  241. return;
  242. if (ctx == CMD_CTX_COMPLETED) {
  243. dev_warn(nvmeq->q_dmadev,
  244. "completed id %d twice on queue %d\n",
  245. cqe->command_id, le16_to_cpup(&cqe->sq_id));
  246. return;
  247. }
  248. if (ctx == CMD_CTX_INVALID) {
  249. dev_warn(nvmeq->q_dmadev,
  250. "invalid id %d completed on queue %d\n",
  251. cqe->command_id, le16_to_cpup(&cqe->sq_id));
  252. return;
  253. }
  254. dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
  255. }
  256. static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
  257. {
  258. void *ctx;
  259. if (fn)
  260. *fn = cmd->fn;
  261. ctx = cmd->ctx;
  262. cmd->fn = special_completion;
  263. cmd->ctx = CMD_CTX_CANCELLED;
  264. return ctx;
  265. }
  266. static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
  267. struct nvme_completion *cqe)
  268. {
  269. u32 result = le32_to_cpup(&cqe->result);
  270. u16 status = le16_to_cpup(&cqe->status) >> 1;
  271. if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
  272. ++nvmeq->dev->event_limit;
  273. if (status != NVME_SC_SUCCESS)
  274. return;
  275. switch (result & 0xff07) {
  276. case NVME_AER_NOTICE_NS_CHANGED:
  277. dev_info(nvmeq->q_dmadev, "rescanning\n");
  278. schedule_work(&nvmeq->dev->scan_work);
  279. default:
  280. dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
  281. }
  282. }
  283. static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
  284. struct nvme_completion *cqe)
  285. {
  286. struct request *req = ctx;
  287. u16 status = le16_to_cpup(&cqe->status) >> 1;
  288. u32 result = le32_to_cpup(&cqe->result);
  289. blk_mq_free_request(req);
  290. dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
  291. ++nvmeq->dev->abort_limit;
  292. }
  293. static void async_completion(struct nvme_queue *nvmeq, void *ctx,
  294. struct nvme_completion *cqe)
  295. {
  296. struct async_cmd_info *cmdinfo = ctx;
  297. cmdinfo->result = le32_to_cpup(&cqe->result);
  298. cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
  299. queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
  300. blk_mq_free_request(cmdinfo->req);
  301. }
  302. static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
  303. unsigned int tag)
  304. {
  305. struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
  306. return blk_mq_rq_to_pdu(req);
  307. }
  308. /*
  309. * Called with local interrupts disabled and the q_lock held. May not sleep.
  310. */
  311. static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
  312. nvme_completion_fn *fn)
  313. {
  314. struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
  315. void *ctx;
  316. if (tag >= nvmeq->q_depth) {
  317. *fn = special_completion;
  318. return CMD_CTX_INVALID;
  319. }
  320. if (fn)
  321. *fn = cmd->fn;
  322. ctx = cmd->ctx;
  323. cmd->fn = special_completion;
  324. cmd->ctx = CMD_CTX_COMPLETED;
  325. return ctx;
  326. }
  327. /**
  328. * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
  329. * @nvmeq: The queue to use
  330. * @cmd: The command to send
  331. *
  332. * Safe to use from interrupt context
  333. */
  334. static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
  335. struct nvme_command *cmd)
  336. {
  337. u16 tail = nvmeq->sq_tail;
  338. if (nvmeq->sq_cmds_io)
  339. memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
  340. else
  341. memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
  342. if (++tail == nvmeq->q_depth)
  343. tail = 0;
  344. writel(tail, nvmeq->q_db);
  345. nvmeq->sq_tail = tail;
  346. }
  347. static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
  348. {
  349. unsigned long flags;
  350. spin_lock_irqsave(&nvmeq->q_lock, flags);
  351. __nvme_submit_cmd(nvmeq, cmd);
  352. spin_unlock_irqrestore(&nvmeq->q_lock, flags);
  353. }
  354. static __le64 **iod_list(struct nvme_iod *iod)
  355. {
  356. return ((void *)iod) + iod->offset;
  357. }
  358. static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
  359. unsigned nseg, unsigned long private)
  360. {
  361. iod->private = private;
  362. iod->offset = offsetof(struct nvme_iod, sg[nseg]);
  363. iod->npages = -1;
  364. iod->length = nbytes;
  365. iod->nents = 0;
  366. }
  367. static struct nvme_iod *
  368. __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
  369. unsigned long priv, gfp_t gfp)
  370. {
  371. struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
  372. sizeof(__le64 *) * nvme_npages(bytes, dev) +
  373. sizeof(struct scatterlist) * nseg, gfp);
  374. if (iod)
  375. iod_init(iod, bytes, nseg, priv);
  376. return iod;
  377. }
  378. static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
  379. gfp_t gfp)
  380. {
  381. unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
  382. sizeof(struct nvme_dsm_range);
  383. struct nvme_iod *iod;
  384. if (rq->nr_phys_segments <= NVME_INT_PAGES &&
  385. size <= NVME_INT_BYTES(dev)) {
  386. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
  387. iod = cmd->iod;
  388. iod_init(iod, size, rq->nr_phys_segments,
  389. (unsigned long) rq | NVME_INT_MASK);
  390. return iod;
  391. }
  392. return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
  393. (unsigned long) rq, gfp);
  394. }
  395. static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
  396. {
  397. const int last_prp = dev->page_size / 8 - 1;
  398. int i;
  399. __le64 **list = iod_list(iod);
  400. dma_addr_t prp_dma = iod->first_dma;
  401. if (iod->npages == 0)
  402. dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
  403. for (i = 0; i < iod->npages; i++) {
  404. __le64 *prp_list = list[i];
  405. dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
  406. dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
  407. prp_dma = next_prp_dma;
  408. }
  409. if (iod_should_kfree(iod))
  410. kfree(iod);
  411. }
  412. static int nvme_error_status(u16 status)
  413. {
  414. switch (status & 0x7ff) {
  415. case NVME_SC_SUCCESS:
  416. return 0;
  417. case NVME_SC_CAP_EXCEEDED:
  418. return -ENOSPC;
  419. default:
  420. return -EIO;
  421. }
  422. }
  423. #ifdef CONFIG_BLK_DEV_INTEGRITY
  424. static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
  425. {
  426. if (be32_to_cpu(pi->ref_tag) == v)
  427. pi->ref_tag = cpu_to_be32(p);
  428. }
  429. static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
  430. {
  431. if (be32_to_cpu(pi->ref_tag) == p)
  432. pi->ref_tag = cpu_to_be32(v);
  433. }
  434. /**
  435. * nvme_dif_remap - remaps ref tags to bip seed and physical lba
  436. *
  437. * The virtual start sector is the one that was originally submitted by the
  438. * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
  439. * start sector may be different. Remap protection information to match the
  440. * physical LBA on writes, and back to the original seed on reads.
  441. *
  442. * Type 0 and 3 do not have a ref tag, so no remapping required.
  443. */
  444. static void nvme_dif_remap(struct request *req,
  445. void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
  446. {
  447. struct nvme_ns *ns = req->rq_disk->private_data;
  448. struct bio_integrity_payload *bip;
  449. struct t10_pi_tuple *pi;
  450. void *p, *pmap;
  451. u32 i, nlb, ts, phys, virt;
  452. if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
  453. return;
  454. bip = bio_integrity(req->bio);
  455. if (!bip)
  456. return;
  457. pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
  458. p = pmap;
  459. virt = bip_get_seed(bip);
  460. phys = nvme_block_nr(ns, blk_rq_pos(req));
  461. nlb = (blk_rq_bytes(req) >> ns->lba_shift);
  462. ts = ns->disk->integrity->tuple_size;
  463. for (i = 0; i < nlb; i++, virt++, phys++) {
  464. pi = (struct t10_pi_tuple *)p;
  465. dif_swap(phys, virt, pi);
  466. p += ts;
  467. }
  468. kunmap_atomic(pmap);
  469. }
  470. static int nvme_noop_verify(struct blk_integrity_iter *iter)
  471. {
  472. return 0;
  473. }
  474. static int nvme_noop_generate(struct blk_integrity_iter *iter)
  475. {
  476. return 0;
  477. }
  478. struct blk_integrity nvme_meta_noop = {
  479. .name = "NVME_META_NOOP",
  480. .generate_fn = nvme_noop_generate,
  481. .verify_fn = nvme_noop_verify,
  482. };
  483. static void nvme_init_integrity(struct nvme_ns *ns)
  484. {
  485. struct blk_integrity integrity;
  486. switch (ns->pi_type) {
  487. case NVME_NS_DPS_PI_TYPE3:
  488. integrity = t10_pi_type3_crc;
  489. break;
  490. case NVME_NS_DPS_PI_TYPE1:
  491. case NVME_NS_DPS_PI_TYPE2:
  492. integrity = t10_pi_type1_crc;
  493. break;
  494. default:
  495. integrity = nvme_meta_noop;
  496. break;
  497. }
  498. integrity.tuple_size = ns->ms;
  499. blk_integrity_register(ns->disk, &integrity);
  500. blk_queue_max_integrity_segments(ns->queue, 1);
  501. }
  502. #else /* CONFIG_BLK_DEV_INTEGRITY */
  503. static void nvme_dif_remap(struct request *req,
  504. void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
  505. {
  506. }
  507. static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
  508. {
  509. }
  510. static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
  511. {
  512. }
  513. static void nvme_init_integrity(struct nvme_ns *ns)
  514. {
  515. }
  516. #endif
  517. static void req_completion(struct nvme_queue *nvmeq, void *ctx,
  518. struct nvme_completion *cqe)
  519. {
  520. struct nvme_iod *iod = ctx;
  521. struct request *req = iod_get_private(iod);
  522. struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
  523. u16 status = le16_to_cpup(&cqe->status) >> 1;
  524. bool requeue = false;
  525. int error = 0;
  526. if (unlikely(status)) {
  527. if (!(status & NVME_SC_DNR || blk_noretry_request(req))
  528. && (jiffies - req->start_time) < req->timeout) {
  529. unsigned long flags;
  530. requeue = true;
  531. blk_mq_requeue_request(req);
  532. spin_lock_irqsave(req->q->queue_lock, flags);
  533. if (!blk_queue_stopped(req->q))
  534. blk_mq_kick_requeue_list(req->q);
  535. spin_unlock_irqrestore(req->q->queue_lock, flags);
  536. goto release_iod;
  537. }
  538. if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
  539. if (cmd_rq->ctx == CMD_CTX_CANCELLED)
  540. error = -EINTR;
  541. else
  542. error = status;
  543. } else {
  544. error = nvme_error_status(status);
  545. }
  546. }
  547. if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
  548. u32 result = le32_to_cpup(&cqe->result);
  549. req->special = (void *)(uintptr_t)result;
  550. }
  551. if (cmd_rq->aborted)
  552. dev_warn(nvmeq->dev->dev,
  553. "completing aborted command with status:%04x\n",
  554. error);
  555. release_iod:
  556. if (iod->nents) {
  557. dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
  558. rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  559. if (blk_integrity_rq(req)) {
  560. if (!rq_data_dir(req))
  561. nvme_dif_remap(req, nvme_dif_complete);
  562. dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
  563. rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  564. }
  565. }
  566. nvme_free_iod(nvmeq->dev, iod);
  567. if (likely(!requeue))
  568. blk_mq_complete_request(req, error);
  569. }
  570. /* length is in bytes. gfp flags indicates whether we may sleep. */
  571. static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
  572. int total_len, gfp_t gfp)
  573. {
  574. struct dma_pool *pool;
  575. int length = total_len;
  576. struct scatterlist *sg = iod->sg;
  577. int dma_len = sg_dma_len(sg);
  578. u64 dma_addr = sg_dma_address(sg);
  579. u32 page_size = dev->page_size;
  580. int offset = dma_addr & (page_size - 1);
  581. __le64 *prp_list;
  582. __le64 **list = iod_list(iod);
  583. dma_addr_t prp_dma;
  584. int nprps, i;
  585. length -= (page_size - offset);
  586. if (length <= 0)
  587. return total_len;
  588. dma_len -= (page_size - offset);
  589. if (dma_len) {
  590. dma_addr += (page_size - offset);
  591. } else {
  592. sg = sg_next(sg);
  593. dma_addr = sg_dma_address(sg);
  594. dma_len = sg_dma_len(sg);
  595. }
  596. if (length <= page_size) {
  597. iod->first_dma = dma_addr;
  598. return total_len;
  599. }
  600. nprps = DIV_ROUND_UP(length, page_size);
  601. if (nprps <= (256 / 8)) {
  602. pool = dev->prp_small_pool;
  603. iod->npages = 0;
  604. } else {
  605. pool = dev->prp_page_pool;
  606. iod->npages = 1;
  607. }
  608. prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
  609. if (!prp_list) {
  610. iod->first_dma = dma_addr;
  611. iod->npages = -1;
  612. return (total_len - length) + page_size;
  613. }
  614. list[0] = prp_list;
  615. iod->first_dma = prp_dma;
  616. i = 0;
  617. for (;;) {
  618. if (i == page_size >> 3) {
  619. __le64 *old_prp_list = prp_list;
  620. prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
  621. if (!prp_list)
  622. return total_len - length;
  623. list[iod->npages++] = prp_list;
  624. prp_list[0] = old_prp_list[i - 1];
  625. old_prp_list[i - 1] = cpu_to_le64(prp_dma);
  626. i = 1;
  627. }
  628. prp_list[i++] = cpu_to_le64(dma_addr);
  629. dma_len -= page_size;
  630. dma_addr += page_size;
  631. length -= page_size;
  632. if (length <= 0)
  633. break;
  634. if (dma_len > 0)
  635. continue;
  636. BUG_ON(dma_len < 0);
  637. sg = sg_next(sg);
  638. dma_addr = sg_dma_address(sg);
  639. dma_len = sg_dma_len(sg);
  640. }
  641. return total_len;
  642. }
  643. static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
  644. struct nvme_iod *iod)
  645. {
  646. struct nvme_command cmnd;
  647. memcpy(&cmnd, req->cmd, sizeof(cmnd));
  648. cmnd.rw.command_id = req->tag;
  649. if (req->nr_phys_segments) {
  650. cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  651. cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
  652. }
  653. __nvme_submit_cmd(nvmeq, &cmnd);
  654. }
  655. /*
  656. * We reuse the small pool to allocate the 16-byte range here as it is not
  657. * worth having a special pool for these or additional cases to handle freeing
  658. * the iod.
  659. */
  660. static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
  661. struct request *req, struct nvme_iod *iod)
  662. {
  663. struct nvme_dsm_range *range =
  664. (struct nvme_dsm_range *)iod_list(iod)[0];
  665. struct nvme_command cmnd;
  666. range->cattr = cpu_to_le32(0);
  667. range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
  668. range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
  669. memset(&cmnd, 0, sizeof(cmnd));
  670. cmnd.dsm.opcode = nvme_cmd_dsm;
  671. cmnd.dsm.command_id = req->tag;
  672. cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
  673. cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
  674. cmnd.dsm.nr = 0;
  675. cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
  676. __nvme_submit_cmd(nvmeq, &cmnd);
  677. }
  678. static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
  679. int cmdid)
  680. {
  681. struct nvme_command cmnd;
  682. memset(&cmnd, 0, sizeof(cmnd));
  683. cmnd.common.opcode = nvme_cmd_flush;
  684. cmnd.common.command_id = cmdid;
  685. cmnd.common.nsid = cpu_to_le32(ns->ns_id);
  686. __nvme_submit_cmd(nvmeq, &cmnd);
  687. }
  688. static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
  689. struct nvme_ns *ns)
  690. {
  691. struct request *req = iod_get_private(iod);
  692. struct nvme_command cmnd;
  693. u16 control = 0;
  694. u32 dsmgmt = 0;
  695. if (req->cmd_flags & REQ_FUA)
  696. control |= NVME_RW_FUA;
  697. if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
  698. control |= NVME_RW_LR;
  699. if (req->cmd_flags & REQ_RAHEAD)
  700. dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
  701. memset(&cmnd, 0, sizeof(cmnd));
  702. cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
  703. cmnd.rw.command_id = req->tag;
  704. cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
  705. cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  706. cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
  707. cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
  708. cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
  709. if (ns->ms) {
  710. switch (ns->pi_type) {
  711. case NVME_NS_DPS_PI_TYPE3:
  712. control |= NVME_RW_PRINFO_PRCHK_GUARD;
  713. break;
  714. case NVME_NS_DPS_PI_TYPE1:
  715. case NVME_NS_DPS_PI_TYPE2:
  716. control |= NVME_RW_PRINFO_PRCHK_GUARD |
  717. NVME_RW_PRINFO_PRCHK_REF;
  718. cmnd.rw.reftag = cpu_to_le32(
  719. nvme_block_nr(ns, blk_rq_pos(req)));
  720. break;
  721. }
  722. if (blk_integrity_rq(req))
  723. cmnd.rw.metadata =
  724. cpu_to_le64(sg_dma_address(iod->meta_sg));
  725. else
  726. control |= NVME_RW_PRINFO_PRACT;
  727. }
  728. cmnd.rw.control = cpu_to_le16(control);
  729. cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
  730. __nvme_submit_cmd(nvmeq, &cmnd);
  731. return 0;
  732. }
  733. /*
  734. * NOTE: ns is NULL when called on the admin queue.
  735. */
  736. static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
  737. const struct blk_mq_queue_data *bd)
  738. {
  739. struct nvme_ns *ns = hctx->queue->queuedata;
  740. struct nvme_queue *nvmeq = hctx->driver_data;
  741. struct nvme_dev *dev = nvmeq->dev;
  742. struct request *req = bd->rq;
  743. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  744. struct nvme_iod *iod;
  745. enum dma_data_direction dma_dir;
  746. /*
  747. * If formated with metadata, require the block layer provide a buffer
  748. * unless this namespace is formated such that the metadata can be
  749. * stripped/generated by the controller with PRACT=1.
  750. */
  751. if (ns && ns->ms && !blk_integrity_rq(req)) {
  752. if (!(ns->pi_type && ns->ms == 8) &&
  753. req->cmd_type != REQ_TYPE_DRV_PRIV) {
  754. blk_mq_complete_request(req, -EFAULT);
  755. return BLK_MQ_RQ_QUEUE_OK;
  756. }
  757. }
  758. iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
  759. if (!iod)
  760. return BLK_MQ_RQ_QUEUE_BUSY;
  761. if (req->cmd_flags & REQ_DISCARD) {
  762. void *range;
  763. /*
  764. * We reuse the small pool to allocate the 16-byte range here
  765. * as it is not worth having a special pool for these or
  766. * additional cases to handle freeing the iod.
  767. */
  768. range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
  769. &iod->first_dma);
  770. if (!range)
  771. goto retry_cmd;
  772. iod_list(iod)[0] = (__le64 *)range;
  773. iod->npages = 0;
  774. } else if (req->nr_phys_segments) {
  775. dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  776. sg_init_table(iod->sg, req->nr_phys_segments);
  777. iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
  778. if (!iod->nents)
  779. goto error_cmd;
  780. if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
  781. goto retry_cmd;
  782. if (blk_rq_bytes(req) !=
  783. nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
  784. dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
  785. goto retry_cmd;
  786. }
  787. if (blk_integrity_rq(req)) {
  788. if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
  789. goto error_cmd;
  790. sg_init_table(iod->meta_sg, 1);
  791. if (blk_rq_map_integrity_sg(
  792. req->q, req->bio, iod->meta_sg) != 1)
  793. goto error_cmd;
  794. if (rq_data_dir(req))
  795. nvme_dif_remap(req, nvme_dif_prep);
  796. if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
  797. goto error_cmd;
  798. }
  799. }
  800. nvme_set_info(cmd, iod, req_completion);
  801. spin_lock_irq(&nvmeq->q_lock);
  802. if (req->cmd_type == REQ_TYPE_DRV_PRIV)
  803. nvme_submit_priv(nvmeq, req, iod);
  804. else if (req->cmd_flags & REQ_DISCARD)
  805. nvme_submit_discard(nvmeq, ns, req, iod);
  806. else if (req->cmd_flags & REQ_FLUSH)
  807. nvme_submit_flush(nvmeq, ns, req->tag);
  808. else
  809. nvme_submit_iod(nvmeq, iod, ns);
  810. nvme_process_cq(nvmeq);
  811. spin_unlock_irq(&nvmeq->q_lock);
  812. return BLK_MQ_RQ_QUEUE_OK;
  813. error_cmd:
  814. nvme_free_iod(dev, iod);
  815. return BLK_MQ_RQ_QUEUE_ERROR;
  816. retry_cmd:
  817. nvme_free_iod(dev, iod);
  818. return BLK_MQ_RQ_QUEUE_BUSY;
  819. }
  820. static int nvme_process_cq(struct nvme_queue *nvmeq)
  821. {
  822. u16 head, phase;
  823. head = nvmeq->cq_head;
  824. phase = nvmeq->cq_phase;
  825. for (;;) {
  826. void *ctx;
  827. nvme_completion_fn fn;
  828. struct nvme_completion cqe = nvmeq->cqes[head];
  829. if ((le16_to_cpu(cqe.status) & 1) != phase)
  830. break;
  831. nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
  832. if (++head == nvmeq->q_depth) {
  833. head = 0;
  834. phase = !phase;
  835. }
  836. ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
  837. fn(nvmeq, ctx, &cqe);
  838. }
  839. /* If the controller ignores the cq head doorbell and continuously
  840. * writes to the queue, it is theoretically possible to wrap around
  841. * the queue twice and mistakenly return IRQ_NONE. Linux only
  842. * requires that 0.1% of your interrupts are handled, so this isn't
  843. * a big problem.
  844. */
  845. if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
  846. return 0;
  847. writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
  848. nvmeq->cq_head = head;
  849. nvmeq->cq_phase = phase;
  850. nvmeq->cqe_seen = 1;
  851. return 1;
  852. }
  853. static irqreturn_t nvme_irq(int irq, void *data)
  854. {
  855. irqreturn_t result;
  856. struct nvme_queue *nvmeq = data;
  857. spin_lock(&nvmeq->q_lock);
  858. nvme_process_cq(nvmeq);
  859. result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
  860. nvmeq->cqe_seen = 0;
  861. spin_unlock(&nvmeq->q_lock);
  862. return result;
  863. }
  864. static irqreturn_t nvme_irq_check(int irq, void *data)
  865. {
  866. struct nvme_queue *nvmeq = data;
  867. struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
  868. if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
  869. return IRQ_NONE;
  870. return IRQ_WAKE_THREAD;
  871. }
  872. /*
  873. * Returns 0 on success. If the result is negative, it's a Linux error code;
  874. * if the result is positive, it's an NVM Express status code
  875. */
  876. int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  877. void *buffer, void __user *ubuffer, unsigned bufflen,
  878. u32 *result, unsigned timeout)
  879. {
  880. bool write = cmd->common.opcode & 1;
  881. struct bio *bio = NULL;
  882. struct request *req;
  883. int ret;
  884. req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
  885. if (IS_ERR(req))
  886. return PTR_ERR(req);
  887. req->cmd_type = REQ_TYPE_DRV_PRIV;
  888. req->cmd_flags |= REQ_FAILFAST_DRIVER;
  889. req->__data_len = 0;
  890. req->__sector = (sector_t) -1;
  891. req->bio = req->biotail = NULL;
  892. req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
  893. req->cmd = (unsigned char *)cmd;
  894. req->cmd_len = sizeof(struct nvme_command);
  895. req->special = (void *)0;
  896. if (buffer && bufflen) {
  897. ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
  898. if (ret)
  899. goto out;
  900. } else if (ubuffer && bufflen) {
  901. ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
  902. if (ret)
  903. goto out;
  904. bio = req->bio;
  905. }
  906. blk_execute_rq(req->q, NULL, req, 0);
  907. if (bio)
  908. blk_rq_unmap_user(bio);
  909. if (result)
  910. *result = (u32)(uintptr_t)req->special;
  911. ret = req->errors;
  912. out:
  913. blk_mq_free_request(req);
  914. return ret;
  915. }
  916. int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  917. void *buffer, unsigned bufflen)
  918. {
  919. return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
  920. }
  921. static int nvme_submit_async_admin_req(struct nvme_dev *dev)
  922. {
  923. struct nvme_queue *nvmeq = dev->queues[0];
  924. struct nvme_command c;
  925. struct nvme_cmd_info *cmd_info;
  926. struct request *req;
  927. req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
  928. if (IS_ERR(req))
  929. return PTR_ERR(req);
  930. req->cmd_flags |= REQ_NO_TIMEOUT;
  931. cmd_info = blk_mq_rq_to_pdu(req);
  932. nvme_set_info(cmd_info, NULL, async_req_completion);
  933. memset(&c, 0, sizeof(c));
  934. c.common.opcode = nvme_admin_async_event;
  935. c.common.command_id = req->tag;
  936. blk_mq_free_request(req);
  937. __nvme_submit_cmd(nvmeq, &c);
  938. return 0;
  939. }
  940. static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
  941. struct nvme_command *cmd,
  942. struct async_cmd_info *cmdinfo, unsigned timeout)
  943. {
  944. struct nvme_queue *nvmeq = dev->queues[0];
  945. struct request *req;
  946. struct nvme_cmd_info *cmd_rq;
  947. req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
  948. if (IS_ERR(req))
  949. return PTR_ERR(req);
  950. req->timeout = timeout;
  951. cmd_rq = blk_mq_rq_to_pdu(req);
  952. cmdinfo->req = req;
  953. nvme_set_info(cmd_rq, cmdinfo, async_completion);
  954. cmdinfo->status = -EINTR;
  955. cmd->common.command_id = req->tag;
  956. nvme_submit_cmd(nvmeq, cmd);
  957. return 0;
  958. }
  959. static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
  960. {
  961. struct nvme_command c;
  962. memset(&c, 0, sizeof(c));
  963. c.delete_queue.opcode = opcode;
  964. c.delete_queue.qid = cpu_to_le16(id);
  965. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  966. }
  967. static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
  968. struct nvme_queue *nvmeq)
  969. {
  970. struct nvme_command c;
  971. int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
  972. /*
  973. * Note: we (ab)use the fact the the prp fields survive if no data
  974. * is attached to the request.
  975. */
  976. memset(&c, 0, sizeof(c));
  977. c.create_cq.opcode = nvme_admin_create_cq;
  978. c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
  979. c.create_cq.cqid = cpu_to_le16(qid);
  980. c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  981. c.create_cq.cq_flags = cpu_to_le16(flags);
  982. c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
  983. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  984. }
  985. static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
  986. struct nvme_queue *nvmeq)
  987. {
  988. struct nvme_command c;
  989. int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
  990. /*
  991. * Note: we (ab)use the fact the the prp fields survive if no data
  992. * is attached to the request.
  993. */
  994. memset(&c, 0, sizeof(c));
  995. c.create_sq.opcode = nvme_admin_create_sq;
  996. c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
  997. c.create_sq.sqid = cpu_to_le16(qid);
  998. c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  999. c.create_sq.sq_flags = cpu_to_le16(flags);
  1000. c.create_sq.cqid = cpu_to_le16(qid);
  1001. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  1002. }
  1003. static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
  1004. {
  1005. return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
  1006. }
  1007. static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
  1008. {
  1009. return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
  1010. }
  1011. int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
  1012. {
  1013. struct nvme_command c = { };
  1014. int error;
  1015. /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
  1016. c.identify.opcode = nvme_admin_identify;
  1017. c.identify.cns = cpu_to_le32(1);
  1018. *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
  1019. if (!*id)
  1020. return -ENOMEM;
  1021. error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
  1022. sizeof(struct nvme_id_ctrl));
  1023. if (error)
  1024. kfree(*id);
  1025. return error;
  1026. }
  1027. int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
  1028. struct nvme_id_ns **id)
  1029. {
  1030. struct nvme_command c = { };
  1031. int error;
  1032. /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
  1033. c.identify.opcode = nvme_admin_identify,
  1034. c.identify.nsid = cpu_to_le32(nsid),
  1035. *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
  1036. if (!*id)
  1037. return -ENOMEM;
  1038. error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
  1039. sizeof(struct nvme_id_ns));
  1040. if (error)
  1041. kfree(*id);
  1042. return error;
  1043. }
  1044. int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
  1045. dma_addr_t dma_addr, u32 *result)
  1046. {
  1047. struct nvme_command c;
  1048. memset(&c, 0, sizeof(c));
  1049. c.features.opcode = nvme_admin_get_features;
  1050. c.features.nsid = cpu_to_le32(nsid);
  1051. c.features.prp1 = cpu_to_le64(dma_addr);
  1052. c.features.fid = cpu_to_le32(fid);
  1053. return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
  1054. result, 0);
  1055. }
  1056. int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
  1057. dma_addr_t dma_addr, u32 *result)
  1058. {
  1059. struct nvme_command c;
  1060. memset(&c, 0, sizeof(c));
  1061. c.features.opcode = nvme_admin_set_features;
  1062. c.features.prp1 = cpu_to_le64(dma_addr);
  1063. c.features.fid = cpu_to_le32(fid);
  1064. c.features.dword11 = cpu_to_le32(dword11);
  1065. return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
  1066. result, 0);
  1067. }
  1068. int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
  1069. {
  1070. struct nvme_command c = { };
  1071. int error;
  1072. c.common.opcode = nvme_admin_get_log_page,
  1073. c.common.nsid = cpu_to_le32(0xFFFFFFFF),
  1074. c.common.cdw10[0] = cpu_to_le32(
  1075. (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
  1076. NVME_LOG_SMART),
  1077. *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
  1078. if (!*log)
  1079. return -ENOMEM;
  1080. error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
  1081. sizeof(struct nvme_smart_log));
  1082. if (error)
  1083. kfree(*log);
  1084. return error;
  1085. }
  1086. /**
  1087. * nvme_abort_req - Attempt aborting a request
  1088. *
  1089. * Schedule controller reset if the command was already aborted once before and
  1090. * still hasn't been returned to the driver, or if this is the admin queue.
  1091. */
  1092. static void nvme_abort_req(struct request *req)
  1093. {
  1094. struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
  1095. struct nvme_queue *nvmeq = cmd_rq->nvmeq;
  1096. struct nvme_dev *dev = nvmeq->dev;
  1097. struct request *abort_req;
  1098. struct nvme_cmd_info *abort_cmd;
  1099. struct nvme_command cmd;
  1100. if (!nvmeq->qid || cmd_rq->aborted) {
  1101. unsigned long flags;
  1102. spin_lock_irqsave(&dev_list_lock, flags);
  1103. if (work_busy(&dev->reset_work))
  1104. goto out;
  1105. list_del_init(&dev->node);
  1106. dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
  1107. req->tag, nvmeq->qid);
  1108. dev->reset_workfn = nvme_reset_failed_dev;
  1109. queue_work(nvme_workq, &dev->reset_work);
  1110. out:
  1111. spin_unlock_irqrestore(&dev_list_lock, flags);
  1112. return;
  1113. }
  1114. if (!dev->abort_limit)
  1115. return;
  1116. abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
  1117. false);
  1118. if (IS_ERR(abort_req))
  1119. return;
  1120. abort_cmd = blk_mq_rq_to_pdu(abort_req);
  1121. nvme_set_info(abort_cmd, abort_req, abort_completion);
  1122. memset(&cmd, 0, sizeof(cmd));
  1123. cmd.abort.opcode = nvme_admin_abort_cmd;
  1124. cmd.abort.cid = req->tag;
  1125. cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
  1126. cmd.abort.command_id = abort_req->tag;
  1127. --dev->abort_limit;
  1128. cmd_rq->aborted = 1;
  1129. dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
  1130. nvmeq->qid);
  1131. nvme_submit_cmd(dev->queues[0], &cmd);
  1132. }
  1133. static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
  1134. {
  1135. struct nvme_queue *nvmeq = data;
  1136. void *ctx;
  1137. nvme_completion_fn fn;
  1138. struct nvme_cmd_info *cmd;
  1139. struct nvme_completion cqe;
  1140. if (!blk_mq_request_started(req))
  1141. return;
  1142. cmd = blk_mq_rq_to_pdu(req);
  1143. if (cmd->ctx == CMD_CTX_CANCELLED)
  1144. return;
  1145. if (blk_queue_dying(req->q))
  1146. cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
  1147. else
  1148. cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
  1149. dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
  1150. req->tag, nvmeq->qid);
  1151. ctx = cancel_cmd_info(cmd, &fn);
  1152. fn(nvmeq, ctx, &cqe);
  1153. }
  1154. static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
  1155. {
  1156. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  1157. struct nvme_queue *nvmeq = cmd->nvmeq;
  1158. dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
  1159. nvmeq->qid);
  1160. spin_lock_irq(&nvmeq->q_lock);
  1161. nvme_abort_req(req);
  1162. spin_unlock_irq(&nvmeq->q_lock);
  1163. /*
  1164. * The aborted req will be completed on receiving the abort req.
  1165. * We enable the timer again. If hit twice, it'll cause a device reset,
  1166. * as the device then is in a faulty state.
  1167. */
  1168. return BLK_EH_RESET_TIMER;
  1169. }
  1170. static void nvme_free_queue(struct nvme_queue *nvmeq)
  1171. {
  1172. dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
  1173. (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
  1174. if (nvmeq->sq_cmds)
  1175. dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
  1176. nvmeq->sq_cmds, nvmeq->sq_dma_addr);
  1177. kfree(nvmeq);
  1178. }
  1179. static void nvme_free_queues(struct nvme_dev *dev, int lowest)
  1180. {
  1181. int i;
  1182. for (i = dev->queue_count - 1; i >= lowest; i--) {
  1183. struct nvme_queue *nvmeq = dev->queues[i];
  1184. dev->queue_count--;
  1185. dev->queues[i] = NULL;
  1186. nvme_free_queue(nvmeq);
  1187. }
  1188. }
  1189. /**
  1190. * nvme_suspend_queue - put queue into suspended state
  1191. * @nvmeq - queue to suspend
  1192. */
  1193. static int nvme_suspend_queue(struct nvme_queue *nvmeq)
  1194. {
  1195. int vector;
  1196. spin_lock_irq(&nvmeq->q_lock);
  1197. if (nvmeq->cq_vector == -1) {
  1198. spin_unlock_irq(&nvmeq->q_lock);
  1199. return 1;
  1200. }
  1201. vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
  1202. nvmeq->dev->online_queues--;
  1203. nvmeq->cq_vector = -1;
  1204. spin_unlock_irq(&nvmeq->q_lock);
  1205. if (!nvmeq->qid && nvmeq->dev->admin_q)
  1206. blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
  1207. irq_set_affinity_hint(vector, NULL);
  1208. free_irq(vector, nvmeq);
  1209. return 0;
  1210. }
  1211. static void nvme_clear_queue(struct nvme_queue *nvmeq)
  1212. {
  1213. spin_lock_irq(&nvmeq->q_lock);
  1214. if (nvmeq->tags && *nvmeq->tags)
  1215. blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
  1216. spin_unlock_irq(&nvmeq->q_lock);
  1217. }
  1218. static void nvme_disable_queue(struct nvme_dev *dev, int qid)
  1219. {
  1220. struct nvme_queue *nvmeq = dev->queues[qid];
  1221. if (!nvmeq)
  1222. return;
  1223. if (nvme_suspend_queue(nvmeq))
  1224. return;
  1225. /* Don't tell the adapter to delete the admin queue.
  1226. * Don't tell a removed adapter to delete IO queues. */
  1227. if (qid && readl(&dev->bar->csts) != -1) {
  1228. adapter_delete_sq(dev, qid);
  1229. adapter_delete_cq(dev, qid);
  1230. }
  1231. spin_lock_irq(&nvmeq->q_lock);
  1232. nvme_process_cq(nvmeq);
  1233. spin_unlock_irq(&nvmeq->q_lock);
  1234. }
  1235. static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
  1236. int entry_size)
  1237. {
  1238. int q_depth = dev->q_depth;
  1239. unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
  1240. if (q_size_aligned * nr_io_queues > dev->cmb_size) {
  1241. u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
  1242. mem_per_q = round_down(mem_per_q, dev->page_size);
  1243. q_depth = div_u64(mem_per_q, entry_size);
  1244. /*
  1245. * Ensure the reduced q_depth is above some threshold where it
  1246. * would be better to map queues in system memory with the
  1247. * original depth
  1248. */
  1249. if (q_depth < 64)
  1250. return -ENOMEM;
  1251. }
  1252. return q_depth;
  1253. }
  1254. static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
  1255. int qid, int depth)
  1256. {
  1257. if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
  1258. unsigned offset = (qid - 1) *
  1259. roundup(SQ_SIZE(depth), dev->page_size);
  1260. nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
  1261. nvmeq->sq_cmds_io = dev->cmb + offset;
  1262. } else {
  1263. nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
  1264. &nvmeq->sq_dma_addr, GFP_KERNEL);
  1265. if (!nvmeq->sq_cmds)
  1266. return -ENOMEM;
  1267. }
  1268. return 0;
  1269. }
  1270. static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
  1271. int depth)
  1272. {
  1273. struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
  1274. if (!nvmeq)
  1275. return NULL;
  1276. nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
  1277. &nvmeq->cq_dma_addr, GFP_KERNEL);
  1278. if (!nvmeq->cqes)
  1279. goto free_nvmeq;
  1280. if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
  1281. goto free_cqdma;
  1282. nvmeq->q_dmadev = dev->dev;
  1283. nvmeq->dev = dev;
  1284. snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
  1285. dev->instance, qid);
  1286. spin_lock_init(&nvmeq->q_lock);
  1287. nvmeq->cq_head = 0;
  1288. nvmeq->cq_phase = 1;
  1289. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1290. nvmeq->q_depth = depth;
  1291. nvmeq->qid = qid;
  1292. nvmeq->cq_vector = -1;
  1293. dev->queues[qid] = nvmeq;
  1294. /* make sure queue descriptor is set before queue count, for kthread */
  1295. mb();
  1296. dev->queue_count++;
  1297. return nvmeq;
  1298. free_cqdma:
  1299. dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
  1300. nvmeq->cq_dma_addr);
  1301. free_nvmeq:
  1302. kfree(nvmeq);
  1303. return NULL;
  1304. }
  1305. static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
  1306. const char *name)
  1307. {
  1308. if (use_threaded_interrupts)
  1309. return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
  1310. nvme_irq_check, nvme_irq, IRQF_SHARED,
  1311. name, nvmeq);
  1312. return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
  1313. IRQF_SHARED, name, nvmeq);
  1314. }
  1315. static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
  1316. {
  1317. struct nvme_dev *dev = nvmeq->dev;
  1318. spin_lock_irq(&nvmeq->q_lock);
  1319. nvmeq->sq_tail = 0;
  1320. nvmeq->cq_head = 0;
  1321. nvmeq->cq_phase = 1;
  1322. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1323. memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
  1324. dev->online_queues++;
  1325. spin_unlock_irq(&nvmeq->q_lock);
  1326. }
  1327. static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
  1328. {
  1329. struct nvme_dev *dev = nvmeq->dev;
  1330. int result;
  1331. nvmeq->cq_vector = qid - 1;
  1332. result = adapter_alloc_cq(dev, qid, nvmeq);
  1333. if (result < 0)
  1334. return result;
  1335. result = adapter_alloc_sq(dev, qid, nvmeq);
  1336. if (result < 0)
  1337. goto release_cq;
  1338. result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
  1339. if (result < 0)
  1340. goto release_sq;
  1341. nvme_init_queue(nvmeq, qid);
  1342. return result;
  1343. release_sq:
  1344. adapter_delete_sq(dev, qid);
  1345. release_cq:
  1346. adapter_delete_cq(dev, qid);
  1347. return result;
  1348. }
  1349. static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
  1350. {
  1351. unsigned long timeout;
  1352. u32 bit = enabled ? NVME_CSTS_RDY : 0;
  1353. timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
  1354. while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
  1355. msleep(100);
  1356. if (fatal_signal_pending(current))
  1357. return -EINTR;
  1358. if (time_after(jiffies, timeout)) {
  1359. dev_err(dev->dev,
  1360. "Device not ready; aborting %s\n", enabled ?
  1361. "initialisation" : "reset");
  1362. return -ENODEV;
  1363. }
  1364. }
  1365. return 0;
  1366. }
  1367. /*
  1368. * If the device has been passed off to us in an enabled state, just clear
  1369. * the enabled bit. The spec says we should set the 'shutdown notification
  1370. * bits', but doing so may cause the device to complete commands to the
  1371. * admin queue ... and we don't know what memory that might be pointing at!
  1372. */
  1373. static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
  1374. {
  1375. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1376. dev->ctrl_config &= ~NVME_CC_ENABLE;
  1377. writel(dev->ctrl_config, &dev->bar->cc);
  1378. return nvme_wait_ready(dev, cap, false);
  1379. }
  1380. static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
  1381. {
  1382. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1383. dev->ctrl_config |= NVME_CC_ENABLE;
  1384. writel(dev->ctrl_config, &dev->bar->cc);
  1385. return nvme_wait_ready(dev, cap, true);
  1386. }
  1387. static int nvme_shutdown_ctrl(struct nvme_dev *dev)
  1388. {
  1389. unsigned long timeout;
  1390. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1391. dev->ctrl_config |= NVME_CC_SHN_NORMAL;
  1392. writel(dev->ctrl_config, &dev->bar->cc);
  1393. timeout = SHUTDOWN_TIMEOUT + jiffies;
  1394. while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
  1395. NVME_CSTS_SHST_CMPLT) {
  1396. msleep(100);
  1397. if (fatal_signal_pending(current))
  1398. return -EINTR;
  1399. if (time_after(jiffies, timeout)) {
  1400. dev_err(dev->dev,
  1401. "Device shutdown incomplete; abort shutdown\n");
  1402. return -ENODEV;
  1403. }
  1404. }
  1405. return 0;
  1406. }
  1407. static struct blk_mq_ops nvme_mq_admin_ops = {
  1408. .queue_rq = nvme_queue_rq,
  1409. .map_queue = blk_mq_map_queue,
  1410. .init_hctx = nvme_admin_init_hctx,
  1411. .exit_hctx = nvme_admin_exit_hctx,
  1412. .init_request = nvme_admin_init_request,
  1413. .timeout = nvme_timeout,
  1414. };
  1415. static struct blk_mq_ops nvme_mq_ops = {
  1416. .queue_rq = nvme_queue_rq,
  1417. .map_queue = blk_mq_map_queue,
  1418. .init_hctx = nvme_init_hctx,
  1419. .init_request = nvme_init_request,
  1420. .timeout = nvme_timeout,
  1421. };
  1422. static void nvme_dev_remove_admin(struct nvme_dev *dev)
  1423. {
  1424. if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
  1425. blk_cleanup_queue(dev->admin_q);
  1426. blk_mq_free_tag_set(&dev->admin_tagset);
  1427. }
  1428. }
  1429. static int nvme_alloc_admin_tags(struct nvme_dev *dev)
  1430. {
  1431. if (!dev->admin_q) {
  1432. dev->admin_tagset.ops = &nvme_mq_admin_ops;
  1433. dev->admin_tagset.nr_hw_queues = 1;
  1434. dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
  1435. dev->admin_tagset.reserved_tags = 1;
  1436. dev->admin_tagset.timeout = ADMIN_TIMEOUT;
  1437. dev->admin_tagset.numa_node = dev_to_node(dev->dev);
  1438. dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
  1439. dev->admin_tagset.driver_data = dev;
  1440. if (blk_mq_alloc_tag_set(&dev->admin_tagset))
  1441. return -ENOMEM;
  1442. dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
  1443. if (IS_ERR(dev->admin_q)) {
  1444. blk_mq_free_tag_set(&dev->admin_tagset);
  1445. return -ENOMEM;
  1446. }
  1447. if (!blk_get_queue(dev->admin_q)) {
  1448. nvme_dev_remove_admin(dev);
  1449. dev->admin_q = NULL;
  1450. return -ENODEV;
  1451. }
  1452. } else
  1453. blk_mq_unfreeze_queue(dev->admin_q);
  1454. return 0;
  1455. }
  1456. static int nvme_configure_admin_queue(struct nvme_dev *dev)
  1457. {
  1458. int result;
  1459. u32 aqa;
  1460. u64 cap = readq(&dev->bar->cap);
  1461. struct nvme_queue *nvmeq;
  1462. unsigned page_shift = PAGE_SHIFT;
  1463. unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
  1464. unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
  1465. if (page_shift < dev_page_min) {
  1466. dev_err(dev->dev,
  1467. "Minimum device page size (%u) too large for "
  1468. "host (%u)\n", 1 << dev_page_min,
  1469. 1 << page_shift);
  1470. return -ENODEV;
  1471. }
  1472. if (page_shift > dev_page_max) {
  1473. dev_info(dev->dev,
  1474. "Device maximum page size (%u) smaller than "
  1475. "host (%u); enabling work-around\n",
  1476. 1 << dev_page_max, 1 << page_shift);
  1477. page_shift = dev_page_max;
  1478. }
  1479. dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
  1480. NVME_CAP_NSSRC(cap) : 0;
  1481. if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
  1482. writel(NVME_CSTS_NSSRO, &dev->bar->csts);
  1483. result = nvme_disable_ctrl(dev, cap);
  1484. if (result < 0)
  1485. return result;
  1486. nvmeq = dev->queues[0];
  1487. if (!nvmeq) {
  1488. nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
  1489. if (!nvmeq)
  1490. return -ENOMEM;
  1491. }
  1492. aqa = nvmeq->q_depth - 1;
  1493. aqa |= aqa << 16;
  1494. dev->page_size = 1 << page_shift;
  1495. dev->ctrl_config = NVME_CC_CSS_NVM;
  1496. dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
  1497. dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
  1498. dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
  1499. writel(aqa, &dev->bar->aqa);
  1500. writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
  1501. writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
  1502. result = nvme_enable_ctrl(dev, cap);
  1503. if (result)
  1504. goto free_nvmeq;
  1505. nvmeq->cq_vector = 0;
  1506. result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
  1507. if (result) {
  1508. nvmeq->cq_vector = -1;
  1509. goto free_nvmeq;
  1510. }
  1511. return result;
  1512. free_nvmeq:
  1513. nvme_free_queues(dev, 0);
  1514. return result;
  1515. }
  1516. static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
  1517. {
  1518. struct nvme_dev *dev = ns->dev;
  1519. struct nvme_user_io io;
  1520. struct nvme_command c;
  1521. unsigned length, meta_len;
  1522. int status, write;
  1523. dma_addr_t meta_dma = 0;
  1524. void *meta = NULL;
  1525. void __user *metadata;
  1526. if (copy_from_user(&io, uio, sizeof(io)))
  1527. return -EFAULT;
  1528. switch (io.opcode) {
  1529. case nvme_cmd_write:
  1530. case nvme_cmd_read:
  1531. case nvme_cmd_compare:
  1532. break;
  1533. default:
  1534. return -EINVAL;
  1535. }
  1536. length = (io.nblocks + 1) << ns->lba_shift;
  1537. meta_len = (io.nblocks + 1) * ns->ms;
  1538. metadata = (void __user *)(uintptr_t)io.metadata;
  1539. write = io.opcode & 1;
  1540. if (ns->ext) {
  1541. length += meta_len;
  1542. meta_len = 0;
  1543. }
  1544. if (meta_len) {
  1545. if (((io.metadata & 3) || !io.metadata) && !ns->ext)
  1546. return -EINVAL;
  1547. meta = dma_alloc_coherent(dev->dev, meta_len,
  1548. &meta_dma, GFP_KERNEL);
  1549. if (!meta) {
  1550. status = -ENOMEM;
  1551. goto unmap;
  1552. }
  1553. if (write) {
  1554. if (copy_from_user(meta, metadata, meta_len)) {
  1555. status = -EFAULT;
  1556. goto unmap;
  1557. }
  1558. }
  1559. }
  1560. memset(&c, 0, sizeof(c));
  1561. c.rw.opcode = io.opcode;
  1562. c.rw.flags = io.flags;
  1563. c.rw.nsid = cpu_to_le32(ns->ns_id);
  1564. c.rw.slba = cpu_to_le64(io.slba);
  1565. c.rw.length = cpu_to_le16(io.nblocks);
  1566. c.rw.control = cpu_to_le16(io.control);
  1567. c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
  1568. c.rw.reftag = cpu_to_le32(io.reftag);
  1569. c.rw.apptag = cpu_to_le16(io.apptag);
  1570. c.rw.appmask = cpu_to_le16(io.appmask);
  1571. c.rw.metadata = cpu_to_le64(meta_dma);
  1572. status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
  1573. (void __user *)(uintptr_t)io.addr, length, NULL, 0);
  1574. unmap:
  1575. if (meta) {
  1576. if (status == NVME_SC_SUCCESS && !write) {
  1577. if (copy_to_user(metadata, meta, meta_len))
  1578. status = -EFAULT;
  1579. }
  1580. dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
  1581. }
  1582. return status;
  1583. }
  1584. static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
  1585. struct nvme_passthru_cmd __user *ucmd)
  1586. {
  1587. struct nvme_passthru_cmd cmd;
  1588. struct nvme_command c;
  1589. unsigned timeout = 0;
  1590. int status;
  1591. if (!capable(CAP_SYS_ADMIN))
  1592. return -EACCES;
  1593. if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
  1594. return -EFAULT;
  1595. memset(&c, 0, sizeof(c));
  1596. c.common.opcode = cmd.opcode;
  1597. c.common.flags = cmd.flags;
  1598. c.common.nsid = cpu_to_le32(cmd.nsid);
  1599. c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
  1600. c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
  1601. c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
  1602. c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
  1603. c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
  1604. c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
  1605. c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
  1606. c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
  1607. if (cmd.timeout_ms)
  1608. timeout = msecs_to_jiffies(cmd.timeout_ms);
  1609. status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
  1610. NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
  1611. &cmd.result, timeout);
  1612. if (status >= 0) {
  1613. if (put_user(cmd.result, &ucmd->result))
  1614. return -EFAULT;
  1615. }
  1616. return status;
  1617. }
  1618. static int nvme_subsys_reset(struct nvme_dev *dev)
  1619. {
  1620. if (!dev->subsystem)
  1621. return -ENOTTY;
  1622. writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
  1623. return 0;
  1624. }
  1625. static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
  1626. unsigned long arg)
  1627. {
  1628. struct nvme_ns *ns = bdev->bd_disk->private_data;
  1629. switch (cmd) {
  1630. case NVME_IOCTL_ID:
  1631. force_successful_syscall_return();
  1632. return ns->ns_id;
  1633. case NVME_IOCTL_ADMIN_CMD:
  1634. return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
  1635. case NVME_IOCTL_IO_CMD:
  1636. return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
  1637. case NVME_IOCTL_SUBMIT_IO:
  1638. return nvme_submit_io(ns, (void __user *)arg);
  1639. case SG_GET_VERSION_NUM:
  1640. return nvme_sg_get_version_num((void __user *)arg);
  1641. case SG_IO:
  1642. return nvme_sg_io(ns, (void __user *)arg);
  1643. default:
  1644. return -ENOTTY;
  1645. }
  1646. }
  1647. #ifdef CONFIG_COMPAT
  1648. static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
  1649. unsigned int cmd, unsigned long arg)
  1650. {
  1651. switch (cmd) {
  1652. case SG_IO:
  1653. return -ENOIOCTLCMD;
  1654. }
  1655. return nvme_ioctl(bdev, mode, cmd, arg);
  1656. }
  1657. #else
  1658. #define nvme_compat_ioctl NULL
  1659. #endif
  1660. static int nvme_open(struct block_device *bdev, fmode_t mode)
  1661. {
  1662. int ret = 0;
  1663. struct nvme_ns *ns;
  1664. spin_lock(&dev_list_lock);
  1665. ns = bdev->bd_disk->private_data;
  1666. if (!ns)
  1667. ret = -ENXIO;
  1668. else if (!kref_get_unless_zero(&ns->dev->kref))
  1669. ret = -ENXIO;
  1670. spin_unlock(&dev_list_lock);
  1671. return ret;
  1672. }
  1673. static void nvme_free_dev(struct kref *kref);
  1674. static void nvme_release(struct gendisk *disk, fmode_t mode)
  1675. {
  1676. struct nvme_ns *ns = disk->private_data;
  1677. struct nvme_dev *dev = ns->dev;
  1678. kref_put(&dev->kref, nvme_free_dev);
  1679. }
  1680. static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
  1681. {
  1682. /* some standard values */
  1683. geo->heads = 1 << 6;
  1684. geo->sectors = 1 << 5;
  1685. geo->cylinders = get_capacity(bd->bd_disk) >> 11;
  1686. return 0;
  1687. }
  1688. static void nvme_config_discard(struct nvme_ns *ns)
  1689. {
  1690. u32 logical_block_size = queue_logical_block_size(ns->queue);
  1691. ns->queue->limits.discard_zeroes_data = 0;
  1692. ns->queue->limits.discard_alignment = logical_block_size;
  1693. ns->queue->limits.discard_granularity = logical_block_size;
  1694. blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
  1695. queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
  1696. }
  1697. static int nvme_revalidate_disk(struct gendisk *disk)
  1698. {
  1699. struct nvme_ns *ns = disk->private_data;
  1700. struct nvme_dev *dev = ns->dev;
  1701. struct nvme_id_ns *id;
  1702. u8 lbaf, pi_type;
  1703. u16 old_ms;
  1704. unsigned short bs;
  1705. if (nvme_identify_ns(dev, ns->ns_id, &id)) {
  1706. dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
  1707. dev->instance, ns->ns_id);
  1708. return -ENODEV;
  1709. }
  1710. if (id->ncap == 0) {
  1711. kfree(id);
  1712. return -ENODEV;
  1713. }
  1714. old_ms = ns->ms;
  1715. lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
  1716. ns->lba_shift = id->lbaf[lbaf].ds;
  1717. ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
  1718. ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
  1719. /*
  1720. * If identify namespace failed, use default 512 byte block size so
  1721. * block layer can use before failing read/write for 0 capacity.
  1722. */
  1723. if (ns->lba_shift == 0)
  1724. ns->lba_shift = 9;
  1725. bs = 1 << ns->lba_shift;
  1726. /* XXX: PI implementation requires metadata equal t10 pi tuple size */
  1727. pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
  1728. id->dps & NVME_NS_DPS_PI_MASK : 0;
  1729. if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
  1730. ns->ms != old_ms ||
  1731. bs != queue_logical_block_size(disk->queue) ||
  1732. (ns->ms && ns->ext)))
  1733. blk_integrity_unregister(disk);
  1734. ns->pi_type = pi_type;
  1735. blk_queue_logical_block_size(ns->queue, bs);
  1736. if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
  1737. !ns->ext)
  1738. nvme_init_integrity(ns);
  1739. if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
  1740. set_capacity(disk, 0);
  1741. else
  1742. set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
  1743. if (dev->oncs & NVME_CTRL_ONCS_DSM)
  1744. nvme_config_discard(ns);
  1745. kfree(id);
  1746. return 0;
  1747. }
  1748. static const struct block_device_operations nvme_fops = {
  1749. .owner = THIS_MODULE,
  1750. .ioctl = nvme_ioctl,
  1751. .compat_ioctl = nvme_compat_ioctl,
  1752. .open = nvme_open,
  1753. .release = nvme_release,
  1754. .getgeo = nvme_getgeo,
  1755. .revalidate_disk= nvme_revalidate_disk,
  1756. };
  1757. static int nvme_kthread(void *data)
  1758. {
  1759. struct nvme_dev *dev, *next;
  1760. while (!kthread_should_stop()) {
  1761. set_current_state(TASK_INTERRUPTIBLE);
  1762. spin_lock(&dev_list_lock);
  1763. list_for_each_entry_safe(dev, next, &dev_list, node) {
  1764. int i;
  1765. u32 csts = readl(&dev->bar->csts);
  1766. if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
  1767. csts & NVME_CSTS_CFS) {
  1768. if (work_busy(&dev->reset_work))
  1769. continue;
  1770. list_del_init(&dev->node);
  1771. dev_warn(dev->dev,
  1772. "Failed status: %x, reset controller\n",
  1773. readl(&dev->bar->csts));
  1774. dev->reset_workfn = nvme_reset_failed_dev;
  1775. queue_work(nvme_workq, &dev->reset_work);
  1776. continue;
  1777. }
  1778. for (i = 0; i < dev->queue_count; i++) {
  1779. struct nvme_queue *nvmeq = dev->queues[i];
  1780. if (!nvmeq)
  1781. continue;
  1782. spin_lock_irq(&nvmeq->q_lock);
  1783. nvme_process_cq(nvmeq);
  1784. while ((i == 0) && (dev->event_limit > 0)) {
  1785. if (nvme_submit_async_admin_req(dev))
  1786. break;
  1787. dev->event_limit--;
  1788. }
  1789. spin_unlock_irq(&nvmeq->q_lock);
  1790. }
  1791. }
  1792. spin_unlock(&dev_list_lock);
  1793. schedule_timeout(round_jiffies_relative(HZ));
  1794. }
  1795. return 0;
  1796. }
  1797. static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
  1798. {
  1799. struct nvme_ns *ns;
  1800. struct gendisk *disk;
  1801. int node = dev_to_node(dev->dev);
  1802. ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
  1803. if (!ns)
  1804. return;
  1805. ns->queue = blk_mq_init_queue(&dev->tagset);
  1806. if (IS_ERR(ns->queue))
  1807. goto out_free_ns;
  1808. queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
  1809. queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
  1810. ns->dev = dev;
  1811. ns->queue->queuedata = ns;
  1812. disk = alloc_disk_node(0, node);
  1813. if (!disk)
  1814. goto out_free_queue;
  1815. ns->ns_id = nsid;
  1816. ns->disk = disk;
  1817. ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
  1818. list_add_tail(&ns->list, &dev->namespaces);
  1819. blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
  1820. if (dev->max_hw_sectors) {
  1821. blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
  1822. blk_queue_max_segments(ns->queue,
  1823. ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
  1824. }
  1825. if (dev->stripe_size)
  1826. blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
  1827. if (dev->vwc & NVME_CTRL_VWC_PRESENT)
  1828. blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
  1829. blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
  1830. disk->major = nvme_major;
  1831. disk->first_minor = 0;
  1832. disk->fops = &nvme_fops;
  1833. disk->private_data = ns;
  1834. disk->queue = ns->queue;
  1835. disk->driverfs_dev = dev->device;
  1836. disk->flags = GENHD_FL_EXT_DEVT;
  1837. sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
  1838. /*
  1839. * Initialize capacity to 0 until we establish the namespace format and
  1840. * setup integrity extentions if necessary. The revalidate_disk after
  1841. * add_disk allows the driver to register with integrity if the format
  1842. * requires it.
  1843. */
  1844. set_capacity(disk, 0);
  1845. if (nvme_revalidate_disk(ns->disk))
  1846. goto out_free_disk;
  1847. add_disk(ns->disk);
  1848. if (ns->ms) {
  1849. struct block_device *bd = bdget_disk(ns->disk, 0);
  1850. if (!bd)
  1851. return;
  1852. if (blkdev_get(bd, FMODE_READ, NULL)) {
  1853. bdput(bd);
  1854. return;
  1855. }
  1856. blkdev_reread_part(bd);
  1857. blkdev_put(bd, FMODE_READ);
  1858. }
  1859. return;
  1860. out_free_disk:
  1861. kfree(disk);
  1862. list_del(&ns->list);
  1863. out_free_queue:
  1864. blk_cleanup_queue(ns->queue);
  1865. out_free_ns:
  1866. kfree(ns);
  1867. }
  1868. static void nvme_create_io_queues(struct nvme_dev *dev)
  1869. {
  1870. unsigned i;
  1871. for (i = dev->queue_count; i <= dev->max_qid; i++)
  1872. if (!nvme_alloc_queue(dev, i, dev->q_depth))
  1873. break;
  1874. for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
  1875. if (nvme_create_queue(dev->queues[i], i))
  1876. break;
  1877. }
  1878. static int set_queue_count(struct nvme_dev *dev, int count)
  1879. {
  1880. int status;
  1881. u32 result;
  1882. u32 q_count = (count - 1) | ((count - 1) << 16);
  1883. status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
  1884. &result);
  1885. if (status < 0)
  1886. return status;
  1887. if (status > 0) {
  1888. dev_err(dev->dev, "Could not set queue count (%d)\n", status);
  1889. return 0;
  1890. }
  1891. return min(result & 0xffff, result >> 16) + 1;
  1892. }
  1893. static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
  1894. {
  1895. u64 szu, size, offset;
  1896. u32 cmbloc;
  1897. resource_size_t bar_size;
  1898. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1899. void __iomem *cmb;
  1900. dma_addr_t dma_addr;
  1901. if (!use_cmb_sqes)
  1902. return NULL;
  1903. dev->cmbsz = readl(&dev->bar->cmbsz);
  1904. if (!(NVME_CMB_SZ(dev->cmbsz)))
  1905. return NULL;
  1906. cmbloc = readl(&dev->bar->cmbloc);
  1907. szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
  1908. size = szu * NVME_CMB_SZ(dev->cmbsz);
  1909. offset = szu * NVME_CMB_OFST(cmbloc);
  1910. bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
  1911. if (offset > bar_size)
  1912. return NULL;
  1913. /*
  1914. * Controllers may support a CMB size larger than their BAR,
  1915. * for example, due to being behind a bridge. Reduce the CMB to
  1916. * the reported size of the BAR
  1917. */
  1918. if (size > bar_size - offset)
  1919. size = bar_size - offset;
  1920. dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
  1921. cmb = ioremap_wc(dma_addr, size);
  1922. if (!cmb)
  1923. return NULL;
  1924. dev->cmb_dma_addr = dma_addr;
  1925. dev->cmb_size = size;
  1926. return cmb;
  1927. }
  1928. static inline void nvme_release_cmb(struct nvme_dev *dev)
  1929. {
  1930. if (dev->cmb) {
  1931. iounmap(dev->cmb);
  1932. dev->cmb = NULL;
  1933. }
  1934. }
  1935. static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
  1936. {
  1937. return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
  1938. }
  1939. static int nvme_setup_io_queues(struct nvme_dev *dev)
  1940. {
  1941. struct nvme_queue *adminq = dev->queues[0];
  1942. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1943. int result, i, vecs, nr_io_queues, size;
  1944. nr_io_queues = num_possible_cpus();
  1945. result = set_queue_count(dev, nr_io_queues);
  1946. if (result <= 0)
  1947. return result;
  1948. if (result < nr_io_queues)
  1949. nr_io_queues = result;
  1950. if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
  1951. result = nvme_cmb_qdepth(dev, nr_io_queues,
  1952. sizeof(struct nvme_command));
  1953. if (result > 0)
  1954. dev->q_depth = result;
  1955. else
  1956. nvme_release_cmb(dev);
  1957. }
  1958. size = db_bar_size(dev, nr_io_queues);
  1959. if (size > 8192) {
  1960. iounmap(dev->bar);
  1961. do {
  1962. dev->bar = ioremap(pci_resource_start(pdev, 0), size);
  1963. if (dev->bar)
  1964. break;
  1965. if (!--nr_io_queues)
  1966. return -ENOMEM;
  1967. size = db_bar_size(dev, nr_io_queues);
  1968. } while (1);
  1969. dev->dbs = ((void __iomem *)dev->bar) + 4096;
  1970. adminq->q_db = dev->dbs;
  1971. }
  1972. /* Deregister the admin queue's interrupt */
  1973. free_irq(dev->entry[0].vector, adminq);
  1974. /*
  1975. * If we enable msix early due to not intx, disable it again before
  1976. * setting up the full range we need.
  1977. */
  1978. if (!pdev->irq)
  1979. pci_disable_msix(pdev);
  1980. for (i = 0; i < nr_io_queues; i++)
  1981. dev->entry[i].entry = i;
  1982. vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
  1983. if (vecs < 0) {
  1984. vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
  1985. if (vecs < 0) {
  1986. vecs = 1;
  1987. } else {
  1988. for (i = 0; i < vecs; i++)
  1989. dev->entry[i].vector = i + pdev->irq;
  1990. }
  1991. }
  1992. /*
  1993. * Should investigate if there's a performance win from allocating
  1994. * more queues than interrupt vectors; it might allow the submission
  1995. * path to scale better, even if the receive path is limited by the
  1996. * number of interrupts.
  1997. */
  1998. nr_io_queues = vecs;
  1999. dev->max_qid = nr_io_queues;
  2000. result = queue_request_irq(dev, adminq, adminq->irqname);
  2001. if (result) {
  2002. adminq->cq_vector = -1;
  2003. goto free_queues;
  2004. }
  2005. /* Free previously allocated queues that are no longer usable */
  2006. nvme_free_queues(dev, nr_io_queues + 1);
  2007. nvme_create_io_queues(dev);
  2008. return 0;
  2009. free_queues:
  2010. nvme_free_queues(dev, 1);
  2011. return result;
  2012. }
  2013. static void nvme_free_namespace(struct nvme_ns *ns)
  2014. {
  2015. list_del(&ns->list);
  2016. spin_lock(&dev_list_lock);
  2017. ns->disk->private_data = NULL;
  2018. spin_unlock(&dev_list_lock);
  2019. put_disk(ns->disk);
  2020. kfree(ns);
  2021. }
  2022. static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
  2023. {
  2024. struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
  2025. struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
  2026. return nsa->ns_id - nsb->ns_id;
  2027. }
  2028. static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
  2029. {
  2030. struct nvme_ns *ns;
  2031. list_for_each_entry(ns, &dev->namespaces, list) {
  2032. if (ns->ns_id == nsid)
  2033. return ns;
  2034. if (ns->ns_id > nsid)
  2035. break;
  2036. }
  2037. return NULL;
  2038. }
  2039. static inline bool nvme_io_incapable(struct nvme_dev *dev)
  2040. {
  2041. return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
  2042. dev->online_queues < 2);
  2043. }
  2044. static void nvme_ns_remove(struct nvme_ns *ns)
  2045. {
  2046. bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
  2047. if (kill)
  2048. blk_set_queue_dying(ns->queue);
  2049. if (ns->disk->flags & GENHD_FL_UP) {
  2050. if (blk_get_integrity(ns->disk))
  2051. blk_integrity_unregister(ns->disk);
  2052. del_gendisk(ns->disk);
  2053. }
  2054. if (kill || !blk_queue_dying(ns->queue)) {
  2055. blk_mq_abort_requeue_list(ns->queue);
  2056. blk_cleanup_queue(ns->queue);
  2057. }
  2058. }
  2059. static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
  2060. {
  2061. struct nvme_ns *ns, *next;
  2062. unsigned i;
  2063. for (i = 1; i <= nn; i++) {
  2064. ns = nvme_find_ns(dev, i);
  2065. if (ns) {
  2066. if (revalidate_disk(ns->disk)) {
  2067. nvme_ns_remove(ns);
  2068. nvme_free_namespace(ns);
  2069. }
  2070. } else
  2071. nvme_alloc_ns(dev, i);
  2072. }
  2073. list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
  2074. if (ns->ns_id > nn) {
  2075. nvme_ns_remove(ns);
  2076. nvme_free_namespace(ns);
  2077. }
  2078. }
  2079. list_sort(NULL, &dev->namespaces, ns_cmp);
  2080. }
  2081. static void nvme_set_irq_hints(struct nvme_dev *dev)
  2082. {
  2083. struct nvme_queue *nvmeq;
  2084. int i;
  2085. for (i = 0; i < dev->online_queues; i++) {
  2086. nvmeq = dev->queues[i];
  2087. if (!nvmeq->tags || !(*nvmeq->tags))
  2088. continue;
  2089. irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
  2090. blk_mq_tags_cpumask(*nvmeq->tags));
  2091. }
  2092. }
  2093. static void nvme_dev_scan(struct work_struct *work)
  2094. {
  2095. struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
  2096. struct nvme_id_ctrl *ctrl;
  2097. if (!dev->tagset.tags)
  2098. return;
  2099. if (nvme_identify_ctrl(dev, &ctrl))
  2100. return;
  2101. nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
  2102. kfree(ctrl);
  2103. nvme_set_irq_hints(dev);
  2104. }
  2105. /*
  2106. * Return: error value if an error occurred setting up the queues or calling
  2107. * Identify Device. 0 if these succeeded, even if adding some of the
  2108. * namespaces failed. At the moment, these failures are silent. TBD which
  2109. * failures should be reported.
  2110. */
  2111. static int nvme_dev_add(struct nvme_dev *dev)
  2112. {
  2113. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2114. int res;
  2115. struct nvme_id_ctrl *ctrl;
  2116. int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
  2117. res = nvme_identify_ctrl(dev, &ctrl);
  2118. if (res) {
  2119. dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
  2120. return -EIO;
  2121. }
  2122. dev->oncs = le16_to_cpup(&ctrl->oncs);
  2123. dev->abort_limit = ctrl->acl + 1;
  2124. dev->vwc = ctrl->vwc;
  2125. memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
  2126. memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
  2127. memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
  2128. if (ctrl->mdts)
  2129. dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
  2130. if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
  2131. (pdev->device == 0x0953) && ctrl->vs[3]) {
  2132. unsigned int max_hw_sectors;
  2133. dev->stripe_size = 1 << (ctrl->vs[3] + shift);
  2134. max_hw_sectors = dev->stripe_size >> (shift - 9);
  2135. if (dev->max_hw_sectors) {
  2136. dev->max_hw_sectors = min(max_hw_sectors,
  2137. dev->max_hw_sectors);
  2138. } else
  2139. dev->max_hw_sectors = max_hw_sectors;
  2140. }
  2141. kfree(ctrl);
  2142. if (!dev->tagset.tags) {
  2143. dev->tagset.ops = &nvme_mq_ops;
  2144. dev->tagset.nr_hw_queues = dev->online_queues - 1;
  2145. dev->tagset.timeout = NVME_IO_TIMEOUT;
  2146. dev->tagset.numa_node = dev_to_node(dev->dev);
  2147. dev->tagset.queue_depth =
  2148. min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
  2149. dev->tagset.cmd_size = nvme_cmd_size(dev);
  2150. dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
  2151. dev->tagset.driver_data = dev;
  2152. if (blk_mq_alloc_tag_set(&dev->tagset))
  2153. return 0;
  2154. }
  2155. schedule_work(&dev->scan_work);
  2156. return 0;
  2157. }
  2158. static int nvme_dev_map(struct nvme_dev *dev)
  2159. {
  2160. u64 cap;
  2161. int bars, result = -ENOMEM;
  2162. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2163. if (pci_enable_device_mem(pdev))
  2164. return result;
  2165. dev->entry[0].vector = pdev->irq;
  2166. pci_set_master(pdev);
  2167. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  2168. if (!bars)
  2169. goto disable_pci;
  2170. if (pci_request_selected_regions(pdev, bars, "nvme"))
  2171. goto disable_pci;
  2172. if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
  2173. dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
  2174. goto disable;
  2175. dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
  2176. if (!dev->bar)
  2177. goto disable;
  2178. if (readl(&dev->bar->csts) == -1) {
  2179. result = -ENODEV;
  2180. goto unmap;
  2181. }
  2182. /*
  2183. * Some devices don't advertse INTx interrupts, pre-enable a single
  2184. * MSIX vec for setup. We'll adjust this later.
  2185. */
  2186. if (!pdev->irq) {
  2187. result = pci_enable_msix(pdev, dev->entry, 1);
  2188. if (result < 0)
  2189. goto unmap;
  2190. }
  2191. cap = readq(&dev->bar->cap);
  2192. dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
  2193. dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
  2194. dev->dbs = ((void __iomem *)dev->bar) + 4096;
  2195. if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
  2196. dev->cmb = nvme_map_cmb(dev);
  2197. return 0;
  2198. unmap:
  2199. iounmap(dev->bar);
  2200. dev->bar = NULL;
  2201. disable:
  2202. pci_release_regions(pdev);
  2203. disable_pci:
  2204. pci_disable_device(pdev);
  2205. return result;
  2206. }
  2207. static void nvme_dev_unmap(struct nvme_dev *dev)
  2208. {
  2209. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2210. if (pdev->msi_enabled)
  2211. pci_disable_msi(pdev);
  2212. else if (pdev->msix_enabled)
  2213. pci_disable_msix(pdev);
  2214. if (dev->bar) {
  2215. iounmap(dev->bar);
  2216. dev->bar = NULL;
  2217. pci_release_regions(pdev);
  2218. }
  2219. if (pci_is_enabled(pdev))
  2220. pci_disable_device(pdev);
  2221. }
  2222. struct nvme_delq_ctx {
  2223. struct task_struct *waiter;
  2224. struct kthread_worker *worker;
  2225. atomic_t refcount;
  2226. };
  2227. static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
  2228. {
  2229. dq->waiter = current;
  2230. mb();
  2231. for (;;) {
  2232. set_current_state(TASK_KILLABLE);
  2233. if (!atomic_read(&dq->refcount))
  2234. break;
  2235. if (!schedule_timeout(ADMIN_TIMEOUT) ||
  2236. fatal_signal_pending(current)) {
  2237. /*
  2238. * Disable the controller first since we can't trust it
  2239. * at this point, but leave the admin queue enabled
  2240. * until all queue deletion requests are flushed.
  2241. * FIXME: This may take a while if there are more h/w
  2242. * queues than admin tags.
  2243. */
  2244. set_current_state(TASK_RUNNING);
  2245. nvme_disable_ctrl(dev, readq(&dev->bar->cap));
  2246. nvme_clear_queue(dev->queues[0]);
  2247. flush_kthread_worker(dq->worker);
  2248. nvme_disable_queue(dev, 0);
  2249. return;
  2250. }
  2251. }
  2252. set_current_state(TASK_RUNNING);
  2253. }
  2254. static void nvme_put_dq(struct nvme_delq_ctx *dq)
  2255. {
  2256. atomic_dec(&dq->refcount);
  2257. if (dq->waiter)
  2258. wake_up_process(dq->waiter);
  2259. }
  2260. static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
  2261. {
  2262. atomic_inc(&dq->refcount);
  2263. return dq;
  2264. }
  2265. static void nvme_del_queue_end(struct nvme_queue *nvmeq)
  2266. {
  2267. struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
  2268. nvme_put_dq(dq);
  2269. }
  2270. static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
  2271. kthread_work_func_t fn)
  2272. {
  2273. struct nvme_command c;
  2274. memset(&c, 0, sizeof(c));
  2275. c.delete_queue.opcode = opcode;
  2276. c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
  2277. init_kthread_work(&nvmeq->cmdinfo.work, fn);
  2278. return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
  2279. ADMIN_TIMEOUT);
  2280. }
  2281. static void nvme_del_cq_work_handler(struct kthread_work *work)
  2282. {
  2283. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2284. cmdinfo.work);
  2285. nvme_del_queue_end(nvmeq);
  2286. }
  2287. static int nvme_delete_cq(struct nvme_queue *nvmeq)
  2288. {
  2289. return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
  2290. nvme_del_cq_work_handler);
  2291. }
  2292. static void nvme_del_sq_work_handler(struct kthread_work *work)
  2293. {
  2294. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2295. cmdinfo.work);
  2296. int status = nvmeq->cmdinfo.status;
  2297. if (!status)
  2298. status = nvme_delete_cq(nvmeq);
  2299. if (status)
  2300. nvme_del_queue_end(nvmeq);
  2301. }
  2302. static int nvme_delete_sq(struct nvme_queue *nvmeq)
  2303. {
  2304. return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
  2305. nvme_del_sq_work_handler);
  2306. }
  2307. static void nvme_del_queue_start(struct kthread_work *work)
  2308. {
  2309. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2310. cmdinfo.work);
  2311. if (nvme_delete_sq(nvmeq))
  2312. nvme_del_queue_end(nvmeq);
  2313. }
  2314. static void nvme_disable_io_queues(struct nvme_dev *dev)
  2315. {
  2316. int i;
  2317. DEFINE_KTHREAD_WORKER_ONSTACK(worker);
  2318. struct nvme_delq_ctx dq;
  2319. struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
  2320. &worker, "nvme%d", dev->instance);
  2321. if (IS_ERR(kworker_task)) {
  2322. dev_err(dev->dev,
  2323. "Failed to create queue del task\n");
  2324. for (i = dev->queue_count - 1; i > 0; i--)
  2325. nvme_disable_queue(dev, i);
  2326. return;
  2327. }
  2328. dq.waiter = NULL;
  2329. atomic_set(&dq.refcount, 0);
  2330. dq.worker = &worker;
  2331. for (i = dev->queue_count - 1; i > 0; i--) {
  2332. struct nvme_queue *nvmeq = dev->queues[i];
  2333. if (nvme_suspend_queue(nvmeq))
  2334. continue;
  2335. nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
  2336. nvmeq->cmdinfo.worker = dq.worker;
  2337. init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
  2338. queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
  2339. }
  2340. nvme_wait_dq(&dq, dev);
  2341. kthread_stop(kworker_task);
  2342. }
  2343. /*
  2344. * Remove the node from the device list and check
  2345. * for whether or not we need to stop the nvme_thread.
  2346. */
  2347. static void nvme_dev_list_remove(struct nvme_dev *dev)
  2348. {
  2349. struct task_struct *tmp = NULL;
  2350. spin_lock(&dev_list_lock);
  2351. list_del_init(&dev->node);
  2352. if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
  2353. tmp = nvme_thread;
  2354. nvme_thread = NULL;
  2355. }
  2356. spin_unlock(&dev_list_lock);
  2357. if (tmp)
  2358. kthread_stop(tmp);
  2359. }
  2360. static void nvme_freeze_queues(struct nvme_dev *dev)
  2361. {
  2362. struct nvme_ns *ns;
  2363. list_for_each_entry(ns, &dev->namespaces, list) {
  2364. blk_mq_freeze_queue_start(ns->queue);
  2365. spin_lock_irq(ns->queue->queue_lock);
  2366. queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
  2367. spin_unlock_irq(ns->queue->queue_lock);
  2368. blk_mq_cancel_requeue_work(ns->queue);
  2369. blk_mq_stop_hw_queues(ns->queue);
  2370. }
  2371. }
  2372. static void nvme_unfreeze_queues(struct nvme_dev *dev)
  2373. {
  2374. struct nvme_ns *ns;
  2375. list_for_each_entry(ns, &dev->namespaces, list) {
  2376. queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
  2377. blk_mq_unfreeze_queue(ns->queue);
  2378. blk_mq_start_stopped_hw_queues(ns->queue, true);
  2379. blk_mq_kick_requeue_list(ns->queue);
  2380. }
  2381. }
  2382. static void nvme_dev_shutdown(struct nvme_dev *dev)
  2383. {
  2384. int i;
  2385. u32 csts = -1;
  2386. nvme_dev_list_remove(dev);
  2387. if (dev->bar) {
  2388. nvme_freeze_queues(dev);
  2389. csts = readl(&dev->bar->csts);
  2390. }
  2391. if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
  2392. for (i = dev->queue_count - 1; i >= 0; i--) {
  2393. struct nvme_queue *nvmeq = dev->queues[i];
  2394. nvme_suspend_queue(nvmeq);
  2395. }
  2396. } else {
  2397. nvme_disable_io_queues(dev);
  2398. nvme_shutdown_ctrl(dev);
  2399. nvme_disable_queue(dev, 0);
  2400. }
  2401. nvme_dev_unmap(dev);
  2402. for (i = dev->queue_count - 1; i >= 0; i--)
  2403. nvme_clear_queue(dev->queues[i]);
  2404. }
  2405. static void nvme_dev_remove(struct nvme_dev *dev)
  2406. {
  2407. struct nvme_ns *ns;
  2408. list_for_each_entry(ns, &dev->namespaces, list)
  2409. nvme_ns_remove(ns);
  2410. }
  2411. static int nvme_setup_prp_pools(struct nvme_dev *dev)
  2412. {
  2413. dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
  2414. PAGE_SIZE, PAGE_SIZE, 0);
  2415. if (!dev->prp_page_pool)
  2416. return -ENOMEM;
  2417. /* Optimisation for I/Os between 4k and 128k */
  2418. dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
  2419. 256, 256, 0);
  2420. if (!dev->prp_small_pool) {
  2421. dma_pool_destroy(dev->prp_page_pool);
  2422. return -ENOMEM;
  2423. }
  2424. return 0;
  2425. }
  2426. static void nvme_release_prp_pools(struct nvme_dev *dev)
  2427. {
  2428. dma_pool_destroy(dev->prp_page_pool);
  2429. dma_pool_destroy(dev->prp_small_pool);
  2430. }
  2431. static DEFINE_IDA(nvme_instance_ida);
  2432. static int nvme_set_instance(struct nvme_dev *dev)
  2433. {
  2434. int instance, error;
  2435. do {
  2436. if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
  2437. return -ENODEV;
  2438. spin_lock(&dev_list_lock);
  2439. error = ida_get_new(&nvme_instance_ida, &instance);
  2440. spin_unlock(&dev_list_lock);
  2441. } while (error == -EAGAIN);
  2442. if (error)
  2443. return -ENODEV;
  2444. dev->instance = instance;
  2445. return 0;
  2446. }
  2447. static void nvme_release_instance(struct nvme_dev *dev)
  2448. {
  2449. spin_lock(&dev_list_lock);
  2450. ida_remove(&nvme_instance_ida, dev->instance);
  2451. spin_unlock(&dev_list_lock);
  2452. }
  2453. static void nvme_free_namespaces(struct nvme_dev *dev)
  2454. {
  2455. struct nvme_ns *ns, *next;
  2456. list_for_each_entry_safe(ns, next, &dev->namespaces, list)
  2457. nvme_free_namespace(ns);
  2458. }
  2459. static void nvme_free_dev(struct kref *kref)
  2460. {
  2461. struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
  2462. put_device(dev->dev);
  2463. put_device(dev->device);
  2464. nvme_free_namespaces(dev);
  2465. nvme_release_instance(dev);
  2466. if (dev->tagset.tags)
  2467. blk_mq_free_tag_set(&dev->tagset);
  2468. if (dev->admin_q)
  2469. blk_put_queue(dev->admin_q);
  2470. kfree(dev->queues);
  2471. kfree(dev->entry);
  2472. kfree(dev);
  2473. }
  2474. static int nvme_dev_open(struct inode *inode, struct file *f)
  2475. {
  2476. struct nvme_dev *dev;
  2477. int instance = iminor(inode);
  2478. int ret = -ENODEV;
  2479. spin_lock(&dev_list_lock);
  2480. list_for_each_entry(dev, &dev_list, node) {
  2481. if (dev->instance == instance) {
  2482. if (!dev->admin_q) {
  2483. ret = -EWOULDBLOCK;
  2484. break;
  2485. }
  2486. if (!kref_get_unless_zero(&dev->kref))
  2487. break;
  2488. f->private_data = dev;
  2489. ret = 0;
  2490. break;
  2491. }
  2492. }
  2493. spin_unlock(&dev_list_lock);
  2494. return ret;
  2495. }
  2496. static int nvme_dev_release(struct inode *inode, struct file *f)
  2497. {
  2498. struct nvme_dev *dev = f->private_data;
  2499. kref_put(&dev->kref, nvme_free_dev);
  2500. return 0;
  2501. }
  2502. static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
  2503. {
  2504. struct nvme_dev *dev = f->private_data;
  2505. struct nvme_ns *ns;
  2506. switch (cmd) {
  2507. case NVME_IOCTL_ADMIN_CMD:
  2508. return nvme_user_cmd(dev, NULL, (void __user *)arg);
  2509. case NVME_IOCTL_IO_CMD:
  2510. if (list_empty(&dev->namespaces))
  2511. return -ENOTTY;
  2512. ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
  2513. return nvme_user_cmd(dev, ns, (void __user *)arg);
  2514. case NVME_IOCTL_RESET:
  2515. dev_warn(dev->dev, "resetting controller\n");
  2516. return nvme_reset(dev);
  2517. case NVME_IOCTL_SUBSYS_RESET:
  2518. return nvme_subsys_reset(dev);
  2519. default:
  2520. return -ENOTTY;
  2521. }
  2522. }
  2523. static const struct file_operations nvme_dev_fops = {
  2524. .owner = THIS_MODULE,
  2525. .open = nvme_dev_open,
  2526. .release = nvme_dev_release,
  2527. .unlocked_ioctl = nvme_dev_ioctl,
  2528. .compat_ioctl = nvme_dev_ioctl,
  2529. };
  2530. static int nvme_dev_start(struct nvme_dev *dev)
  2531. {
  2532. int result;
  2533. bool start_thread = false;
  2534. result = nvme_dev_map(dev);
  2535. if (result)
  2536. return result;
  2537. result = nvme_configure_admin_queue(dev);
  2538. if (result)
  2539. goto unmap;
  2540. spin_lock(&dev_list_lock);
  2541. if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
  2542. start_thread = true;
  2543. nvme_thread = NULL;
  2544. }
  2545. list_add(&dev->node, &dev_list);
  2546. spin_unlock(&dev_list_lock);
  2547. if (start_thread) {
  2548. nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
  2549. wake_up_all(&nvme_kthread_wait);
  2550. } else
  2551. wait_event_killable(nvme_kthread_wait, nvme_thread);
  2552. if (IS_ERR_OR_NULL(nvme_thread)) {
  2553. result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
  2554. goto disable;
  2555. }
  2556. nvme_init_queue(dev->queues[0], 0);
  2557. result = nvme_alloc_admin_tags(dev);
  2558. if (result)
  2559. goto disable;
  2560. result = nvme_setup_io_queues(dev);
  2561. if (result)
  2562. goto free_tags;
  2563. dev->event_limit = 1;
  2564. return result;
  2565. free_tags:
  2566. nvme_dev_remove_admin(dev);
  2567. blk_put_queue(dev->admin_q);
  2568. dev->admin_q = NULL;
  2569. dev->queues[0]->tags = NULL;
  2570. disable:
  2571. nvme_disable_queue(dev, 0);
  2572. nvme_dev_list_remove(dev);
  2573. unmap:
  2574. nvme_dev_unmap(dev);
  2575. return result;
  2576. }
  2577. static int nvme_remove_dead_ctrl(void *arg)
  2578. {
  2579. struct nvme_dev *dev = (struct nvme_dev *)arg;
  2580. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2581. if (pci_get_drvdata(pdev))
  2582. pci_stop_and_remove_bus_device_locked(pdev);
  2583. kref_put(&dev->kref, nvme_free_dev);
  2584. return 0;
  2585. }
  2586. static void nvme_remove_disks(struct work_struct *ws)
  2587. {
  2588. struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
  2589. nvme_free_queues(dev, 1);
  2590. nvme_dev_remove(dev);
  2591. }
  2592. static int nvme_dev_resume(struct nvme_dev *dev)
  2593. {
  2594. int ret;
  2595. ret = nvme_dev_start(dev);
  2596. if (ret)
  2597. return ret;
  2598. if (dev->online_queues < 2) {
  2599. spin_lock(&dev_list_lock);
  2600. dev->reset_workfn = nvme_remove_disks;
  2601. queue_work(nvme_workq, &dev->reset_work);
  2602. spin_unlock(&dev_list_lock);
  2603. } else {
  2604. nvme_unfreeze_queues(dev);
  2605. nvme_dev_add(dev);
  2606. }
  2607. return 0;
  2608. }
  2609. static void nvme_dead_ctrl(struct nvme_dev *dev)
  2610. {
  2611. dev_warn(dev->dev, "Device failed to resume\n");
  2612. kref_get(&dev->kref);
  2613. if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
  2614. dev->instance))) {
  2615. dev_err(dev->dev,
  2616. "Failed to start controller remove task\n");
  2617. kref_put(&dev->kref, nvme_free_dev);
  2618. }
  2619. }
  2620. static void nvme_dev_reset(struct nvme_dev *dev)
  2621. {
  2622. bool in_probe = work_busy(&dev->probe_work);
  2623. nvme_dev_shutdown(dev);
  2624. /* Synchronize with device probe so that work will see failure status
  2625. * and exit gracefully without trying to schedule another reset */
  2626. flush_work(&dev->probe_work);
  2627. /* Fail this device if reset occured during probe to avoid
  2628. * infinite initialization loops. */
  2629. if (in_probe) {
  2630. nvme_dead_ctrl(dev);
  2631. return;
  2632. }
  2633. /* Schedule device resume asynchronously so the reset work is available
  2634. * to cleanup errors that may occur during reinitialization */
  2635. schedule_work(&dev->probe_work);
  2636. }
  2637. static void nvme_reset_failed_dev(struct work_struct *ws)
  2638. {
  2639. struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
  2640. nvme_dev_reset(dev);
  2641. }
  2642. static void nvme_reset_workfn(struct work_struct *work)
  2643. {
  2644. struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
  2645. dev->reset_workfn(work);
  2646. }
  2647. static int nvme_reset(struct nvme_dev *dev)
  2648. {
  2649. int ret = -EBUSY;
  2650. if (!dev->admin_q || blk_queue_dying(dev->admin_q))
  2651. return -ENODEV;
  2652. spin_lock(&dev_list_lock);
  2653. if (!work_pending(&dev->reset_work)) {
  2654. dev->reset_workfn = nvme_reset_failed_dev;
  2655. queue_work(nvme_workq, &dev->reset_work);
  2656. ret = 0;
  2657. }
  2658. spin_unlock(&dev_list_lock);
  2659. if (!ret) {
  2660. flush_work(&dev->reset_work);
  2661. flush_work(&dev->probe_work);
  2662. return 0;
  2663. }
  2664. return ret;
  2665. }
  2666. static ssize_t nvme_sysfs_reset(struct device *dev,
  2667. struct device_attribute *attr, const char *buf,
  2668. size_t count)
  2669. {
  2670. struct nvme_dev *ndev = dev_get_drvdata(dev);
  2671. int ret;
  2672. ret = nvme_reset(ndev);
  2673. if (ret < 0)
  2674. return ret;
  2675. return count;
  2676. }
  2677. static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
  2678. static void nvme_async_probe(struct work_struct *work);
  2679. static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2680. {
  2681. int node, result = -ENOMEM;
  2682. struct nvme_dev *dev;
  2683. node = dev_to_node(&pdev->dev);
  2684. if (node == NUMA_NO_NODE)
  2685. set_dev_node(&pdev->dev, 0);
  2686. dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
  2687. if (!dev)
  2688. return -ENOMEM;
  2689. dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
  2690. GFP_KERNEL, node);
  2691. if (!dev->entry)
  2692. goto free;
  2693. dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
  2694. GFP_KERNEL, node);
  2695. if (!dev->queues)
  2696. goto free;
  2697. INIT_LIST_HEAD(&dev->namespaces);
  2698. dev->reset_workfn = nvme_reset_failed_dev;
  2699. INIT_WORK(&dev->reset_work, nvme_reset_workfn);
  2700. dev->dev = get_device(&pdev->dev);
  2701. pci_set_drvdata(pdev, dev);
  2702. result = nvme_set_instance(dev);
  2703. if (result)
  2704. goto put_pci;
  2705. result = nvme_setup_prp_pools(dev);
  2706. if (result)
  2707. goto release;
  2708. kref_init(&dev->kref);
  2709. dev->device = device_create(nvme_class, &pdev->dev,
  2710. MKDEV(nvme_char_major, dev->instance),
  2711. dev, "nvme%d", dev->instance);
  2712. if (IS_ERR(dev->device)) {
  2713. result = PTR_ERR(dev->device);
  2714. goto release_pools;
  2715. }
  2716. get_device(dev->device);
  2717. dev_set_drvdata(dev->device, dev);
  2718. result = device_create_file(dev->device, &dev_attr_reset_controller);
  2719. if (result)
  2720. goto put_dev;
  2721. INIT_LIST_HEAD(&dev->node);
  2722. INIT_WORK(&dev->scan_work, nvme_dev_scan);
  2723. INIT_WORK(&dev->probe_work, nvme_async_probe);
  2724. schedule_work(&dev->probe_work);
  2725. return 0;
  2726. put_dev:
  2727. device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
  2728. put_device(dev->device);
  2729. release_pools:
  2730. nvme_release_prp_pools(dev);
  2731. release:
  2732. nvme_release_instance(dev);
  2733. put_pci:
  2734. put_device(dev->dev);
  2735. free:
  2736. kfree(dev->queues);
  2737. kfree(dev->entry);
  2738. kfree(dev);
  2739. return result;
  2740. }
  2741. static void nvme_async_probe(struct work_struct *work)
  2742. {
  2743. struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
  2744. if (nvme_dev_resume(dev) && !work_busy(&dev->reset_work))
  2745. nvme_dead_ctrl(dev);
  2746. }
  2747. static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
  2748. {
  2749. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2750. if (prepare)
  2751. nvme_dev_shutdown(dev);
  2752. else
  2753. nvme_dev_resume(dev);
  2754. }
  2755. static void nvme_shutdown(struct pci_dev *pdev)
  2756. {
  2757. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2758. nvme_dev_shutdown(dev);
  2759. }
  2760. static void nvme_remove(struct pci_dev *pdev)
  2761. {
  2762. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2763. spin_lock(&dev_list_lock);
  2764. list_del_init(&dev->node);
  2765. spin_unlock(&dev_list_lock);
  2766. pci_set_drvdata(pdev, NULL);
  2767. flush_work(&dev->probe_work);
  2768. flush_work(&dev->reset_work);
  2769. flush_work(&dev->scan_work);
  2770. device_remove_file(dev->device, &dev_attr_reset_controller);
  2771. nvme_dev_remove(dev);
  2772. nvme_dev_shutdown(dev);
  2773. nvme_dev_remove_admin(dev);
  2774. device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
  2775. nvme_free_queues(dev, 0);
  2776. nvme_release_cmb(dev);
  2777. nvme_release_prp_pools(dev);
  2778. kref_put(&dev->kref, nvme_free_dev);
  2779. }
  2780. /* These functions are yet to be implemented */
  2781. #define nvme_error_detected NULL
  2782. #define nvme_dump_registers NULL
  2783. #define nvme_link_reset NULL
  2784. #define nvme_slot_reset NULL
  2785. #define nvme_error_resume NULL
  2786. #ifdef CONFIG_PM_SLEEP
  2787. static int nvme_suspend(struct device *dev)
  2788. {
  2789. struct pci_dev *pdev = to_pci_dev(dev);
  2790. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2791. nvme_dev_shutdown(ndev);
  2792. return 0;
  2793. }
  2794. static int nvme_resume(struct device *dev)
  2795. {
  2796. struct pci_dev *pdev = to_pci_dev(dev);
  2797. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2798. if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
  2799. ndev->reset_workfn = nvme_reset_failed_dev;
  2800. queue_work(nvme_workq, &ndev->reset_work);
  2801. }
  2802. return 0;
  2803. }
  2804. #endif
  2805. static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
  2806. static const struct pci_error_handlers nvme_err_handler = {
  2807. .error_detected = nvme_error_detected,
  2808. .mmio_enabled = nvme_dump_registers,
  2809. .link_reset = nvme_link_reset,
  2810. .slot_reset = nvme_slot_reset,
  2811. .resume = nvme_error_resume,
  2812. .reset_notify = nvme_reset_notify,
  2813. };
  2814. /* Move to pci_ids.h later */
  2815. #define PCI_CLASS_STORAGE_EXPRESS 0x010802
  2816. static const struct pci_device_id nvme_id_table[] = {
  2817. { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
  2818. { 0, }
  2819. };
  2820. MODULE_DEVICE_TABLE(pci, nvme_id_table);
  2821. static struct pci_driver nvme_driver = {
  2822. .name = "nvme",
  2823. .id_table = nvme_id_table,
  2824. .probe = nvme_probe,
  2825. .remove = nvme_remove,
  2826. .shutdown = nvme_shutdown,
  2827. .driver = {
  2828. .pm = &nvme_dev_pm_ops,
  2829. },
  2830. .err_handler = &nvme_err_handler,
  2831. };
  2832. static int __init nvme_init(void)
  2833. {
  2834. int result;
  2835. init_waitqueue_head(&nvme_kthread_wait);
  2836. nvme_workq = create_singlethread_workqueue("nvme");
  2837. if (!nvme_workq)
  2838. return -ENOMEM;
  2839. result = register_blkdev(nvme_major, "nvme");
  2840. if (result < 0)
  2841. goto kill_workq;
  2842. else if (result > 0)
  2843. nvme_major = result;
  2844. result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
  2845. &nvme_dev_fops);
  2846. if (result < 0)
  2847. goto unregister_blkdev;
  2848. else if (result > 0)
  2849. nvme_char_major = result;
  2850. nvme_class = class_create(THIS_MODULE, "nvme");
  2851. if (IS_ERR(nvme_class)) {
  2852. result = PTR_ERR(nvme_class);
  2853. goto unregister_chrdev;
  2854. }
  2855. result = pci_register_driver(&nvme_driver);
  2856. if (result)
  2857. goto destroy_class;
  2858. return 0;
  2859. destroy_class:
  2860. class_destroy(nvme_class);
  2861. unregister_chrdev:
  2862. __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
  2863. unregister_blkdev:
  2864. unregister_blkdev(nvme_major, "nvme");
  2865. kill_workq:
  2866. destroy_workqueue(nvme_workq);
  2867. return result;
  2868. }
  2869. static void __exit nvme_exit(void)
  2870. {
  2871. pci_unregister_driver(&nvme_driver);
  2872. unregister_blkdev(nvme_major, "nvme");
  2873. destroy_workqueue(nvme_workq);
  2874. class_destroy(nvme_class);
  2875. __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
  2876. BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
  2877. _nvme_check_size();
  2878. }
  2879. MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
  2880. MODULE_LICENSE("GPL");
  2881. MODULE_VERSION("1.0");
  2882. module_init(nvme_init);
  2883. module_exit(nvme_exit);