intel_pstate.c 23 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009
  1. /*
  2. * intel_pstate.c: Native P state management for Intel processors
  3. *
  4. * (C) Copyright 2012 Intel Corporation
  5. * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; version 2
  10. * of the License.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/module.h>
  15. #include <linux/ktime.h>
  16. #include <linux/hrtimer.h>
  17. #include <linux/tick.h>
  18. #include <linux/slab.h>
  19. #include <linux/sched.h>
  20. #include <linux/list.h>
  21. #include <linux/cpu.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/sysfs.h>
  24. #include <linux/types.h>
  25. #include <linux/fs.h>
  26. #include <linux/debugfs.h>
  27. #include <linux/acpi.h>
  28. #include <trace/events/power.h>
  29. #include <asm/div64.h>
  30. #include <asm/msr.h>
  31. #include <asm/cpu_device_id.h>
  32. #define BYT_RATIOS 0x66a
  33. #define BYT_VIDS 0x66b
  34. #define BYT_TURBO_RATIOS 0x66c
  35. #define BYT_TURBO_VIDS 0x66d
  36. #define FRAC_BITS 8
  37. #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  38. #define fp_toint(X) ((X) >> FRAC_BITS)
  39. static inline int32_t mul_fp(int32_t x, int32_t y)
  40. {
  41. return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  42. }
  43. static inline int32_t div_fp(int32_t x, int32_t y)
  44. {
  45. return div_s64((int64_t)x << FRAC_BITS, y);
  46. }
  47. struct sample {
  48. int32_t core_pct_busy;
  49. u64 aperf;
  50. u64 mperf;
  51. int freq;
  52. ktime_t time;
  53. };
  54. struct pstate_data {
  55. int current_pstate;
  56. int min_pstate;
  57. int max_pstate;
  58. int turbo_pstate;
  59. };
  60. struct vid_data {
  61. int min;
  62. int max;
  63. int turbo;
  64. int32_t ratio;
  65. };
  66. struct _pid {
  67. int setpoint;
  68. int32_t integral;
  69. int32_t p_gain;
  70. int32_t i_gain;
  71. int32_t d_gain;
  72. int deadband;
  73. int32_t last_err;
  74. };
  75. struct cpudata {
  76. int cpu;
  77. struct timer_list timer;
  78. struct pstate_data pstate;
  79. struct vid_data vid;
  80. struct _pid pid;
  81. ktime_t last_sample_time;
  82. u64 prev_aperf;
  83. u64 prev_mperf;
  84. struct sample sample;
  85. };
  86. static struct cpudata **all_cpu_data;
  87. struct pstate_adjust_policy {
  88. int sample_rate_ms;
  89. int deadband;
  90. int setpoint;
  91. int p_gain_pct;
  92. int d_gain_pct;
  93. int i_gain_pct;
  94. };
  95. struct pstate_funcs {
  96. int (*get_max)(void);
  97. int (*get_min)(void);
  98. int (*get_turbo)(void);
  99. void (*set)(struct cpudata*, int pstate);
  100. void (*get_vid)(struct cpudata *);
  101. };
  102. struct cpu_defaults {
  103. struct pstate_adjust_policy pid_policy;
  104. struct pstate_funcs funcs;
  105. };
  106. static struct pstate_adjust_policy pid_params;
  107. static struct pstate_funcs pstate_funcs;
  108. struct perf_limits {
  109. int no_turbo;
  110. int turbo_disabled;
  111. int max_perf_pct;
  112. int min_perf_pct;
  113. int32_t max_perf;
  114. int32_t min_perf;
  115. int max_policy_pct;
  116. int max_sysfs_pct;
  117. };
  118. static struct perf_limits limits = {
  119. .no_turbo = 0,
  120. .turbo_disabled = 0,
  121. .max_perf_pct = 100,
  122. .max_perf = int_tofp(1),
  123. .min_perf_pct = 0,
  124. .min_perf = 0,
  125. .max_policy_pct = 100,
  126. .max_sysfs_pct = 100,
  127. };
  128. static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
  129. int deadband, int integral) {
  130. pid->setpoint = setpoint;
  131. pid->deadband = deadband;
  132. pid->integral = int_tofp(integral);
  133. pid->last_err = int_tofp(setpoint) - int_tofp(busy);
  134. }
  135. static inline void pid_p_gain_set(struct _pid *pid, int percent)
  136. {
  137. pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
  138. }
  139. static inline void pid_i_gain_set(struct _pid *pid, int percent)
  140. {
  141. pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
  142. }
  143. static inline void pid_d_gain_set(struct _pid *pid, int percent)
  144. {
  145. pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
  146. }
  147. static signed int pid_calc(struct _pid *pid, int32_t busy)
  148. {
  149. signed int result;
  150. int32_t pterm, dterm, fp_error;
  151. int32_t integral_limit;
  152. fp_error = int_tofp(pid->setpoint) - busy;
  153. if (abs(fp_error) <= int_tofp(pid->deadband))
  154. return 0;
  155. pterm = mul_fp(pid->p_gain, fp_error);
  156. pid->integral += fp_error;
  157. /* limit the integral term */
  158. integral_limit = int_tofp(30);
  159. if (pid->integral > integral_limit)
  160. pid->integral = integral_limit;
  161. if (pid->integral < -integral_limit)
  162. pid->integral = -integral_limit;
  163. dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
  164. pid->last_err = fp_error;
  165. result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
  166. result = result + (1 << (FRAC_BITS-1));
  167. return (signed int)fp_toint(result);
  168. }
  169. static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
  170. {
  171. pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
  172. pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
  173. pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
  174. pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
  175. }
  176. static inline void intel_pstate_reset_all_pid(void)
  177. {
  178. unsigned int cpu;
  179. for_each_online_cpu(cpu) {
  180. if (all_cpu_data[cpu])
  181. intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
  182. }
  183. }
  184. static inline void update_turbo_state(void)
  185. {
  186. u64 misc_en;
  187. struct cpudata *cpu;
  188. cpu = all_cpu_data[0];
  189. rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
  190. limits.turbo_disabled =
  191. (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
  192. cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
  193. }
  194. /************************** debugfs begin ************************/
  195. static int pid_param_set(void *data, u64 val)
  196. {
  197. *(u32 *)data = val;
  198. intel_pstate_reset_all_pid();
  199. return 0;
  200. }
  201. static int pid_param_get(void *data, u64 *val)
  202. {
  203. *val = *(u32 *)data;
  204. return 0;
  205. }
  206. DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
  207. struct pid_param {
  208. char *name;
  209. void *value;
  210. };
  211. static struct pid_param pid_files[] = {
  212. {"sample_rate_ms", &pid_params.sample_rate_ms},
  213. {"d_gain_pct", &pid_params.d_gain_pct},
  214. {"i_gain_pct", &pid_params.i_gain_pct},
  215. {"deadband", &pid_params.deadband},
  216. {"setpoint", &pid_params.setpoint},
  217. {"p_gain_pct", &pid_params.p_gain_pct},
  218. {NULL, NULL}
  219. };
  220. static void __init intel_pstate_debug_expose_params(void)
  221. {
  222. struct dentry *debugfs_parent;
  223. int i = 0;
  224. debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
  225. if (IS_ERR_OR_NULL(debugfs_parent))
  226. return;
  227. while (pid_files[i].name) {
  228. debugfs_create_file(pid_files[i].name, 0660,
  229. debugfs_parent, pid_files[i].value,
  230. &fops_pid_param);
  231. i++;
  232. }
  233. }
  234. /************************** debugfs end ************************/
  235. /************************** sysfs begin ************************/
  236. #define show_one(file_name, object) \
  237. static ssize_t show_##file_name \
  238. (struct kobject *kobj, struct attribute *attr, char *buf) \
  239. { \
  240. return sprintf(buf, "%u\n", limits.object); \
  241. }
  242. static ssize_t show_no_turbo(struct kobject *kobj,
  243. struct attribute *attr, char *buf)
  244. {
  245. ssize_t ret;
  246. update_turbo_state();
  247. if (limits.turbo_disabled)
  248. ret = sprintf(buf, "%u\n", limits.turbo_disabled);
  249. else
  250. ret = sprintf(buf, "%u\n", limits.no_turbo);
  251. return ret;
  252. }
  253. static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
  254. const char *buf, size_t count)
  255. {
  256. unsigned int input;
  257. int ret;
  258. ret = sscanf(buf, "%u", &input);
  259. if (ret != 1)
  260. return -EINVAL;
  261. update_turbo_state();
  262. if (limits.turbo_disabled) {
  263. pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
  264. return -EPERM;
  265. }
  266. limits.no_turbo = clamp_t(int, input, 0, 1);
  267. return count;
  268. }
  269. static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
  270. const char *buf, size_t count)
  271. {
  272. unsigned int input;
  273. int ret;
  274. ret = sscanf(buf, "%u", &input);
  275. if (ret != 1)
  276. return -EINVAL;
  277. limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
  278. limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
  279. limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
  280. return count;
  281. }
  282. static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
  283. const char *buf, size_t count)
  284. {
  285. unsigned int input;
  286. int ret;
  287. ret = sscanf(buf, "%u", &input);
  288. if (ret != 1)
  289. return -EINVAL;
  290. limits.min_perf_pct = clamp_t(int, input, 0 , 100);
  291. limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
  292. return count;
  293. }
  294. show_one(max_perf_pct, max_perf_pct);
  295. show_one(min_perf_pct, min_perf_pct);
  296. define_one_global_rw(no_turbo);
  297. define_one_global_rw(max_perf_pct);
  298. define_one_global_rw(min_perf_pct);
  299. static struct attribute *intel_pstate_attributes[] = {
  300. &no_turbo.attr,
  301. &max_perf_pct.attr,
  302. &min_perf_pct.attr,
  303. NULL
  304. };
  305. static struct attribute_group intel_pstate_attr_group = {
  306. .attrs = intel_pstate_attributes,
  307. };
  308. static void __init intel_pstate_sysfs_expose_params(void)
  309. {
  310. struct kobject *intel_pstate_kobject;
  311. int rc;
  312. intel_pstate_kobject = kobject_create_and_add("intel_pstate",
  313. &cpu_subsys.dev_root->kobj);
  314. BUG_ON(!intel_pstate_kobject);
  315. rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
  316. BUG_ON(rc);
  317. }
  318. /************************** sysfs end ************************/
  319. static int byt_get_min_pstate(void)
  320. {
  321. u64 value;
  322. rdmsrl(BYT_RATIOS, value);
  323. return (value >> 8) & 0x7F;
  324. }
  325. static int byt_get_max_pstate(void)
  326. {
  327. u64 value;
  328. rdmsrl(BYT_RATIOS, value);
  329. return (value >> 16) & 0x7F;
  330. }
  331. static int byt_get_turbo_pstate(void)
  332. {
  333. u64 value;
  334. rdmsrl(BYT_TURBO_RATIOS, value);
  335. return value & 0x7F;
  336. }
  337. static void byt_set_pstate(struct cpudata *cpudata, int pstate)
  338. {
  339. u64 val;
  340. int32_t vid_fp;
  341. u32 vid;
  342. val = pstate << 8;
  343. if (limits.no_turbo && !limits.turbo_disabled)
  344. val |= (u64)1 << 32;
  345. vid_fp = cpudata->vid.min + mul_fp(
  346. int_tofp(pstate - cpudata->pstate.min_pstate),
  347. cpudata->vid.ratio);
  348. vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
  349. vid = fp_toint(vid_fp);
  350. if (pstate > cpudata->pstate.max_pstate)
  351. vid = cpudata->vid.turbo;
  352. val |= vid;
  353. wrmsrl(MSR_IA32_PERF_CTL, val);
  354. }
  355. static void byt_get_vid(struct cpudata *cpudata)
  356. {
  357. u64 value;
  358. rdmsrl(BYT_VIDS, value);
  359. cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
  360. cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
  361. cpudata->vid.ratio = div_fp(
  362. cpudata->vid.max - cpudata->vid.min,
  363. int_tofp(cpudata->pstate.max_pstate -
  364. cpudata->pstate.min_pstate));
  365. rdmsrl(BYT_TURBO_VIDS, value);
  366. cpudata->vid.turbo = value & 0x7f;
  367. }
  368. static int core_get_min_pstate(void)
  369. {
  370. u64 value;
  371. rdmsrl(MSR_PLATFORM_INFO, value);
  372. return (value >> 40) & 0xFF;
  373. }
  374. static int core_get_max_pstate(void)
  375. {
  376. u64 value;
  377. rdmsrl(MSR_PLATFORM_INFO, value);
  378. return (value >> 8) & 0xFF;
  379. }
  380. static int core_get_turbo_pstate(void)
  381. {
  382. u64 value;
  383. int nont, ret;
  384. rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
  385. nont = core_get_max_pstate();
  386. ret = (value) & 255;
  387. if (ret <= nont)
  388. ret = nont;
  389. return ret;
  390. }
  391. static void core_set_pstate(struct cpudata *cpudata, int pstate)
  392. {
  393. u64 val;
  394. val = pstate << 8;
  395. if (limits.no_turbo && !limits.turbo_disabled)
  396. val |= (u64)1 << 32;
  397. wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
  398. }
  399. static struct cpu_defaults core_params = {
  400. .pid_policy = {
  401. .sample_rate_ms = 10,
  402. .deadband = 0,
  403. .setpoint = 97,
  404. .p_gain_pct = 20,
  405. .d_gain_pct = 0,
  406. .i_gain_pct = 0,
  407. },
  408. .funcs = {
  409. .get_max = core_get_max_pstate,
  410. .get_min = core_get_min_pstate,
  411. .get_turbo = core_get_turbo_pstate,
  412. .set = core_set_pstate,
  413. },
  414. };
  415. static struct cpu_defaults byt_params = {
  416. .pid_policy = {
  417. .sample_rate_ms = 10,
  418. .deadband = 0,
  419. .setpoint = 97,
  420. .p_gain_pct = 14,
  421. .d_gain_pct = 0,
  422. .i_gain_pct = 4,
  423. },
  424. .funcs = {
  425. .get_max = byt_get_max_pstate,
  426. .get_min = byt_get_min_pstate,
  427. .get_turbo = byt_get_turbo_pstate,
  428. .set = byt_set_pstate,
  429. .get_vid = byt_get_vid,
  430. },
  431. };
  432. static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
  433. {
  434. int max_perf = cpu->pstate.turbo_pstate;
  435. int max_perf_adj;
  436. int min_perf;
  437. if (limits.no_turbo || limits.turbo_disabled)
  438. max_perf = cpu->pstate.max_pstate;
  439. max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
  440. *max = clamp_t(int, max_perf_adj,
  441. cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
  442. min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
  443. *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
  444. }
  445. static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
  446. {
  447. int max_perf, min_perf;
  448. update_turbo_state();
  449. intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
  450. pstate = clamp_t(int, pstate, min_perf, max_perf);
  451. if (pstate == cpu->pstate.current_pstate)
  452. return;
  453. trace_cpu_frequency(pstate * 100000, cpu->cpu);
  454. cpu->pstate.current_pstate = pstate;
  455. pstate_funcs.set(cpu, pstate);
  456. }
  457. static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
  458. {
  459. cpu->pstate.min_pstate = pstate_funcs.get_min();
  460. cpu->pstate.max_pstate = pstate_funcs.get_max();
  461. cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
  462. if (pstate_funcs.get_vid)
  463. pstate_funcs.get_vid(cpu);
  464. intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
  465. }
  466. static inline void intel_pstate_calc_busy(struct cpudata *cpu)
  467. {
  468. struct sample *sample = &cpu->sample;
  469. int64_t core_pct;
  470. core_pct = int_tofp(sample->aperf) * int_tofp(100);
  471. core_pct = div64_u64(core_pct, int_tofp(sample->mperf));
  472. sample->freq = fp_toint(
  473. mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
  474. sample->core_pct_busy = (int32_t)core_pct;
  475. }
  476. static inline void intel_pstate_sample(struct cpudata *cpu)
  477. {
  478. u64 aperf, mperf;
  479. unsigned long flags;
  480. local_irq_save(flags);
  481. rdmsrl(MSR_IA32_APERF, aperf);
  482. rdmsrl(MSR_IA32_MPERF, mperf);
  483. local_irq_restore(flags);
  484. cpu->last_sample_time = cpu->sample.time;
  485. cpu->sample.time = ktime_get();
  486. cpu->sample.aperf = aperf;
  487. cpu->sample.mperf = mperf;
  488. cpu->sample.aperf -= cpu->prev_aperf;
  489. cpu->sample.mperf -= cpu->prev_mperf;
  490. intel_pstate_calc_busy(cpu);
  491. cpu->prev_aperf = aperf;
  492. cpu->prev_mperf = mperf;
  493. }
  494. static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
  495. {
  496. int delay;
  497. delay = msecs_to_jiffies(pid_params.sample_rate_ms);
  498. mod_timer_pinned(&cpu->timer, jiffies + delay);
  499. }
  500. static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
  501. {
  502. int32_t core_busy, max_pstate, current_pstate, sample_ratio;
  503. u32 duration_us;
  504. u32 sample_time;
  505. core_busy = cpu->sample.core_pct_busy;
  506. max_pstate = int_tofp(cpu->pstate.max_pstate);
  507. current_pstate = int_tofp(cpu->pstate.current_pstate);
  508. core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
  509. sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC;
  510. duration_us = (u32) ktime_us_delta(cpu->sample.time,
  511. cpu->last_sample_time);
  512. if (duration_us > sample_time * 3) {
  513. sample_ratio = div_fp(int_tofp(sample_time),
  514. int_tofp(duration_us));
  515. core_busy = mul_fp(core_busy, sample_ratio);
  516. }
  517. return core_busy;
  518. }
  519. static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
  520. {
  521. int32_t busy_scaled;
  522. struct _pid *pid;
  523. signed int ctl;
  524. pid = &cpu->pid;
  525. busy_scaled = intel_pstate_get_scaled_busy(cpu);
  526. ctl = pid_calc(pid, busy_scaled);
  527. /* Negative values of ctl increase the pstate and vice versa */
  528. intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl);
  529. }
  530. static void intel_pstate_timer_func(unsigned long __data)
  531. {
  532. struct cpudata *cpu = (struct cpudata *) __data;
  533. struct sample *sample;
  534. intel_pstate_sample(cpu);
  535. sample = &cpu->sample;
  536. intel_pstate_adjust_busy_pstate(cpu);
  537. trace_pstate_sample(fp_toint(sample->core_pct_busy),
  538. fp_toint(intel_pstate_get_scaled_busy(cpu)),
  539. cpu->pstate.current_pstate,
  540. sample->mperf,
  541. sample->aperf,
  542. sample->freq);
  543. intel_pstate_set_sample_time(cpu);
  544. }
  545. #define ICPU(model, policy) \
  546. { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
  547. (unsigned long)&policy }
  548. static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
  549. ICPU(0x2a, core_params),
  550. ICPU(0x2d, core_params),
  551. ICPU(0x37, byt_params),
  552. ICPU(0x3a, core_params),
  553. ICPU(0x3c, core_params),
  554. ICPU(0x3d, core_params),
  555. ICPU(0x3e, core_params),
  556. ICPU(0x3f, core_params),
  557. ICPU(0x45, core_params),
  558. ICPU(0x46, core_params),
  559. ICPU(0x4c, byt_params),
  560. ICPU(0x4f, core_params),
  561. ICPU(0x56, core_params),
  562. {}
  563. };
  564. MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
  565. static int intel_pstate_init_cpu(unsigned int cpunum)
  566. {
  567. struct cpudata *cpu;
  568. if (!all_cpu_data[cpunum])
  569. all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
  570. GFP_KERNEL);
  571. if (!all_cpu_data[cpunum])
  572. return -ENOMEM;
  573. cpu = all_cpu_data[cpunum];
  574. cpu->cpu = cpunum;
  575. intel_pstate_get_cpu_pstates(cpu);
  576. init_timer_deferrable(&cpu->timer);
  577. cpu->timer.function = intel_pstate_timer_func;
  578. cpu->timer.data = (unsigned long)cpu;
  579. cpu->timer.expires = jiffies + HZ/100;
  580. intel_pstate_busy_pid_reset(cpu);
  581. intel_pstate_sample(cpu);
  582. add_timer_on(&cpu->timer, cpunum);
  583. pr_debug("Intel pstate controlling: cpu %d\n", cpunum);
  584. return 0;
  585. }
  586. static unsigned int intel_pstate_get(unsigned int cpu_num)
  587. {
  588. struct sample *sample;
  589. struct cpudata *cpu;
  590. cpu = all_cpu_data[cpu_num];
  591. if (!cpu)
  592. return 0;
  593. sample = &cpu->sample;
  594. return sample->freq;
  595. }
  596. static int intel_pstate_set_policy(struct cpufreq_policy *policy)
  597. {
  598. if (!policy->cpuinfo.max_freq)
  599. return -ENODEV;
  600. if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
  601. limits.min_perf_pct = 100;
  602. limits.min_perf = int_tofp(1);
  603. limits.max_policy_pct = 100;
  604. limits.max_perf_pct = 100;
  605. limits.max_perf = int_tofp(1);
  606. limits.no_turbo = 0;
  607. return 0;
  608. }
  609. limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
  610. limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
  611. limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
  612. limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq;
  613. limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
  614. limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
  615. limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
  616. return 0;
  617. }
  618. static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
  619. {
  620. cpufreq_verify_within_cpu_limits(policy);
  621. if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
  622. policy->policy != CPUFREQ_POLICY_PERFORMANCE)
  623. return -EINVAL;
  624. return 0;
  625. }
  626. static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
  627. {
  628. int cpu_num = policy->cpu;
  629. struct cpudata *cpu = all_cpu_data[cpu_num];
  630. pr_info("intel_pstate CPU %d exiting\n", cpu_num);
  631. del_timer_sync(&all_cpu_data[cpu_num]->timer);
  632. intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
  633. }
  634. static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
  635. {
  636. struct cpudata *cpu;
  637. int rc;
  638. rc = intel_pstate_init_cpu(policy->cpu);
  639. if (rc)
  640. return rc;
  641. cpu = all_cpu_data[policy->cpu];
  642. if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
  643. policy->policy = CPUFREQ_POLICY_PERFORMANCE;
  644. else
  645. policy->policy = CPUFREQ_POLICY_POWERSAVE;
  646. policy->min = cpu->pstate.min_pstate * 100000;
  647. policy->max = cpu->pstate.turbo_pstate * 100000;
  648. /* cpuinfo and default policy values */
  649. policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
  650. policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
  651. policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
  652. cpumask_set_cpu(policy->cpu, policy->cpus);
  653. return 0;
  654. }
  655. static struct cpufreq_driver intel_pstate_driver = {
  656. .flags = CPUFREQ_CONST_LOOPS,
  657. .verify = intel_pstate_verify_policy,
  658. .setpolicy = intel_pstate_set_policy,
  659. .get = intel_pstate_get,
  660. .init = intel_pstate_cpu_init,
  661. .stop_cpu = intel_pstate_stop_cpu,
  662. .name = "intel_pstate",
  663. };
  664. static int __initdata no_load;
  665. static int intel_pstate_msrs_not_valid(void)
  666. {
  667. /* Check that all the msr's we are using are valid. */
  668. u64 aperf, mperf, tmp;
  669. rdmsrl(MSR_IA32_APERF, aperf);
  670. rdmsrl(MSR_IA32_MPERF, mperf);
  671. if (!pstate_funcs.get_max() ||
  672. !pstate_funcs.get_min() ||
  673. !pstate_funcs.get_turbo())
  674. return -ENODEV;
  675. rdmsrl(MSR_IA32_APERF, tmp);
  676. if (!(tmp - aperf))
  677. return -ENODEV;
  678. rdmsrl(MSR_IA32_MPERF, tmp);
  679. if (!(tmp - mperf))
  680. return -ENODEV;
  681. return 0;
  682. }
  683. static void copy_pid_params(struct pstate_adjust_policy *policy)
  684. {
  685. pid_params.sample_rate_ms = policy->sample_rate_ms;
  686. pid_params.p_gain_pct = policy->p_gain_pct;
  687. pid_params.i_gain_pct = policy->i_gain_pct;
  688. pid_params.d_gain_pct = policy->d_gain_pct;
  689. pid_params.deadband = policy->deadband;
  690. pid_params.setpoint = policy->setpoint;
  691. }
  692. static void copy_cpu_funcs(struct pstate_funcs *funcs)
  693. {
  694. pstate_funcs.get_max = funcs->get_max;
  695. pstate_funcs.get_min = funcs->get_min;
  696. pstate_funcs.get_turbo = funcs->get_turbo;
  697. pstate_funcs.set = funcs->set;
  698. pstate_funcs.get_vid = funcs->get_vid;
  699. }
  700. #if IS_ENABLED(CONFIG_ACPI)
  701. #include <acpi/processor.h>
  702. static bool intel_pstate_no_acpi_pss(void)
  703. {
  704. int i;
  705. for_each_possible_cpu(i) {
  706. acpi_status status;
  707. union acpi_object *pss;
  708. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  709. struct acpi_processor *pr = per_cpu(processors, i);
  710. if (!pr)
  711. continue;
  712. status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
  713. if (ACPI_FAILURE(status))
  714. continue;
  715. pss = buffer.pointer;
  716. if (pss && pss->type == ACPI_TYPE_PACKAGE) {
  717. kfree(pss);
  718. return false;
  719. }
  720. kfree(pss);
  721. }
  722. return true;
  723. }
  724. struct hw_vendor_info {
  725. u16 valid;
  726. char oem_id[ACPI_OEM_ID_SIZE];
  727. char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
  728. };
  729. /* Hardware vendor-specific info that has its own power management modes */
  730. static struct hw_vendor_info vendor_info[] = {
  731. {1, "HP ", "ProLiant"},
  732. {0, "", ""},
  733. };
  734. static bool intel_pstate_platform_pwr_mgmt_exists(void)
  735. {
  736. struct acpi_table_header hdr;
  737. struct hw_vendor_info *v_info;
  738. if (acpi_disabled ||
  739. ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
  740. return false;
  741. for (v_info = vendor_info; v_info->valid; v_info++) {
  742. if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
  743. !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
  744. intel_pstate_no_acpi_pss())
  745. return true;
  746. }
  747. return false;
  748. }
  749. #else /* CONFIG_ACPI not enabled */
  750. static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
  751. #endif /* CONFIG_ACPI */
  752. static int __init intel_pstate_init(void)
  753. {
  754. int cpu, rc = 0;
  755. const struct x86_cpu_id *id;
  756. struct cpu_defaults *cpu_info;
  757. if (no_load)
  758. return -ENODEV;
  759. id = x86_match_cpu(intel_pstate_cpu_ids);
  760. if (!id)
  761. return -ENODEV;
  762. /*
  763. * The Intel pstate driver will be ignored if the platform
  764. * firmware has its own power management modes.
  765. */
  766. if (intel_pstate_platform_pwr_mgmt_exists())
  767. return -ENODEV;
  768. cpu_info = (struct cpu_defaults *)id->driver_data;
  769. copy_pid_params(&cpu_info->pid_policy);
  770. copy_cpu_funcs(&cpu_info->funcs);
  771. if (intel_pstate_msrs_not_valid())
  772. return -ENODEV;
  773. pr_info("Intel P-state driver initializing.\n");
  774. all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
  775. if (!all_cpu_data)
  776. return -ENOMEM;
  777. rc = cpufreq_register_driver(&intel_pstate_driver);
  778. if (rc)
  779. goto out;
  780. intel_pstate_debug_expose_params();
  781. intel_pstate_sysfs_expose_params();
  782. return rc;
  783. out:
  784. get_online_cpus();
  785. for_each_online_cpu(cpu) {
  786. if (all_cpu_data[cpu]) {
  787. del_timer_sync(&all_cpu_data[cpu]->timer);
  788. kfree(all_cpu_data[cpu]);
  789. }
  790. }
  791. put_online_cpus();
  792. vfree(all_cpu_data);
  793. return -ENODEV;
  794. }
  795. device_initcall(intel_pstate_init);
  796. static int __init intel_pstate_setup(char *str)
  797. {
  798. if (!str)
  799. return -EINVAL;
  800. if (!strcmp(str, "disable"))
  801. no_load = 1;
  802. return 0;
  803. }
  804. early_param("intel_pstate", intel_pstate_setup);
  805. MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
  806. MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
  807. MODULE_LICENSE("GPL");