ddbridge-core.c 87 KB

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  1. /*
  2. * ddbridge-core.c: Digital Devices bridge core functions
  3. *
  4. * Copyright (C) 2010-2017 Digital Devices GmbH
  5. * Marcus Metzler <mocm@metzlerbros.de>
  6. * Ralph Metzler <rjkm@metzlerbros.de>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 only, as published by the Free Software Foundation.
  12. *
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * To obtain the license, point your browser to
  20. * http://www.gnu.org/copyleft/gpl.html
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/poll.h>
  28. #include <linux/io.h>
  29. #include <linux/pci.h>
  30. #include <linux/pci_ids.h>
  31. #include <linux/timer.h>
  32. #include <linux/i2c.h>
  33. #include <linux/swab.h>
  34. #include <linux/vmalloc.h>
  35. #include "ddbridge.h"
  36. #include "ddbridge-i2c.h"
  37. #include "ddbridge-regs.h"
  38. #include "ddbridge-maxs8.h"
  39. #include "ddbridge-io.h"
  40. #include "tda18271c2dd.h"
  41. #include "stv6110x.h"
  42. #include "stv090x.h"
  43. #include "lnbh24.h"
  44. #include "drxk.h"
  45. #include "stv0367.h"
  46. #include "stv0367_priv.h"
  47. #include "cxd2841er.h"
  48. #include "tda18212.h"
  49. #include "stv0910.h"
  50. #include "stv6111.h"
  51. #include "lnbh25.h"
  52. #include "cxd2099.h"
  53. /****************************************************************************/
  54. #define DDB_MAX_ADAPTER 64
  55. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  56. DEFINE_MUTEX(redirect_lock);
  57. static struct ddb *ddbs[DDB_MAX_ADAPTER];
  58. /****************************************************************************/
  59. /****************************************************************************/
  60. /****************************************************************************/
  61. static void ddb_set_dma_table(struct ddb_io *io)
  62. {
  63. struct ddb *dev = io->port->dev;
  64. struct ddb_dma *dma = io->dma;
  65. u32 i;
  66. u64 mem;
  67. if (!dma)
  68. return;
  69. for (i = 0; i < dma->num; i++) {
  70. mem = dma->pbuf[i];
  71. ddbwritel(dev, mem & 0xffffffff, dma->bufregs + i * 8);
  72. ddbwritel(dev, mem >> 32, dma->bufregs + i * 8 + 4);
  73. }
  74. dma->bufval = ((dma->div & 0x0f) << 16) |
  75. ((dma->num & 0x1f) << 11) |
  76. ((dma->size >> 7) & 0x7ff);
  77. }
  78. static void ddb_set_dma_tables(struct ddb *dev)
  79. {
  80. u32 i;
  81. for (i = 0; i < DDB_MAX_PORT; i++) {
  82. if (dev->port[i].input[0])
  83. ddb_set_dma_table(dev->port[i].input[0]);
  84. if (dev->port[i].input[1])
  85. ddb_set_dma_table(dev->port[i].input[1]);
  86. if (dev->port[i].output)
  87. ddb_set_dma_table(dev->port[i].output);
  88. }
  89. }
  90. /****************************************************************************/
  91. /****************************************************************************/
  92. /****************************************************************************/
  93. static void ddb_redirect_dma(struct ddb *dev,
  94. struct ddb_dma *sdma,
  95. struct ddb_dma *ddma)
  96. {
  97. u32 i, base;
  98. u64 mem;
  99. sdma->bufval = ddma->bufval;
  100. base = sdma->bufregs;
  101. for (i = 0; i < ddma->num; i++) {
  102. mem = ddma->pbuf[i];
  103. ddbwritel(dev, mem & 0xffffffff, base + i * 8);
  104. ddbwritel(dev, mem >> 32, base + i * 8 + 4);
  105. }
  106. }
  107. static int ddb_unredirect(struct ddb_port *port)
  108. {
  109. struct ddb_input *oredi, *iredi = 0;
  110. struct ddb_output *iredo = 0;
  111. /* dev_info(port->dev->dev,
  112. * "unredirect %d.%d\n", port->dev->nr, port->nr);
  113. */
  114. mutex_lock(&redirect_lock);
  115. if (port->output->dma->running) {
  116. mutex_unlock(&redirect_lock);
  117. return -EBUSY;
  118. }
  119. oredi = port->output->redi;
  120. if (!oredi)
  121. goto done;
  122. if (port->input[0]) {
  123. iredi = port->input[0]->redi;
  124. iredo = port->input[0]->redo;
  125. if (iredo) {
  126. iredo->port->output->redi = oredi;
  127. if (iredo->port->input[0]) {
  128. iredo->port->input[0]->redi = iredi;
  129. ddb_redirect_dma(oredi->port->dev,
  130. oredi->dma, iredo->dma);
  131. }
  132. port->input[0]->redo = 0;
  133. ddb_set_dma_table(port->input[0]);
  134. }
  135. oredi->redi = iredi;
  136. port->input[0]->redi = 0;
  137. }
  138. oredi->redo = 0;
  139. port->output->redi = 0;
  140. ddb_set_dma_table(oredi);
  141. done:
  142. mutex_unlock(&redirect_lock);
  143. return 0;
  144. }
  145. static int ddb_redirect(u32 i, u32 p)
  146. {
  147. struct ddb *idev = ddbs[(i >> 4) & 0x3f];
  148. struct ddb_input *input, *input2;
  149. struct ddb *pdev = ddbs[(p >> 4) & 0x3f];
  150. struct ddb_port *port;
  151. if (!idev || !pdev)
  152. return -EINVAL;
  153. if (!idev->has_dma || !pdev->has_dma)
  154. return -EINVAL;
  155. port = &pdev->port[p & 0x0f];
  156. if (!port->output)
  157. return -EINVAL;
  158. if (ddb_unredirect(port))
  159. return -EBUSY;
  160. if (i == 8)
  161. return 0;
  162. input = &idev->input[i & 7];
  163. if (!input)
  164. return -EINVAL;
  165. mutex_lock(&redirect_lock);
  166. if (port->output->dma->running || input->dma->running) {
  167. mutex_unlock(&redirect_lock);
  168. return -EBUSY;
  169. }
  170. input2 = port->input[0];
  171. if (input2) {
  172. if (input->redi) {
  173. input2->redi = input->redi;
  174. input->redi = 0;
  175. } else
  176. input2->redi = input;
  177. }
  178. input->redo = port->output;
  179. port->output->redi = input;
  180. ddb_redirect_dma(input->port->dev, input->dma, port->output->dma);
  181. mutex_unlock(&redirect_lock);
  182. return 0;
  183. }
  184. /****************************************************************************/
  185. /****************************************************************************/
  186. /****************************************************************************/
  187. static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
  188. {
  189. int i;
  190. if (!dma)
  191. return;
  192. for (i = 0; i < dma->num; i++) {
  193. if (dma->vbuf[i]) {
  194. if (alt_dma) {
  195. dma_unmap_single(&pdev->dev, dma->pbuf[i],
  196. dma->size,
  197. dir ? DMA_TO_DEVICE :
  198. DMA_FROM_DEVICE);
  199. kfree(dma->vbuf[i]);
  200. dma->vbuf[i] = NULL;
  201. } else {
  202. dma_free_coherent(&pdev->dev, dma->size,
  203. dma->vbuf[i], dma->pbuf[i]);
  204. }
  205. dma->vbuf[i] = NULL;
  206. }
  207. }
  208. }
  209. static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
  210. {
  211. int i;
  212. if (!dma)
  213. return 0;
  214. for (i = 0; i < dma->num; i++) {
  215. if (alt_dma) {
  216. dma->vbuf[i] = kmalloc(dma->size, __GFP_RETRY_MAYFAIL);
  217. if (!dma->vbuf[i])
  218. return -ENOMEM;
  219. dma->pbuf[i] = dma_map_single(&pdev->dev,
  220. dma->vbuf[i],
  221. dma->size,
  222. dir ? DMA_TO_DEVICE :
  223. DMA_FROM_DEVICE);
  224. if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) {
  225. kfree(dma->vbuf[i]);
  226. dma->vbuf[i] = NULL;
  227. return -ENOMEM;
  228. }
  229. } else {
  230. dma->vbuf[i] = dma_alloc_coherent(&pdev->dev,
  231. dma->size,
  232. &dma->pbuf[i],
  233. GFP_KERNEL);
  234. if (!dma->vbuf[i])
  235. return -ENOMEM;
  236. }
  237. }
  238. return 0;
  239. }
  240. int ddb_buffers_alloc(struct ddb *dev)
  241. {
  242. int i;
  243. struct ddb_port *port;
  244. for (i = 0; i < dev->port_num; i++) {
  245. port = &dev->port[i];
  246. switch (port->class) {
  247. case DDB_PORT_TUNER:
  248. if (port->input[0]->dma)
  249. if (dma_alloc(dev->pdev, port->input[0]->dma, 0)
  250. < 0)
  251. return -1;
  252. if (port->input[1]->dma)
  253. if (dma_alloc(dev->pdev, port->input[1]->dma, 0)
  254. < 0)
  255. return -1;
  256. break;
  257. case DDB_PORT_CI:
  258. case DDB_PORT_LOOP:
  259. if (port->input[0]->dma)
  260. if (dma_alloc(dev->pdev, port->input[0]->dma, 0)
  261. < 0)
  262. return -1;
  263. if (port->output->dma)
  264. if (dma_alloc(dev->pdev, port->output->dma, 1)
  265. < 0)
  266. return -1;
  267. break;
  268. default:
  269. break;
  270. }
  271. }
  272. ddb_set_dma_tables(dev);
  273. return 0;
  274. }
  275. void ddb_buffers_free(struct ddb *dev)
  276. {
  277. int i;
  278. struct ddb_port *port;
  279. for (i = 0; i < dev->port_num; i++) {
  280. port = &dev->port[i];
  281. if (port->input[0] && port->input[0]->dma)
  282. dma_free(dev->pdev, port->input[0]->dma, 0);
  283. if (port->input[1] && port->input[1]->dma)
  284. dma_free(dev->pdev, port->input[1]->dma, 0);
  285. if (port->output && port->output->dma)
  286. dma_free(dev->pdev, port->output->dma, 1);
  287. }
  288. }
  289. static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
  290. {
  291. struct ddb *dev = output->port->dev;
  292. u32 bitrate = output->port->obr, max_bitrate = 72000;
  293. u32 gap = 4, nco = 0;
  294. *con = 0x1c;
  295. if (output->port->gap != 0xffffffff) {
  296. flags |= 1;
  297. gap = output->port->gap;
  298. max_bitrate = 0;
  299. }
  300. if (dev->link[0].info->type == DDB_OCTOPUS_CI && output->port->nr > 1) {
  301. *con = 0x10c;
  302. if (dev->link[0].ids.regmapid >= 0x10003 && !(flags & 1)) {
  303. if (!(flags & 2)) {
  304. /* NCO */
  305. max_bitrate = 0;
  306. gap = 0;
  307. if (bitrate != 72000) {
  308. if (bitrate >= 96000)
  309. *con |= 0x800;
  310. else {
  311. *con |= 0x1000;
  312. nco = (bitrate * 8192 + 71999)
  313. / 72000;
  314. }
  315. }
  316. } else {
  317. /* Divider and gap */
  318. *con |= 0x1810;
  319. if (bitrate <= 64000) {
  320. max_bitrate = 64000;
  321. nco = 8;
  322. } else if (bitrate <= 72000) {
  323. max_bitrate = 72000;
  324. nco = 7;
  325. } else {
  326. max_bitrate = 96000;
  327. nco = 5;
  328. }
  329. }
  330. } else {
  331. if (bitrate > 72000) {
  332. *con |= 0x810; /* 96 MBit/s and gap */
  333. max_bitrate = 96000;
  334. }
  335. *con |= 0x10; /* enable gap */
  336. }
  337. }
  338. if (max_bitrate > 0) {
  339. if (bitrate > max_bitrate)
  340. bitrate = max_bitrate;
  341. if (bitrate < 31000)
  342. bitrate = 31000;
  343. gap = ((max_bitrate - bitrate) * 94) / bitrate;
  344. if (gap < 2)
  345. *con &= ~0x10; /* Disable gap */
  346. else
  347. gap -= 2;
  348. if (gap > 127)
  349. gap = 127;
  350. }
  351. *con2 = (nco << 16) | gap;
  352. }
  353. static void ddb_output_start(struct ddb_output *output)
  354. {
  355. struct ddb *dev = output->port->dev;
  356. u32 con = 0x11c, con2 = 0;
  357. if (output->dma) {
  358. spin_lock_irq(&output->dma->lock);
  359. output->dma->cbuf = 0;
  360. output->dma->coff = 0;
  361. output->dma->stat = 0;
  362. ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
  363. }
  364. if (output->port->input[0]->port->class == DDB_PORT_LOOP)
  365. con = (1UL << 13) | 0x14;
  366. else
  367. calc_con(output, &con, &con2, 0);
  368. ddbwritel(dev, 0, TS_CONTROL(output));
  369. ddbwritel(dev, 2, TS_CONTROL(output));
  370. ddbwritel(dev, 0, TS_CONTROL(output));
  371. ddbwritel(dev, con, TS_CONTROL(output));
  372. ddbwritel(dev, con2, TS_CONTROL2(output));
  373. if (output->dma) {
  374. ddbwritel(dev, output->dma->bufval,
  375. DMA_BUFFER_SIZE(output->dma));
  376. ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma));
  377. ddbwritel(dev, 1, DMA_BASE_READ);
  378. ddbwritel(dev, 7, DMA_BUFFER_CONTROL(output->dma));
  379. }
  380. ddbwritel(dev, con | 1, TS_CONTROL(output));
  381. if (output->dma) {
  382. output->dma->running = 1;
  383. spin_unlock_irq(&output->dma->lock);
  384. }
  385. }
  386. static void ddb_output_stop(struct ddb_output *output)
  387. {
  388. struct ddb *dev = output->port->dev;
  389. if (output->dma)
  390. spin_lock_irq(&output->dma->lock);
  391. ddbwritel(dev, 0, TS_CONTROL(output));
  392. if (output->dma) {
  393. ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
  394. output->dma->running = 0;
  395. spin_unlock_irq(&output->dma->lock);
  396. }
  397. }
  398. static void ddb_input_stop(struct ddb_input *input)
  399. {
  400. struct ddb *dev = input->port->dev;
  401. u32 tag = DDB_LINK_TAG(input->port->lnr);
  402. if (input->dma)
  403. spin_lock_irq(&input->dma->lock);
  404. ddbwritel(dev, 0, tag | TS_CONTROL(input));
  405. if (input->dma) {
  406. ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
  407. input->dma->running = 0;
  408. spin_unlock_irq(&input->dma->lock);
  409. }
  410. }
  411. static void ddb_input_start(struct ddb_input *input)
  412. {
  413. struct ddb *dev = input->port->dev;
  414. if (input->dma) {
  415. spin_lock_irq(&input->dma->lock);
  416. input->dma->cbuf = 0;
  417. input->dma->coff = 0;
  418. input->dma->stat = 0;
  419. ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
  420. }
  421. ddbwritel(dev, 0, TS_CONTROL(input));
  422. ddbwritel(dev, 2, TS_CONTROL(input));
  423. ddbwritel(dev, 0, TS_CONTROL(input));
  424. if (input->dma) {
  425. ddbwritel(dev, input->dma->bufval,
  426. DMA_BUFFER_SIZE(input->dma));
  427. ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma));
  428. ddbwritel(dev, 1, DMA_BASE_WRITE);
  429. ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma));
  430. }
  431. ddbwritel(dev, 0x09, TS_CONTROL(input));
  432. if (input->dma) {
  433. input->dma->running = 1;
  434. spin_unlock_irq(&input->dma->lock);
  435. }
  436. }
  437. static void ddb_input_start_all(struct ddb_input *input)
  438. {
  439. struct ddb_input *i = input;
  440. struct ddb_output *o;
  441. mutex_lock(&redirect_lock);
  442. while (i && (o = i->redo)) {
  443. ddb_output_start(o);
  444. i = o->port->input[0];
  445. if (i)
  446. ddb_input_start(i);
  447. }
  448. ddb_input_start(input);
  449. mutex_unlock(&redirect_lock);
  450. }
  451. static void ddb_input_stop_all(struct ddb_input *input)
  452. {
  453. struct ddb_input *i = input;
  454. struct ddb_output *o;
  455. mutex_lock(&redirect_lock);
  456. ddb_input_stop(input);
  457. while (i && (o = i->redo)) {
  458. ddb_output_stop(o);
  459. i = o->port->input[0];
  460. if (i)
  461. ddb_input_stop(i);
  462. }
  463. mutex_unlock(&redirect_lock);
  464. }
  465. static u32 ddb_output_free(struct ddb_output *output)
  466. {
  467. u32 idx, off, stat = output->dma->stat;
  468. s32 diff;
  469. idx = (stat >> 11) & 0x1f;
  470. off = (stat & 0x7ff) << 7;
  471. if (output->dma->cbuf != idx) {
  472. if ((((output->dma->cbuf + 1) % output->dma->num) == idx) &&
  473. (output->dma->size - output->dma->coff <= 188))
  474. return 0;
  475. return 188;
  476. }
  477. diff = off - output->dma->coff;
  478. if (diff <= 0 || diff > 188)
  479. return 188;
  480. return 0;
  481. }
  482. static ssize_t ddb_output_write(struct ddb_output *output,
  483. const __user u8 *buf, size_t count)
  484. {
  485. struct ddb *dev = output->port->dev;
  486. u32 idx, off, stat = output->dma->stat;
  487. u32 left = count, len;
  488. idx = (stat >> 11) & 0x1f;
  489. off = (stat & 0x7ff) << 7;
  490. while (left) {
  491. len = output->dma->size - output->dma->coff;
  492. if ((((output->dma->cbuf + 1) % output->dma->num) == idx) &&
  493. (off == 0)) {
  494. if (len <= 188)
  495. break;
  496. len -= 188;
  497. }
  498. if (output->dma->cbuf == idx) {
  499. if (off > output->dma->coff) {
  500. len = off - output->dma->coff;
  501. len -= (len % 188);
  502. if (len <= 188)
  503. break;
  504. len -= 188;
  505. }
  506. }
  507. if (len > left)
  508. len = left;
  509. if (copy_from_user(output->dma->vbuf[output->dma->cbuf] +
  510. output->dma->coff,
  511. buf, len))
  512. return -EIO;
  513. if (alt_dma)
  514. dma_sync_single_for_device(dev->dev,
  515. output->dma->pbuf[output->dma->cbuf],
  516. output->dma->size, DMA_TO_DEVICE);
  517. left -= len;
  518. buf += len;
  519. output->dma->coff += len;
  520. if (output->dma->coff == output->dma->size) {
  521. output->dma->coff = 0;
  522. output->dma->cbuf = ((output->dma->cbuf + 1) %
  523. output->dma->num);
  524. }
  525. ddbwritel(dev,
  526. (output->dma->cbuf << 11) |
  527. (output->dma->coff >> 7),
  528. DMA_BUFFER_ACK(output->dma));
  529. }
  530. return count - left;
  531. }
  532. static u32 ddb_input_avail(struct ddb_input *input)
  533. {
  534. struct ddb *dev = input->port->dev;
  535. u32 idx, off, stat = input->dma->stat;
  536. u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma));
  537. idx = (stat >> 11) & 0x1f;
  538. off = (stat & 0x7ff) << 7;
  539. if (ctrl & 4) {
  540. dev_err(dev->dev, "IA %d %d %08x\n", idx, off, ctrl);
  541. ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma));
  542. return 0;
  543. }
  544. if (input->dma->cbuf != idx)
  545. return 188;
  546. return 0;
  547. }
  548. static ssize_t ddb_input_read(struct ddb_input *input,
  549. __user u8 *buf, size_t count)
  550. {
  551. struct ddb *dev = input->port->dev;
  552. u32 left = count;
  553. u32 idx, free, stat = input->dma->stat;
  554. int ret;
  555. idx = (stat >> 11) & 0x1f;
  556. while (left) {
  557. if (input->dma->cbuf == idx)
  558. return count - left;
  559. free = input->dma->size - input->dma->coff;
  560. if (free > left)
  561. free = left;
  562. if (alt_dma)
  563. dma_sync_single_for_cpu(dev->dev,
  564. input->dma->pbuf[input->dma->cbuf],
  565. input->dma->size, DMA_FROM_DEVICE);
  566. ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] +
  567. input->dma->coff, free);
  568. if (ret)
  569. return -EFAULT;
  570. input->dma->coff += free;
  571. if (input->dma->coff == input->dma->size) {
  572. input->dma->coff = 0;
  573. input->dma->cbuf = (input->dma->cbuf + 1) %
  574. input->dma->num;
  575. }
  576. left -= free;
  577. buf += free;
  578. ddbwritel(dev,
  579. (input->dma->cbuf << 11) | (input->dma->coff >> 7),
  580. DMA_BUFFER_ACK(input->dma));
  581. }
  582. return count;
  583. }
  584. /****************************************************************************/
  585. /****************************************************************************/
  586. static ssize_t ts_write(struct file *file, const __user char *buf,
  587. size_t count, loff_t *ppos)
  588. {
  589. struct dvb_device *dvbdev = file->private_data;
  590. struct ddb_output *output = dvbdev->priv;
  591. struct ddb *dev = output->port->dev;
  592. size_t left = count;
  593. int stat;
  594. if (!dev->has_dma)
  595. return -EINVAL;
  596. while (left) {
  597. if (ddb_output_free(output) < 188) {
  598. if (file->f_flags & O_NONBLOCK)
  599. break;
  600. if (wait_event_interruptible(
  601. output->dma->wq,
  602. ddb_output_free(output) >= 188) < 0)
  603. break;
  604. }
  605. stat = ddb_output_write(output, buf, left);
  606. if (stat < 0)
  607. return stat;
  608. buf += stat;
  609. left -= stat;
  610. }
  611. return (left == count) ? -EAGAIN : (count - left);
  612. }
  613. static ssize_t ts_read(struct file *file, __user char *buf,
  614. size_t count, loff_t *ppos)
  615. {
  616. struct dvb_device *dvbdev = file->private_data;
  617. struct ddb_output *output = dvbdev->priv;
  618. struct ddb_input *input = output->port->input[0];
  619. struct ddb *dev = output->port->dev;
  620. size_t left = count;
  621. int stat;
  622. if (!dev->has_dma)
  623. return -EINVAL;
  624. while (left) {
  625. if (ddb_input_avail(input) < 188) {
  626. if (file->f_flags & O_NONBLOCK)
  627. break;
  628. if (wait_event_interruptible(
  629. input->dma->wq,
  630. ddb_input_avail(input) >= 188) < 0)
  631. break;
  632. }
  633. stat = ddb_input_read(input, buf, left);
  634. if (stat < 0)
  635. return stat;
  636. left -= stat;
  637. buf += stat;
  638. }
  639. return (count && (left == count)) ? -EAGAIN : (count - left);
  640. }
  641. static unsigned int ts_poll(struct file *file, poll_table *wait)
  642. {
  643. struct dvb_device *dvbdev = file->private_data;
  644. struct ddb_output *output = dvbdev->priv;
  645. struct ddb_input *input = output->port->input[0];
  646. unsigned int mask = 0;
  647. poll_wait(file, &input->dma->wq, wait);
  648. poll_wait(file, &output->dma->wq, wait);
  649. if (ddb_input_avail(input) >= 188)
  650. mask |= POLLIN | POLLRDNORM;
  651. if (ddb_output_free(output) >= 188)
  652. mask |= POLLOUT | POLLWRNORM;
  653. return mask;
  654. }
  655. static int ts_release(struct inode *inode, struct file *file)
  656. {
  657. struct dvb_device *dvbdev = file->private_data;
  658. struct ddb_output *output = NULL;
  659. struct ddb_input *input = NULL;
  660. if (dvbdev) {
  661. output = dvbdev->priv;
  662. input = output->port->input[0];
  663. }
  664. if ((file->f_flags & O_ACCMODE) == O_RDONLY) {
  665. if (!input)
  666. return -EINVAL;
  667. ddb_input_stop(input);
  668. } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
  669. if (!output)
  670. return -EINVAL;
  671. ddb_output_stop(output);
  672. }
  673. return dvb_generic_release(inode, file);
  674. }
  675. static int ts_open(struct inode *inode, struct file *file)
  676. {
  677. int err;
  678. struct dvb_device *dvbdev = file->private_data;
  679. struct ddb_output *output = NULL;
  680. struct ddb_input *input = NULL;
  681. if (dvbdev) {
  682. output = dvbdev->priv;
  683. input = output->port->input[0];
  684. }
  685. if ((file->f_flags & O_ACCMODE) == O_RDONLY) {
  686. if (!input)
  687. return -EINVAL;
  688. if (input->redo || input->redi)
  689. return -EBUSY;
  690. } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
  691. if (!output)
  692. return -EINVAL;
  693. } else
  694. return -EINVAL;
  695. err = dvb_generic_open(inode, file);
  696. if (err < 0)
  697. return err;
  698. if ((file->f_flags & O_ACCMODE) == O_RDONLY)
  699. ddb_input_start(input);
  700. else if ((file->f_flags & O_ACCMODE) == O_WRONLY)
  701. ddb_output_start(output);
  702. return err;
  703. }
  704. static const struct file_operations ci_fops = {
  705. .owner = THIS_MODULE,
  706. .read = ts_read,
  707. .write = ts_write,
  708. .open = ts_open,
  709. .release = ts_release,
  710. .poll = ts_poll,
  711. .mmap = 0,
  712. };
  713. static struct dvb_device dvbdev_ci = {
  714. .priv = 0,
  715. .readers = 1,
  716. .writers = 1,
  717. .users = 2,
  718. .fops = &ci_fops,
  719. };
  720. /****************************************************************************/
  721. /****************************************************************************/
  722. static int locked_gate_ctrl(struct dvb_frontend *fe, int enable)
  723. {
  724. struct ddb_input *input = fe->sec_priv;
  725. struct ddb_port *port = input->port;
  726. struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
  727. int status;
  728. if (enable) {
  729. mutex_lock(&port->i2c_gate_lock);
  730. status = dvb->i2c_gate_ctrl(fe, 1);
  731. } else {
  732. status = dvb->i2c_gate_ctrl(fe, 0);
  733. mutex_unlock(&port->i2c_gate_lock);
  734. }
  735. return status;
  736. }
  737. static int demod_attach_drxk(struct ddb_input *input)
  738. {
  739. struct i2c_adapter *i2c = &input->port->i2c->adap;
  740. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  741. struct device *dev = input->port->dev->dev;
  742. struct dvb_frontend *fe;
  743. struct drxk_config config;
  744. memset(&config, 0, sizeof(config));
  745. config.adr = 0x29 + (input->nr & 1);
  746. config.microcode_name = "drxk_a3.mc";
  747. fe = dvb->fe = dvb_attach(drxk_attach, &config, i2c);
  748. if (!fe) {
  749. dev_err(dev, "No DRXK found!\n");
  750. return -ENODEV;
  751. }
  752. fe->sec_priv = input;
  753. dvb->i2c_gate_ctrl = fe->ops.i2c_gate_ctrl;
  754. fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
  755. return 0;
  756. }
  757. static int tuner_attach_tda18271(struct ddb_input *input)
  758. {
  759. struct i2c_adapter *i2c = &input->port->i2c->adap;
  760. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  761. struct device *dev = input->port->dev->dev;
  762. struct dvb_frontend *fe;
  763. if (dvb->fe->ops.i2c_gate_ctrl)
  764. dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1);
  765. fe = dvb_attach(tda18271c2dd_attach, dvb->fe, i2c, 0x60);
  766. if (dvb->fe->ops.i2c_gate_ctrl)
  767. dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
  768. if (!fe) {
  769. dev_err(dev, "No TDA18271 found!\n");
  770. return -ENODEV;
  771. }
  772. return 0;
  773. }
  774. /******************************************************************************/
  775. /******************************************************************************/
  776. /******************************************************************************/
  777. static struct stv0367_config ddb_stv0367_config[] = {
  778. {
  779. .demod_address = 0x1f,
  780. .xtal = 27000000,
  781. .if_khz = 0,
  782. .if_iq_mode = FE_TER_NORMAL_IF_TUNER,
  783. .ts_mode = STV0367_SERIAL_PUNCT_CLOCK,
  784. .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
  785. }, {
  786. .demod_address = 0x1e,
  787. .xtal = 27000000,
  788. .if_khz = 0,
  789. .if_iq_mode = FE_TER_NORMAL_IF_TUNER,
  790. .ts_mode = STV0367_SERIAL_PUNCT_CLOCK,
  791. .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
  792. },
  793. };
  794. static int demod_attach_stv0367(struct ddb_input *input)
  795. {
  796. struct i2c_adapter *i2c = &input->port->i2c->adap;
  797. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  798. struct device *dev = input->port->dev->dev;
  799. struct dvb_frontend *fe;
  800. /* attach frontend */
  801. fe = dvb->fe = dvb_attach(stv0367ddb_attach,
  802. &ddb_stv0367_config[(input->nr & 1)], i2c);
  803. if (!dvb->fe) {
  804. dev_err(dev, "No stv0367 found!\n");
  805. return -ENODEV;
  806. }
  807. fe->sec_priv = input;
  808. dvb->i2c_gate_ctrl = fe->ops.i2c_gate_ctrl;
  809. fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
  810. return 0;
  811. }
  812. static int tuner_tda18212_ping(struct ddb_input *input, unsigned short adr)
  813. {
  814. struct i2c_adapter *adapter = &input->port->i2c->adap;
  815. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  816. struct device *dev = input->port->dev->dev;
  817. u8 tda_id[2];
  818. u8 subaddr = 0x00;
  819. dev_dbg(dev, "stv0367-tda18212 tuner ping\n");
  820. if (dvb->fe->ops.i2c_gate_ctrl)
  821. dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1);
  822. if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0)
  823. dev_dbg(dev, "tda18212 ping 1 fail\n");
  824. if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0)
  825. dev_warn(dev, "tda18212 ping failed, expect problems\n");
  826. if (dvb->fe->ops.i2c_gate_ctrl)
  827. dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
  828. return 0;
  829. }
  830. static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24)
  831. {
  832. struct i2c_adapter *i2c = &input->port->i2c->adap;
  833. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  834. struct device *dev = input->port->dev->dev;
  835. struct dvb_frontend *fe;
  836. struct cxd2841er_config cfg;
  837. /* the cxd2841er driver expects 8bit/shifted I2C addresses */
  838. cfg.i2c_addr = ((input->nr & 1) ? 0x6d : 0x6c) << 1;
  839. cfg.xtal = osc24 ? SONY_XTAL_24000 : SONY_XTAL_20500;
  840. cfg.flags = CXD2841ER_AUTO_IFHZ | CXD2841ER_EARLY_TUNE |
  841. CXD2841ER_NO_WAIT_LOCK | CXD2841ER_NO_AGCNEG |
  842. CXD2841ER_TSBITS;
  843. if (!par)
  844. cfg.flags |= CXD2841ER_TS_SERIAL;
  845. /* attach frontend */
  846. fe = dvb->fe = dvb_attach(cxd2841er_attach_t_c, &cfg, i2c);
  847. if (!dvb->fe) {
  848. dev_err(dev, "No cxd2837/38/43/54 found!\n");
  849. return -ENODEV;
  850. }
  851. fe->sec_priv = input;
  852. dvb->i2c_gate_ctrl = fe->ops.i2c_gate_ctrl;
  853. fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
  854. return 0;
  855. }
  856. static int tuner_attach_tda18212(struct ddb_input *input, u32 porttype)
  857. {
  858. struct i2c_adapter *adapter = &input->port->i2c->adap;
  859. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  860. struct device *dev = input->port->dev->dev;
  861. struct i2c_client *client;
  862. struct tda18212_config config = {
  863. .fe = dvb->fe,
  864. .if_dvbt_6 = 3550,
  865. .if_dvbt_7 = 3700,
  866. .if_dvbt_8 = 4150,
  867. .if_dvbt2_6 = 3250,
  868. .if_dvbt2_7 = 4000,
  869. .if_dvbt2_8 = 4000,
  870. .if_dvbc = 5000,
  871. };
  872. struct i2c_board_info board_info = {
  873. .type = "tda18212",
  874. .platform_data = &config,
  875. };
  876. if (input->nr & 1)
  877. board_info.addr = 0x63;
  878. else
  879. board_info.addr = 0x60;
  880. /* due to a hardware quirk with the I2C gate on the stv0367+tda18212
  881. * combo, the tda18212 must be probed by reading it's id _twice_ when
  882. * cold started, or it very likely will fail.
  883. */
  884. if (porttype == DDB_TUNER_DVBCT_ST)
  885. tuner_tda18212_ping(input, board_info.addr);
  886. request_module(board_info.type);
  887. /* perform tuner init/attach */
  888. client = i2c_new_device(adapter, &board_info);
  889. if (client == NULL || client->dev.driver == NULL)
  890. goto err;
  891. if (!try_module_get(client->dev.driver->owner)) {
  892. i2c_unregister_device(client);
  893. goto err;
  894. }
  895. dvb->i2c_client[0] = client;
  896. return 0;
  897. err:
  898. dev_notice(dev, "TDA18212 tuner not found. Device is not fully operational.\n");
  899. return -ENODEV;
  900. }
  901. /****************************************************************************/
  902. /****************************************************************************/
  903. /****************************************************************************/
  904. static struct stv090x_config stv0900 = {
  905. .device = STV0900,
  906. .demod_mode = STV090x_DUAL,
  907. .clk_mode = STV090x_CLK_EXT,
  908. .xtal = 27000000,
  909. .address = 0x69,
  910. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  911. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  912. .ts1_tei = 1,
  913. .ts2_tei = 1,
  914. .repeater_level = STV090x_RPTLEVEL_16,
  915. .adc1_range = STV090x_ADC_1Vpp,
  916. .adc2_range = STV090x_ADC_1Vpp,
  917. .diseqc_envelope_mode = true,
  918. };
  919. static struct stv090x_config stv0900_aa = {
  920. .device = STV0900,
  921. .demod_mode = STV090x_DUAL,
  922. .clk_mode = STV090x_CLK_EXT,
  923. .xtal = 27000000,
  924. .address = 0x68,
  925. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  926. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  927. .ts1_tei = 1,
  928. .ts2_tei = 1,
  929. .repeater_level = STV090x_RPTLEVEL_16,
  930. .adc1_range = STV090x_ADC_1Vpp,
  931. .adc2_range = STV090x_ADC_1Vpp,
  932. .diseqc_envelope_mode = true,
  933. };
  934. static struct stv6110x_config stv6110a = {
  935. .addr = 0x60,
  936. .refclk = 27000000,
  937. .clk_div = 1,
  938. };
  939. static struct stv6110x_config stv6110b = {
  940. .addr = 0x63,
  941. .refclk = 27000000,
  942. .clk_div = 1,
  943. };
  944. static int demod_attach_stv0900(struct ddb_input *input, int type)
  945. {
  946. struct i2c_adapter *i2c = &input->port->i2c->adap;
  947. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  948. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  949. struct device *dev = input->port->dev->dev;
  950. dvb->fe = dvb_attach(stv090x_attach, feconf, i2c,
  951. (input->nr & 1) ? STV090x_DEMODULATOR_1
  952. : STV090x_DEMODULATOR_0);
  953. if (!dvb->fe) {
  954. dev_err(dev, "No STV0900 found!\n");
  955. return -ENODEV;
  956. }
  957. if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0,
  958. 0, (input->nr & 1) ?
  959. (0x09 - type) : (0x0b - type))) {
  960. dev_err(dev, "No LNBH24 found!\n");
  961. return -ENODEV;
  962. }
  963. return 0;
  964. }
  965. static int tuner_attach_stv6110(struct ddb_input *input, int type)
  966. {
  967. struct i2c_adapter *i2c = &input->port->i2c->adap;
  968. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  969. struct device *dev = input->port->dev->dev;
  970. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  971. struct stv6110x_config *tunerconf = (input->nr & 1) ?
  972. &stv6110b : &stv6110a;
  973. const struct stv6110x_devctl *ctl;
  974. ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c);
  975. if (!ctl) {
  976. dev_err(dev, "No STV6110X found!\n");
  977. return -ENODEV;
  978. }
  979. dev_info(dev, "attach tuner input %d adr %02x\n",
  980. input->nr, tunerconf->addr);
  981. feconf->tuner_init = ctl->tuner_init;
  982. feconf->tuner_sleep = ctl->tuner_sleep;
  983. feconf->tuner_set_mode = ctl->tuner_set_mode;
  984. feconf->tuner_set_frequency = ctl->tuner_set_frequency;
  985. feconf->tuner_get_frequency = ctl->tuner_get_frequency;
  986. feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
  987. feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
  988. feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
  989. feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
  990. feconf->tuner_set_refclk = ctl->tuner_set_refclk;
  991. feconf->tuner_get_status = ctl->tuner_get_status;
  992. return 0;
  993. }
  994. static struct stv0910_cfg stv0910_p = {
  995. .adr = 0x68,
  996. .parallel = 1,
  997. .rptlvl = 4,
  998. .clk = 30000000,
  999. };
  1000. static struct lnbh25_config lnbh25_cfg = {
  1001. .i2c_address = 0x0c << 1,
  1002. .data2_config = LNBH25_TEN
  1003. };
  1004. static int demod_attach_stv0910(struct ddb_input *input, int type)
  1005. {
  1006. struct i2c_adapter *i2c = &input->port->i2c->adap;
  1007. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1008. struct device *dev = input->port->dev->dev;
  1009. struct stv0910_cfg cfg = stv0910_p;
  1010. struct lnbh25_config lnbcfg = lnbh25_cfg;
  1011. if (stv0910_single)
  1012. cfg.single = 1;
  1013. if (type)
  1014. cfg.parallel = 2;
  1015. dvb->fe = dvb_attach(stv0910_attach, i2c, &cfg, (input->nr & 1));
  1016. if (!dvb->fe) {
  1017. cfg.adr = 0x6c;
  1018. dvb->fe = dvb_attach(stv0910_attach, i2c,
  1019. &cfg, (input->nr & 1));
  1020. }
  1021. if (!dvb->fe) {
  1022. dev_err(dev, "No STV0910 found!\n");
  1023. return -ENODEV;
  1024. }
  1025. /* attach lnbh25 - leftshift by one as the lnbh25 driver expects 8bit
  1026. * i2c addresses
  1027. */
  1028. lnbcfg.i2c_address = (((input->nr & 1) ? 0x0d : 0x0c) << 1);
  1029. if (!dvb_attach(lnbh25_attach, dvb->fe, &lnbcfg, i2c)) {
  1030. lnbcfg.i2c_address = (((input->nr & 1) ? 0x09 : 0x08) << 1);
  1031. if (!dvb_attach(lnbh25_attach, dvb->fe, &lnbcfg, i2c)) {
  1032. dev_err(dev, "No LNBH25 found!\n");
  1033. return -ENODEV;
  1034. }
  1035. }
  1036. return 0;
  1037. }
  1038. static int tuner_attach_stv6111(struct ddb_input *input, int type)
  1039. {
  1040. struct i2c_adapter *i2c = &input->port->i2c->adap;
  1041. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1042. struct device *dev = input->port->dev->dev;
  1043. struct dvb_frontend *fe;
  1044. u8 adr = (type ? 0 : 4) + ((input->nr & 1) ? 0x63 : 0x60);
  1045. fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr);
  1046. if (!fe) {
  1047. fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr & ~4);
  1048. if (!fe) {
  1049. dev_err(dev, "No STV6111 found at 0x%02x!\n", adr);
  1050. return -ENODEV;
  1051. }
  1052. }
  1053. return 0;
  1054. }
  1055. static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
  1056. {
  1057. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  1058. struct ddb_input *input = dvbdmx->priv;
  1059. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1060. if (!dvb->users)
  1061. ddb_input_start_all(input);
  1062. return ++dvb->users;
  1063. }
  1064. static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  1065. {
  1066. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  1067. struct ddb_input *input = dvbdmx->priv;
  1068. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1069. if (--dvb->users)
  1070. return dvb->users;
  1071. ddb_input_stop_all(input);
  1072. return 0;
  1073. }
  1074. static void dvb_input_detach(struct ddb_input *input)
  1075. {
  1076. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1077. struct dvb_demux *dvbdemux = &dvb->demux;
  1078. struct i2c_client *client;
  1079. switch (dvb->attached) {
  1080. case 0x31:
  1081. client = dvb->i2c_client[0];
  1082. if (client) {
  1083. module_put(client->dev.driver->owner);
  1084. i2c_unregister_device(client);
  1085. }
  1086. if (dvb->fe2)
  1087. dvb_unregister_frontend(dvb->fe2);
  1088. if (dvb->fe)
  1089. dvb_unregister_frontend(dvb->fe);
  1090. /* fallthrough */
  1091. case 0x30:
  1092. if (dvb->fe2)
  1093. dvb_frontend_detach(dvb->fe2);
  1094. if (dvb->fe)
  1095. dvb_frontend_detach(dvb->fe);
  1096. dvb->fe = dvb->fe2 = NULL;
  1097. /* fallthrough */
  1098. case 0x20:
  1099. dvb_net_release(&dvb->dvbnet);
  1100. /* fallthrough */
  1101. case 0x12:
  1102. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  1103. &dvb->hw_frontend);
  1104. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  1105. &dvb->mem_frontend);
  1106. /* fallthrough */
  1107. case 0x11:
  1108. dvb_dmxdev_release(&dvb->dmxdev);
  1109. /* fallthrough */
  1110. case 0x10:
  1111. dvb_dmx_release(&dvb->demux);
  1112. /* fallthrough */
  1113. case 0x01:
  1114. break;
  1115. }
  1116. dvb->attached = 0x00;
  1117. }
  1118. static int dvb_register_adapters(struct ddb *dev)
  1119. {
  1120. int i, ret = 0;
  1121. struct ddb_port *port;
  1122. struct dvb_adapter *adap;
  1123. if (adapter_alloc == 3) {
  1124. port = &dev->port[0];
  1125. adap = port->dvb[0].adap;
  1126. ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
  1127. port->dev->dev,
  1128. adapter_nr);
  1129. if (ret < 0)
  1130. return ret;
  1131. port->dvb[0].adap_registered = 1;
  1132. for (i = 0; i < dev->port_num; i++) {
  1133. port = &dev->port[i];
  1134. port->dvb[0].adap = adap;
  1135. port->dvb[1].adap = adap;
  1136. }
  1137. return 0;
  1138. }
  1139. for (i = 0; i < dev->port_num; i++) {
  1140. port = &dev->port[i];
  1141. switch (port->class) {
  1142. case DDB_PORT_TUNER:
  1143. adap = port->dvb[0].adap;
  1144. ret = dvb_register_adapter(adap, "DDBridge",
  1145. THIS_MODULE,
  1146. port->dev->dev,
  1147. adapter_nr);
  1148. if (ret < 0)
  1149. return ret;
  1150. port->dvb[0].adap_registered = 1;
  1151. if (adapter_alloc > 0) {
  1152. port->dvb[1].adap = port->dvb[0].adap;
  1153. break;
  1154. }
  1155. adap = port->dvb[1].adap;
  1156. ret = dvb_register_adapter(adap, "DDBridge",
  1157. THIS_MODULE,
  1158. port->dev->dev,
  1159. adapter_nr);
  1160. if (ret < 0)
  1161. return ret;
  1162. port->dvb[1].adap_registered = 1;
  1163. break;
  1164. case DDB_PORT_CI:
  1165. case DDB_PORT_LOOP:
  1166. adap = port->dvb[0].adap;
  1167. ret = dvb_register_adapter(adap, "DDBridge",
  1168. THIS_MODULE,
  1169. port->dev->dev,
  1170. adapter_nr);
  1171. if (ret < 0)
  1172. return ret;
  1173. port->dvb[0].adap_registered = 1;
  1174. break;
  1175. default:
  1176. if (adapter_alloc < 2)
  1177. break;
  1178. adap = port->dvb[0].adap;
  1179. ret = dvb_register_adapter(adap, "DDBridge",
  1180. THIS_MODULE,
  1181. port->dev->dev,
  1182. adapter_nr);
  1183. if (ret < 0)
  1184. return ret;
  1185. port->dvb[0].adap_registered = 1;
  1186. break;
  1187. }
  1188. }
  1189. return ret;
  1190. }
  1191. static void dvb_unregister_adapters(struct ddb *dev)
  1192. {
  1193. int i;
  1194. struct ddb_port *port;
  1195. struct ddb_dvb *dvb;
  1196. for (i = 0; i < dev->link[0].info->port_num; i++) {
  1197. port = &dev->port[i];
  1198. dvb = &port->dvb[0];
  1199. if (dvb->adap_registered)
  1200. dvb_unregister_adapter(dvb->adap);
  1201. dvb->adap_registered = 0;
  1202. dvb = &port->dvb[1];
  1203. if (dvb->adap_registered)
  1204. dvb_unregister_adapter(dvb->adap);
  1205. dvb->adap_registered = 0;
  1206. }
  1207. }
  1208. static int dvb_input_attach(struct ddb_input *input)
  1209. {
  1210. int ret = 0;
  1211. struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
  1212. struct ddb_port *port = input->port;
  1213. struct dvb_adapter *adap = dvb->adap;
  1214. struct dvb_demux *dvbdemux = &dvb->demux;
  1215. int par = 0, osc24 = 0;
  1216. dvb->attached = 0x01;
  1217. dvbdemux->priv = input;
  1218. dvbdemux->dmx.capabilities = DMX_TS_FILTERING |
  1219. DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING;
  1220. dvbdemux->start_feed = start_feed;
  1221. dvbdemux->stop_feed = stop_feed;
  1222. dvbdemux->filternum = dvbdemux->feednum = 256;
  1223. ret = dvb_dmx_init(dvbdemux);
  1224. if (ret < 0)
  1225. return ret;
  1226. dvb->attached = 0x10;
  1227. dvb->dmxdev.filternum = 256;
  1228. dvb->dmxdev.demux = &dvbdemux->dmx;
  1229. ret = dvb_dmxdev_init(&dvb->dmxdev, adap);
  1230. if (ret < 0)
  1231. return ret;
  1232. dvb->attached = 0x11;
  1233. dvb->mem_frontend.source = DMX_MEMORY_FE;
  1234. dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->mem_frontend);
  1235. dvb->hw_frontend.source = DMX_FRONTEND_0;
  1236. dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->hw_frontend);
  1237. ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &dvb->hw_frontend);
  1238. if (ret < 0)
  1239. return ret;
  1240. dvb->attached = 0x12;
  1241. ret = dvb_net_init(adap, &dvb->dvbnet, dvb->dmxdev.demux);
  1242. if (ret < 0)
  1243. return ret;
  1244. dvb->attached = 0x20;
  1245. dvb->fe = dvb->fe2 = NULL;
  1246. switch (port->type) {
  1247. case DDB_TUNER_MXL5XX:
  1248. if (fe_attach_mxl5xx(input) < 0)
  1249. return -ENODEV;
  1250. break;
  1251. case DDB_TUNER_DVBS_ST:
  1252. if (demod_attach_stv0900(input, 0) < 0)
  1253. return -ENODEV;
  1254. if (tuner_attach_stv6110(input, 0) < 0)
  1255. return -ENODEV;
  1256. break;
  1257. case DDB_TUNER_DVBS_ST_AA:
  1258. if (demod_attach_stv0900(input, 1) < 0)
  1259. return -ENODEV;
  1260. if (tuner_attach_stv6110(input, 1) < 0)
  1261. return -ENODEV;
  1262. break;
  1263. case DDB_TUNER_DVBS_STV0910:
  1264. if (demod_attach_stv0910(input, 0) < 0)
  1265. return -ENODEV;
  1266. if (tuner_attach_stv6111(input, 0) < 0)
  1267. return -ENODEV;
  1268. break;
  1269. case DDB_TUNER_DVBS_STV0910_PR:
  1270. if (demod_attach_stv0910(input, 1) < 0)
  1271. return -ENODEV;
  1272. if (tuner_attach_stv6111(input, 1) < 0)
  1273. return -ENODEV;
  1274. break;
  1275. case DDB_TUNER_DVBS_STV0910_P:
  1276. if (demod_attach_stv0910(input, 0) < 0)
  1277. return -ENODEV;
  1278. if (tuner_attach_stv6111(input, 1) < 0)
  1279. return -ENODEV;
  1280. break;
  1281. case DDB_TUNER_DVBCT_TR:
  1282. if (demod_attach_drxk(input) < 0)
  1283. return -ENODEV;
  1284. if (tuner_attach_tda18271(input) < 0)
  1285. return -ENODEV;
  1286. break;
  1287. case DDB_TUNER_DVBCT_ST:
  1288. if (demod_attach_stv0367(input) < 0)
  1289. return -ENODEV;
  1290. if (tuner_attach_tda18212(input, port->type) < 0) {
  1291. if (dvb->fe2)
  1292. dvb_frontend_detach(dvb->fe2);
  1293. if (dvb->fe)
  1294. dvb_frontend_detach(dvb->fe);
  1295. return -ENODEV;
  1296. }
  1297. break;
  1298. case DDB_TUNER_DVBC2T2I_SONY_P:
  1299. if (input->port->dev->link[input->port->lnr].info->ts_quirks &
  1300. TS_QUIRK_ALT_OSC)
  1301. osc24 = 0;
  1302. else
  1303. osc24 = 1;
  1304. case DDB_TUNER_DVBCT2_SONY_P:
  1305. case DDB_TUNER_DVBC2T2_SONY_P:
  1306. case DDB_TUNER_ISDBT_SONY_P:
  1307. if (input->port->dev->link[input->port->lnr].info->ts_quirks
  1308. & TS_QUIRK_SERIAL)
  1309. par = 0;
  1310. else
  1311. par = 1;
  1312. if (demod_attach_cxd28xx(input, par, osc24) < 0)
  1313. return -ENODEV;
  1314. if (tuner_attach_tda18212(input, port->type) < 0) {
  1315. if (dvb->fe2)
  1316. dvb_frontend_detach(dvb->fe2);
  1317. if (dvb->fe)
  1318. dvb_frontend_detach(dvb->fe);
  1319. return -ENODEV;
  1320. }
  1321. break;
  1322. case DDB_TUNER_DVBC2T2I_SONY:
  1323. osc24 = 1;
  1324. case DDB_TUNER_DVBCT2_SONY:
  1325. case DDB_TUNER_DVBC2T2_SONY:
  1326. case DDB_TUNER_ISDBT_SONY:
  1327. if (demod_attach_cxd28xx(input, 0, osc24) < 0)
  1328. return -ENODEV;
  1329. if (tuner_attach_tda18212(input, port->type) < 0) {
  1330. if (dvb->fe2)
  1331. dvb_frontend_detach(dvb->fe2);
  1332. if (dvb->fe)
  1333. dvb_frontend_detach(dvb->fe);
  1334. return -ENODEV;
  1335. }
  1336. break;
  1337. default:
  1338. return 0;
  1339. }
  1340. dvb->attached = 0x30;
  1341. if (dvb->fe) {
  1342. if (dvb_register_frontend(adap, dvb->fe) < 0)
  1343. return -ENODEV;
  1344. if (dvb->fe2) {
  1345. if (dvb_register_frontend(adap, dvb->fe2) < 0)
  1346. return -ENODEV;
  1347. dvb->fe2->tuner_priv = dvb->fe->tuner_priv;
  1348. memcpy(&dvb->fe2->ops.tuner_ops,
  1349. &dvb->fe->ops.tuner_ops,
  1350. sizeof(struct dvb_tuner_ops));
  1351. }
  1352. }
  1353. dvb->attached = 0x31;
  1354. return 0;
  1355. }
  1356. static int port_has_encti(struct ddb_port *port)
  1357. {
  1358. struct device *dev = port->dev->dev;
  1359. u8 val;
  1360. int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val);
  1361. if (!ret)
  1362. dev_info(dev, "[0x20]=0x%02x\n", val);
  1363. return ret ? 0 : 1;
  1364. }
  1365. static int port_has_cxd(struct ddb_port *port, u8 *type)
  1366. {
  1367. u8 val;
  1368. u8 probe[4] = { 0xe0, 0x00, 0x00, 0x00 }, data[4];
  1369. struct i2c_msg msgs[2] = {{ .addr = 0x40, .flags = 0,
  1370. .buf = probe, .len = 4 },
  1371. { .addr = 0x40, .flags = I2C_M_RD,
  1372. .buf = data, .len = 4 } };
  1373. val = i2c_transfer(&port->i2c->adap, msgs, 2);
  1374. if (val != 2)
  1375. return 0;
  1376. if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43)
  1377. *type = 2;
  1378. else
  1379. *type = 1;
  1380. return 1;
  1381. }
  1382. static int port_has_xo2(struct ddb_port *port, u8 *type, u8 *id)
  1383. {
  1384. u8 probe[1] = { 0x00 }, data[4];
  1385. if (i2c_io(&port->i2c->adap, 0x10, probe, 1, data, 4))
  1386. return 0;
  1387. if (data[0] == 'D' && data[1] == 'F') {
  1388. *id = data[2];
  1389. *type = 1;
  1390. return 1;
  1391. }
  1392. if (data[0] == 'C' && data[1] == 'I') {
  1393. *id = data[2];
  1394. *type = 2;
  1395. return 1;
  1396. }
  1397. return 0;
  1398. }
  1399. static int port_has_stv0900(struct ddb_port *port)
  1400. {
  1401. u8 val;
  1402. if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
  1403. return 0;
  1404. return 1;
  1405. }
  1406. static int port_has_stv0900_aa(struct ddb_port *port, u8 *id)
  1407. {
  1408. if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, id) < 0)
  1409. return 0;
  1410. return 1;
  1411. }
  1412. static int port_has_drxks(struct ddb_port *port)
  1413. {
  1414. u8 val;
  1415. if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
  1416. return 0;
  1417. if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
  1418. return 0;
  1419. return 1;
  1420. }
  1421. static int port_has_stv0367(struct ddb_port *port)
  1422. {
  1423. u8 val;
  1424. if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0)
  1425. return 0;
  1426. if (val != 0x60)
  1427. return 0;
  1428. if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0)
  1429. return 0;
  1430. if (val != 0x60)
  1431. return 0;
  1432. return 1;
  1433. }
  1434. static int init_xo2(struct ddb_port *port)
  1435. {
  1436. struct i2c_adapter *i2c = &port->i2c->adap;
  1437. struct ddb *dev = port->dev;
  1438. u8 val, data[2];
  1439. int res;
  1440. res = i2c_read_regs(i2c, 0x10, 0x04, data, 2);
  1441. if (res < 0)
  1442. return res;
  1443. if (data[0] != 0x01) {
  1444. dev_info(dev->dev, "Port %d: invalid XO2\n", port->nr);
  1445. return -1;
  1446. }
  1447. i2c_read_reg(i2c, 0x10, 0x08, &val);
  1448. if (val != 0) {
  1449. i2c_write_reg(i2c, 0x10, 0x08, 0x00);
  1450. msleep(100);
  1451. }
  1452. /* Enable tuner power, disable pll, reset demods */
  1453. i2c_write_reg(i2c, 0x10, 0x08, 0x04);
  1454. usleep_range(2000, 3000);
  1455. /* Release demod resets */
  1456. i2c_write_reg(i2c, 0x10, 0x08, 0x07);
  1457. /* speed: 0=55,1=75,2=90,3=104 MBit/s */
  1458. i2c_write_reg(i2c, 0x10, 0x09, xo2_speed);
  1459. if (dev->link[port->lnr].info->con_clock) {
  1460. dev_info(dev->dev, "Setting continuous clock for XO2\n");
  1461. i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
  1462. i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
  1463. } else {
  1464. i2c_write_reg(i2c, 0x10, 0x0a, 0x01);
  1465. i2c_write_reg(i2c, 0x10, 0x0b, 0x01);
  1466. }
  1467. usleep_range(2000, 3000);
  1468. /* Start XO2 PLL */
  1469. i2c_write_reg(i2c, 0x10, 0x08, 0x87);
  1470. return 0;
  1471. }
  1472. static int init_xo2_ci(struct ddb_port *port)
  1473. {
  1474. struct i2c_adapter *i2c = &port->i2c->adap;
  1475. struct ddb *dev = port->dev;
  1476. u8 val, data[2];
  1477. int res;
  1478. res = i2c_read_regs(i2c, 0x10, 0x04, data, 2);
  1479. if (res < 0)
  1480. return res;
  1481. if (data[0] > 1) {
  1482. dev_info(dev->dev, "Port %d: invalid XO2 CI %02x\n",
  1483. port->nr, data[0]);
  1484. return -1;
  1485. }
  1486. dev_info(dev->dev, "Port %d: DuoFlex CI %u.%u\n",
  1487. port->nr, data[0], data[1]);
  1488. i2c_read_reg(i2c, 0x10, 0x08, &val);
  1489. if (val != 0) {
  1490. i2c_write_reg(i2c, 0x10, 0x08, 0x00);
  1491. msleep(100);
  1492. }
  1493. /* Enable both CI */
  1494. i2c_write_reg(i2c, 0x10, 0x08, 3);
  1495. usleep_range(2000, 3000);
  1496. /* speed: 0=55,1=75,2=90,3=104 MBit/s */
  1497. i2c_write_reg(i2c, 0x10, 0x09, 1);
  1498. i2c_write_reg(i2c, 0x10, 0x08, 0x83);
  1499. usleep_range(2000, 3000);
  1500. if (dev->link[port->lnr].info->con_clock) {
  1501. dev_info(dev->dev, "Setting continuous clock for DuoFlex CI\n");
  1502. i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
  1503. i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
  1504. } else {
  1505. i2c_write_reg(i2c, 0x10, 0x0a, 0x01);
  1506. i2c_write_reg(i2c, 0x10, 0x0b, 0x01);
  1507. }
  1508. return 0;
  1509. }
  1510. static int port_has_cxd28xx(struct ddb_port *port, u8 *id)
  1511. {
  1512. struct i2c_adapter *i2c = &port->i2c->adap;
  1513. int status;
  1514. status = i2c_write_reg(&port->i2c->adap, 0x6e, 0, 0);
  1515. if (status)
  1516. return 0;
  1517. status = i2c_read_reg(i2c, 0x6e, 0xfd, id);
  1518. if (status)
  1519. return 0;
  1520. return 1;
  1521. }
  1522. static char *xo2names[] = {
  1523. "DUAL DVB-S2", "DUAL DVB-C/T/T2",
  1524. "DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2",
  1525. "DUAL ATSC", "DUAL DVB-C/C2/T/T2,ISDB-T",
  1526. "", ""
  1527. };
  1528. static char *xo2types[] = {
  1529. "DVBS_ST", "DVBCT2_SONY",
  1530. "ISDBT_SONY", "DVBC2T2_SONY",
  1531. "ATSC_ST", "DVBC2T2I_SONY"
  1532. };
  1533. static void ddb_port_probe(struct ddb_port *port)
  1534. {
  1535. struct ddb *dev = port->dev;
  1536. u32 l = port->lnr;
  1537. u8 id, type;
  1538. port->name = "NO MODULE";
  1539. port->type_name = "NONE";
  1540. port->class = DDB_PORT_NONE;
  1541. /* Handle missing ports and ports without I2C */
  1542. if (port->nr == ts_loop) {
  1543. port->name = "TS LOOP";
  1544. port->class = DDB_PORT_LOOP;
  1545. return;
  1546. }
  1547. if (port->nr == 1 && dev->link[l].info->type == DDB_OCTOPUS_CI &&
  1548. dev->link[l].info->i2c_mask == 1) {
  1549. port->name = "NO TAB";
  1550. port->class = DDB_PORT_NONE;
  1551. return;
  1552. }
  1553. if (dev->link[l].info->type == DDB_OCTOPUS_MAX) {
  1554. port->name = "DUAL DVB-S2 MAX";
  1555. port->type_name = "MXL5XX";
  1556. port->class = DDB_PORT_TUNER;
  1557. port->type = DDB_TUNER_MXL5XX;
  1558. if (port->i2c)
  1559. ddbwritel(dev, I2C_SPEED_400,
  1560. port->i2c->regs + I2C_TIMING);
  1561. return;
  1562. }
  1563. if (port->nr > 1 && dev->link[l].info->type == DDB_OCTOPUS_CI) {
  1564. port->name = "CI internal";
  1565. port->type_name = "INTERNAL";
  1566. port->class = DDB_PORT_CI;
  1567. port->type = DDB_CI_INTERNAL;
  1568. }
  1569. if (!port->i2c)
  1570. return;
  1571. /* Probe ports with I2C */
  1572. if (port_has_cxd(port, &id)) {
  1573. if (id == 1) {
  1574. port->name = "CI";
  1575. port->type_name = "CXD2099";
  1576. port->class = DDB_PORT_CI;
  1577. port->type = DDB_CI_EXTERNAL_SONY;
  1578. ddbwritel(dev, I2C_SPEED_400,
  1579. port->i2c->regs + I2C_TIMING);
  1580. } else {
  1581. dev_info(dev->dev, "Port %d: Uninitialized DuoFlex\n",
  1582. port->nr);
  1583. return;
  1584. }
  1585. } else if (port_has_xo2(port, &type, &id)) {
  1586. ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1587. /*dev_info(dev->dev, "XO2 ID %02x\n", id);*/
  1588. if (type == 2) {
  1589. port->name = "DuoFlex CI";
  1590. port->class = DDB_PORT_CI;
  1591. port->type = DDB_CI_EXTERNAL_XO2;
  1592. port->type_name = "CI_XO2";
  1593. init_xo2_ci(port);
  1594. return;
  1595. }
  1596. id >>= 2;
  1597. if (id > 5) {
  1598. port->name = "unknown XO2 DuoFlex";
  1599. port->type_name = "UNKNOWN";
  1600. } else {
  1601. port->name = xo2names[id];
  1602. port->class = DDB_PORT_TUNER;
  1603. port->type = DDB_TUNER_XO2 + id;
  1604. port->type_name = xo2types[id];
  1605. init_xo2(port);
  1606. }
  1607. } else if (port_has_cxd28xx(port, &id)) {
  1608. switch (id) {
  1609. case 0xa4:
  1610. port->name = "DUAL DVB-C2T2 CXD2843";
  1611. port->type = DDB_TUNER_DVBC2T2_SONY_P;
  1612. port->type_name = "DVBC2T2_SONY";
  1613. break;
  1614. case 0xb1:
  1615. port->name = "DUAL DVB-CT2 CXD2837";
  1616. port->type = DDB_TUNER_DVBCT2_SONY_P;
  1617. port->type_name = "DVBCT2_SONY";
  1618. break;
  1619. case 0xb0:
  1620. port->name = "DUAL ISDB-T CXD2838";
  1621. port->type = DDB_TUNER_ISDBT_SONY_P;
  1622. port->type_name = "ISDBT_SONY";
  1623. break;
  1624. case 0xc1:
  1625. port->name = "DUAL DVB-C2T2 ISDB-T CXD2854";
  1626. port->type = DDB_TUNER_DVBC2T2I_SONY_P;
  1627. port->type_name = "DVBC2T2I_ISDBT_SONY";
  1628. break;
  1629. default:
  1630. return;
  1631. }
  1632. port->class = DDB_PORT_TUNER;
  1633. ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1634. } else if (port_has_stv0900(port)) {
  1635. port->name = "DUAL DVB-S2";
  1636. port->class = DDB_PORT_TUNER;
  1637. port->type = DDB_TUNER_DVBS_ST;
  1638. port->type_name = "DVBS_ST";
  1639. ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1640. } else if (port_has_stv0900_aa(port, &id)) {
  1641. port->name = "DUAL DVB-S2";
  1642. port->class = DDB_PORT_TUNER;
  1643. if (id == 0x51) {
  1644. if (port->nr == 0 &&
  1645. dev->link[l].info->ts_quirks & TS_QUIRK_REVERSED)
  1646. port->type = DDB_TUNER_DVBS_STV0910_PR;
  1647. else
  1648. port->type = DDB_TUNER_DVBS_STV0910_P;
  1649. port->type_name = "DVBS_ST_0910";
  1650. } else {
  1651. port->type = DDB_TUNER_DVBS_ST_AA;
  1652. port->type_name = "DVBS_ST_AA";
  1653. }
  1654. ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1655. } else if (port_has_drxks(port)) {
  1656. port->name = "DUAL DVB-C/T";
  1657. port->class = DDB_PORT_TUNER;
  1658. port->type = DDB_TUNER_DVBCT_TR;
  1659. port->type_name = "DVBCT_TR";
  1660. ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1661. } else if (port_has_stv0367(port)) {
  1662. port->name = "DUAL DVB-C/T";
  1663. port->class = DDB_PORT_TUNER;
  1664. port->type = DDB_TUNER_DVBCT_ST;
  1665. port->type_name = "DVBCT_ST";
  1666. ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1667. } else if (port_has_encti(port)) {
  1668. port->name = "ENCTI";
  1669. port->class = DDB_PORT_LOOP;
  1670. }
  1671. }
  1672. /****************************************************************************/
  1673. /****************************************************************************/
  1674. /****************************************************************************/
  1675. static int wait_ci_ready(struct ddb_ci *ci)
  1676. {
  1677. u32 count = 10;
  1678. ndelay(500);
  1679. do {
  1680. if (ddbreadl(ci->port->dev,
  1681. CI_CONTROL(ci->nr)) & CI_READY)
  1682. break;
  1683. usleep_range(1, 2);
  1684. if ((--count) == 0)
  1685. return -1;
  1686. } while (1);
  1687. return 0;
  1688. }
  1689. static int read_attribute_mem(struct dvb_ca_en50221 *ca,
  1690. int slot, int address)
  1691. {
  1692. struct ddb_ci *ci = ca->data;
  1693. u32 val, off = (address >> 1) & (CI_BUFFER_SIZE - 1);
  1694. if (address > CI_BUFFER_SIZE)
  1695. return -1;
  1696. ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address,
  1697. CI_DO_READ_ATTRIBUTES(ci->nr));
  1698. wait_ci_ready(ci);
  1699. val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off);
  1700. return val;
  1701. }
  1702. static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
  1703. int address, u8 value)
  1704. {
  1705. struct ddb_ci *ci = ca->data;
  1706. ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
  1707. CI_DO_ATTRIBUTE_RW(ci->nr));
  1708. wait_ci_ready(ci);
  1709. return 0;
  1710. }
  1711. static int read_cam_control(struct dvb_ca_en50221 *ca,
  1712. int slot, u8 address)
  1713. {
  1714. u32 count = 100;
  1715. struct ddb_ci *ci = ca->data;
  1716. u32 res;
  1717. ddbwritel(ci->port->dev, CI_READ_CMD | address,
  1718. CI_DO_IO_RW(ci->nr));
  1719. ndelay(500);
  1720. do {
  1721. res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr));
  1722. if (res & CI_READY)
  1723. break;
  1724. usleep_range(1, 2);
  1725. if ((--count) == 0)
  1726. return -1;
  1727. } while (1);
  1728. return 0xff & res;
  1729. }
  1730. static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
  1731. u8 address, u8 value)
  1732. {
  1733. struct ddb_ci *ci = ca->data;
  1734. ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
  1735. CI_DO_IO_RW(ci->nr));
  1736. wait_ci_ready(ci);
  1737. return 0;
  1738. }
  1739. static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
  1740. {
  1741. struct ddb_ci *ci = ca->data;
  1742. ddbwritel(ci->port->dev, CI_POWER_ON,
  1743. CI_CONTROL(ci->nr));
  1744. msleep(100);
  1745. ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM,
  1746. CI_CONTROL(ci->nr));
  1747. ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM,
  1748. CI_CONTROL(ci->nr));
  1749. udelay(20);
  1750. ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON,
  1751. CI_CONTROL(ci->nr));
  1752. return 0;
  1753. }
  1754. static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
  1755. {
  1756. struct ddb_ci *ci = ca->data;
  1757. ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr));
  1758. msleep(300);
  1759. return 0;
  1760. }
  1761. static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
  1762. {
  1763. struct ddb_ci *ci = ca->data;
  1764. u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
  1765. ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE,
  1766. CI_CONTROL(ci->nr));
  1767. return 0;
  1768. }
  1769. static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
  1770. {
  1771. struct ddb_ci *ci = ca->data;
  1772. u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
  1773. int stat = 0;
  1774. if (val & CI_CAM_DETECT)
  1775. stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
  1776. if (val & CI_CAM_READY)
  1777. stat |= DVB_CA_EN50221_POLL_CAM_READY;
  1778. return stat;
  1779. }
  1780. static struct dvb_ca_en50221 en_templ = {
  1781. .read_attribute_mem = read_attribute_mem,
  1782. .write_attribute_mem = write_attribute_mem,
  1783. .read_cam_control = read_cam_control,
  1784. .write_cam_control = write_cam_control,
  1785. .slot_reset = slot_reset,
  1786. .slot_shutdown = slot_shutdown,
  1787. .slot_ts_enable = slot_ts_enable,
  1788. .poll_slot_status = poll_slot_status,
  1789. };
  1790. static void ci_attach(struct ddb_port *port)
  1791. {
  1792. struct ddb_ci *ci = 0;
  1793. ci = kzalloc(sizeof(*ci), GFP_KERNEL);
  1794. if (!ci)
  1795. return;
  1796. memcpy(&ci->en, &en_templ, sizeof(en_templ));
  1797. ci->en.data = ci;
  1798. port->en = &ci->en;
  1799. ci->port = port;
  1800. ci->nr = port->nr - 2;
  1801. }
  1802. /****************************************************************************/
  1803. /****************************************************************************/
  1804. /****************************************************************************/
  1805. static int write_creg(struct ddb_ci *ci, u8 data, u8 mask)
  1806. {
  1807. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1808. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1809. ci->port->creg = (ci->port->creg & ~mask) | data;
  1810. return i2c_write_reg(i2c, adr, 0x02, ci->port->creg);
  1811. }
  1812. static int read_attribute_mem_xo2(struct dvb_ca_en50221 *ca,
  1813. int slot, int address)
  1814. {
  1815. struct ddb_ci *ci = ca->data;
  1816. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1817. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1818. int res;
  1819. u8 val;
  1820. res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val);
  1821. return res ? res : val;
  1822. }
  1823. static int write_attribute_mem_xo2(struct dvb_ca_en50221 *ca, int slot,
  1824. int address, u8 value)
  1825. {
  1826. struct ddb_ci *ci = ca->data;
  1827. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1828. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1829. return i2c_write_reg16(i2c, adr, 0x8000 | address, value);
  1830. }
  1831. static int read_cam_control_xo2(struct dvb_ca_en50221 *ca,
  1832. int slot, u8 address)
  1833. {
  1834. struct ddb_ci *ci = ca->data;
  1835. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1836. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1837. u8 val;
  1838. int res;
  1839. res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val);
  1840. return res ? res : val;
  1841. }
  1842. static int write_cam_control_xo2(struct dvb_ca_en50221 *ca, int slot,
  1843. u8 address, u8 value)
  1844. {
  1845. struct ddb_ci *ci = ca->data;
  1846. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1847. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1848. return i2c_write_reg(i2c, adr, 0x20 | (address & 3), value);
  1849. }
  1850. static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
  1851. {
  1852. struct ddb_ci *ci = ca->data;
  1853. dev_dbg(ci->port->dev->dev, "%s\n", __func__);
  1854. write_creg(ci, 0x01, 0x01);
  1855. write_creg(ci, 0x04, 0x04);
  1856. msleep(20);
  1857. write_creg(ci, 0x02, 0x02);
  1858. write_creg(ci, 0x00, 0x04);
  1859. write_creg(ci, 0x18, 0x18);
  1860. return 0;
  1861. }
  1862. static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
  1863. {
  1864. struct ddb_ci *ci = ca->data;
  1865. dev_dbg(ci->port->dev->dev, "%s\n", __func__);
  1866. write_creg(ci, 0x10, 0xff);
  1867. write_creg(ci, 0x08, 0x08);
  1868. return 0;
  1869. }
  1870. static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot)
  1871. {
  1872. struct ddb_ci *ci = ca->data;
  1873. dev_info(ci->port->dev->dev, "%s\n", __func__);
  1874. write_creg(ci, 0x00, 0x10);
  1875. return 0;
  1876. }
  1877. static int poll_slot_status_xo2(struct dvb_ca_en50221 *ca, int slot, int open)
  1878. {
  1879. struct ddb_ci *ci = ca->data;
  1880. struct i2c_adapter *i2c = &ci->port->i2c->adap;
  1881. u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
  1882. u8 val = 0;
  1883. int stat = 0;
  1884. i2c_read_reg(i2c, adr, 0x01, &val);
  1885. if (val & 2)
  1886. stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
  1887. if (val & 1)
  1888. stat |= DVB_CA_EN50221_POLL_CAM_READY;
  1889. return stat;
  1890. }
  1891. static struct dvb_ca_en50221 en_xo2_templ = {
  1892. .read_attribute_mem = read_attribute_mem_xo2,
  1893. .write_attribute_mem = write_attribute_mem_xo2,
  1894. .read_cam_control = read_cam_control_xo2,
  1895. .write_cam_control = write_cam_control_xo2,
  1896. .slot_reset = slot_reset_xo2,
  1897. .slot_shutdown = slot_shutdown_xo2,
  1898. .slot_ts_enable = slot_ts_enable_xo2,
  1899. .poll_slot_status = poll_slot_status_xo2,
  1900. };
  1901. static void ci_xo2_attach(struct ddb_port *port)
  1902. {
  1903. struct ddb_ci *ci;
  1904. ci = kzalloc(sizeof(*ci), GFP_KERNEL);
  1905. if (!ci)
  1906. return;
  1907. memcpy(&ci->en, &en_xo2_templ, sizeof(en_xo2_templ));
  1908. ci->en.data = ci;
  1909. port->en = &ci->en;
  1910. ci->port = port;
  1911. ci->nr = port->nr - 2;
  1912. ci->port->creg = 0;
  1913. write_creg(ci, 0x10, 0xff);
  1914. write_creg(ci, 0x08, 0x08);
  1915. }
  1916. /****************************************************************************/
  1917. /****************************************************************************/
  1918. /****************************************************************************/
  1919. struct cxd2099_cfg cxd_cfg = {
  1920. .bitrate = 72000,
  1921. .adr = 0x40,
  1922. .polarity = 1,
  1923. .clock_mode = 1,
  1924. .max_i2c = 512,
  1925. };
  1926. static int ddb_ci_attach(struct ddb_port *port)
  1927. {
  1928. switch (port->type) {
  1929. case DDB_CI_EXTERNAL_SONY:
  1930. cxd_cfg.bitrate = ci_bitrate;
  1931. port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
  1932. if (!port->en)
  1933. return -ENODEV;
  1934. dvb_ca_en50221_init(port->dvb[0].adap,
  1935. port->en, 0, 1);
  1936. break;
  1937. case DDB_CI_EXTERNAL_XO2:
  1938. case DDB_CI_EXTERNAL_XO2_B:
  1939. ci_xo2_attach(port);
  1940. if (!port->en)
  1941. return -ENODEV;
  1942. dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1);
  1943. break;
  1944. case DDB_CI_INTERNAL:
  1945. ci_attach(port);
  1946. if (!port->en)
  1947. return -ENODEV;
  1948. dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1);
  1949. break;
  1950. }
  1951. return 0;
  1952. }
  1953. static int ddb_port_attach(struct ddb_port *port)
  1954. {
  1955. int ret = 0;
  1956. switch (port->class) {
  1957. case DDB_PORT_TUNER:
  1958. ret = dvb_input_attach(port->input[0]);
  1959. if (ret < 0)
  1960. break;
  1961. ret = dvb_input_attach(port->input[1]);
  1962. if (ret < 0)
  1963. break;
  1964. port->input[0]->redi = port->input[0];
  1965. port->input[1]->redi = port->input[1];
  1966. break;
  1967. case DDB_PORT_CI:
  1968. ret = ddb_ci_attach(port);
  1969. if (ret < 0)
  1970. break;
  1971. case DDB_PORT_LOOP:
  1972. ret = dvb_register_device(port->dvb[0].adap,
  1973. &port->dvb[0].dev,
  1974. &dvbdev_ci, (void *) port->output,
  1975. DVB_DEVICE_SEC, 0);
  1976. break;
  1977. default:
  1978. break;
  1979. }
  1980. if (ret < 0)
  1981. dev_err(port->dev->dev, "port_attach on port %d failed\n",
  1982. port->nr);
  1983. return ret;
  1984. }
  1985. int ddb_ports_attach(struct ddb *dev)
  1986. {
  1987. int i, ret = 0;
  1988. struct ddb_port *port;
  1989. if (dev->port_num) {
  1990. ret = dvb_register_adapters(dev);
  1991. if (ret < 0) {
  1992. dev_err(dev->dev, "Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
  1993. return ret;
  1994. }
  1995. }
  1996. for (i = 0; i < dev->port_num; i++) {
  1997. port = &dev->port[i];
  1998. ret = ddb_port_attach(port);
  1999. }
  2000. return ret;
  2001. }
  2002. void ddb_ports_detach(struct ddb *dev)
  2003. {
  2004. int i;
  2005. struct ddb_port *port;
  2006. for (i = 0; i < dev->port_num; i++) {
  2007. port = &dev->port[i];
  2008. switch (port->class) {
  2009. case DDB_PORT_TUNER:
  2010. dvb_input_detach(port->input[0]);
  2011. dvb_input_detach(port->input[1]);
  2012. break;
  2013. case DDB_PORT_CI:
  2014. case DDB_PORT_LOOP:
  2015. if (port->dvb[0].dev)
  2016. dvb_unregister_device(port->dvb[0].dev);
  2017. if (port->en) {
  2018. dvb_ca_en50221_release(port->en);
  2019. kfree(port->en);
  2020. port->en = NULL;
  2021. }
  2022. break;
  2023. }
  2024. }
  2025. dvb_unregister_adapters(dev);
  2026. }
  2027. /* Copy input DMA pointers to output DMA and ACK. */
  2028. static void input_write_output(struct ddb_input *input,
  2029. struct ddb_output *output)
  2030. {
  2031. ddbwritel(output->port->dev,
  2032. input->dma->stat, DMA_BUFFER_ACK(output->dma));
  2033. output->dma->cbuf = (input->dma->stat >> 11) & 0x1f;
  2034. output->dma->coff = (input->dma->stat & 0x7ff) << 7;
  2035. }
  2036. static void output_ack_input(struct ddb_output *output,
  2037. struct ddb_input *input)
  2038. {
  2039. ddbwritel(input->port->dev,
  2040. output->dma->stat, DMA_BUFFER_ACK(input->dma));
  2041. }
  2042. static void input_write_dvb(struct ddb_input *input,
  2043. struct ddb_input *input2)
  2044. {
  2045. struct ddb_dvb *dvb = &input2->port->dvb[input2->nr & 1];
  2046. struct ddb_dma *dma, *dma2;
  2047. struct ddb *dev = input->port->dev;
  2048. int ack = 1;
  2049. dma = dma2 = input->dma;
  2050. /* if there also is an output connected, do not ACK.
  2051. * input_write_output will ACK.
  2052. */
  2053. if (input->redo) {
  2054. dma2 = input->redo->dma;
  2055. ack = 0;
  2056. }
  2057. while (dma->cbuf != ((dma->stat >> 11) & 0x1f)
  2058. || (4 & dma->ctrl)) {
  2059. if (4 & dma->ctrl) {
  2060. /* dev_err(dev->dev, "Overflow dma %d\n", dma->nr); */
  2061. ack = 1;
  2062. }
  2063. if (alt_dma)
  2064. dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
  2065. dma2->size, DMA_FROM_DEVICE);
  2066. dvb_dmx_swfilter_packets(&dvb->demux,
  2067. dma2->vbuf[dma->cbuf],
  2068. dma2->size / 188);
  2069. dma->cbuf = (dma->cbuf + 1) % dma2->num;
  2070. if (ack)
  2071. ddbwritel(dev, (dma->cbuf << 11),
  2072. DMA_BUFFER_ACK(dma));
  2073. dma->stat = safe_ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
  2074. dma->ctrl = safe_ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
  2075. }
  2076. }
  2077. static void input_work(struct work_struct *work)
  2078. {
  2079. struct ddb_dma *dma = container_of(work, struct ddb_dma, work);
  2080. struct ddb_input *input = (struct ddb_input *) dma->io;
  2081. struct ddb *dev = input->port->dev;
  2082. unsigned long flags;
  2083. spin_lock_irqsave(&dma->lock, flags);
  2084. if (!dma->running) {
  2085. spin_unlock_irqrestore(&dma->lock, flags);
  2086. return;
  2087. }
  2088. dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
  2089. dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
  2090. if (input->redi)
  2091. input_write_dvb(input, input->redi);
  2092. if (input->redo)
  2093. input_write_output(input, input->redo);
  2094. wake_up(&dma->wq);
  2095. spin_unlock_irqrestore(&dma->lock, flags);
  2096. }
  2097. static void input_handler(unsigned long data)
  2098. {
  2099. struct ddb_input *input = (struct ddb_input *) data;
  2100. struct ddb_dma *dma = input->dma;
  2101. /* If there is no input connected, input_tasklet() will
  2102. * just copy pointers and ACK. So, there is no need to go
  2103. * through the tasklet scheduler.
  2104. */
  2105. if (input->redi)
  2106. queue_work(ddb_wq, &dma->work);
  2107. else
  2108. input_work(&dma->work);
  2109. }
  2110. static void output_handler(unsigned long data)
  2111. {
  2112. struct ddb_output *output = (struct ddb_output *) data;
  2113. struct ddb_dma *dma = output->dma;
  2114. struct ddb *dev = output->port->dev;
  2115. spin_lock(&dma->lock);
  2116. if (!dma->running) {
  2117. spin_unlock(&dma->lock);
  2118. return;
  2119. }
  2120. dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
  2121. dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
  2122. if (output->redi)
  2123. output_ack_input(output, output->redi);
  2124. wake_up(&dma->wq);
  2125. spin_unlock(&dma->lock);
  2126. }
  2127. /****************************************************************************/
  2128. /****************************************************************************/
  2129. static struct ddb_regmap *io_regmap(struct ddb_io *io, int link)
  2130. {
  2131. struct ddb_info *info;
  2132. if (link)
  2133. info = io->port->dev->link[io->port->lnr].info;
  2134. else
  2135. info = io->port->dev->link[0].info;
  2136. if (!info)
  2137. return NULL;
  2138. return info->regmap;
  2139. }
  2140. static void ddb_dma_init(struct ddb_io *io, int nr, int out)
  2141. {
  2142. struct ddb_dma *dma;
  2143. struct ddb_regmap *rm = io_regmap(io, 0);
  2144. dma = out ? &io->port->dev->odma[nr] : &io->port->dev->idma[nr];
  2145. io->dma = dma;
  2146. dma->io = io;
  2147. spin_lock_init(&dma->lock);
  2148. init_waitqueue_head(&dma->wq);
  2149. if (out) {
  2150. dma->regs = rm->odma->base + rm->odma->size * nr;
  2151. dma->bufregs = rm->odma_buf->base + rm->odma_buf->size * nr;
  2152. dma->num = OUTPUT_DMA_BUFS;
  2153. dma->size = OUTPUT_DMA_SIZE;
  2154. dma->div = OUTPUT_DMA_IRQ_DIV;
  2155. } else {
  2156. INIT_WORK(&dma->work, input_work);
  2157. dma->regs = rm->idma->base + rm->idma->size * nr;
  2158. dma->bufregs = rm->idma_buf->base + rm->idma_buf->size * nr;
  2159. dma->num = INPUT_DMA_BUFS;
  2160. dma->size = INPUT_DMA_SIZE;
  2161. dma->div = INPUT_DMA_IRQ_DIV;
  2162. }
  2163. ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
  2164. dev_dbg(io->port->dev->dev, "init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
  2165. io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
  2166. }
  2167. static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
  2168. {
  2169. struct ddb *dev = port->dev;
  2170. struct ddb_input *input = &dev->input[anr];
  2171. struct ddb_regmap *rm;
  2172. port->input[pnr] = input;
  2173. input->nr = nr;
  2174. input->port = port;
  2175. rm = io_regmap(input, 1);
  2176. input->regs = DDB_LINK_TAG(port->lnr) |
  2177. (rm->input->base + rm->input->size * nr);
  2178. dev_dbg(dev->dev, "init link %u, input %u, regs %08x\n",
  2179. port->lnr, nr, input->regs);
  2180. if (dev->has_dma) {
  2181. struct ddb_regmap *rm0 = io_regmap(input, 0);
  2182. u32 base = rm0->irq_base_idma;
  2183. u32 dma_nr = nr;
  2184. if (port->lnr)
  2185. dma_nr += 32 + (port->lnr - 1) * 8;
  2186. dev_dbg(dev->dev, "init link %u, input %u, handler %u\n",
  2187. port->lnr, nr, dma_nr + base);
  2188. dev->handler[0][dma_nr + base] = input_handler;
  2189. dev->handler_data[0][dma_nr + base] = (unsigned long) input;
  2190. ddb_dma_init(input, dma_nr, 0);
  2191. }
  2192. }
  2193. static void ddb_output_init(struct ddb_port *port, int nr)
  2194. {
  2195. struct ddb *dev = port->dev;
  2196. struct ddb_output *output = &dev->output[nr];
  2197. struct ddb_regmap *rm;
  2198. port->output = output;
  2199. output->nr = nr;
  2200. output->port = port;
  2201. rm = io_regmap(output, 1);
  2202. output->regs = DDB_LINK_TAG(port->lnr) |
  2203. (rm->output->base + rm->output->size * nr);
  2204. dev_dbg(dev->dev, "init link %u, output %u, regs %08x\n",
  2205. port->lnr, nr, output->regs);
  2206. if (dev->has_dma) {
  2207. struct ddb_regmap *rm0 = io_regmap(output, 0);
  2208. u32 base = rm0->irq_base_odma;
  2209. dev->handler[0][nr + base] = output_handler;
  2210. dev->handler_data[0][nr + base] = (unsigned long) output;
  2211. ddb_dma_init(output, nr, 1);
  2212. }
  2213. }
  2214. static int ddb_port_match_i2c(struct ddb_port *port)
  2215. {
  2216. struct ddb *dev = port->dev;
  2217. u32 i;
  2218. for (i = 0; i < dev->i2c_num; i++) {
  2219. if (dev->i2c[i].link == port->lnr &&
  2220. dev->i2c[i].nr == port->nr) {
  2221. port->i2c = &dev->i2c[i];
  2222. return 1;
  2223. }
  2224. }
  2225. return 0;
  2226. }
  2227. static int ddb_port_match_link_i2c(struct ddb_port *port)
  2228. {
  2229. struct ddb *dev = port->dev;
  2230. u32 i;
  2231. for (i = 0; i < dev->i2c_num; i++) {
  2232. if (dev->i2c[i].link == port->lnr) {
  2233. port->i2c = &dev->i2c[i];
  2234. return 1;
  2235. }
  2236. }
  2237. return 0;
  2238. }
  2239. void ddb_ports_init(struct ddb *dev)
  2240. {
  2241. u32 i, l, p;
  2242. struct ddb_port *port;
  2243. struct ddb_info *info;
  2244. struct ddb_regmap *rm;
  2245. for (p = l = 0; l < DDB_MAX_LINK; l++) {
  2246. info = dev->link[l].info;
  2247. if (!info)
  2248. continue;
  2249. rm = info->regmap;
  2250. if (!rm)
  2251. continue;
  2252. for (i = 0; i < info->port_num; i++, p++) {
  2253. port = &dev->port[p];
  2254. port->dev = dev;
  2255. port->nr = i;
  2256. port->lnr = l;
  2257. port->pnr = p;
  2258. port->gap = 0xffffffff;
  2259. port->obr = ci_bitrate;
  2260. mutex_init(&port->i2c_gate_lock);
  2261. if (!ddb_port_match_i2c(port)) {
  2262. if (info->type == DDB_OCTOPUS_MAX)
  2263. ddb_port_match_link_i2c(port);
  2264. }
  2265. ddb_port_probe(port);
  2266. port->dvb[0].adap = &dev->adap[2 * p];
  2267. port->dvb[1].adap = &dev->adap[2 * p + 1];
  2268. if ((port->class == DDB_PORT_NONE) && i && p &&
  2269. dev->port[p - 1].type == DDB_CI_EXTERNAL_XO2) {
  2270. port->class = DDB_PORT_CI;
  2271. port->type = DDB_CI_EXTERNAL_XO2_B;
  2272. port->name = "DuoFlex CI_B";
  2273. port->i2c = dev->port[p - 1].i2c;
  2274. }
  2275. dev_info(dev->dev, "Port %u: Link %u, Link Port %u (TAB %u): %s\n",
  2276. port->pnr, port->lnr, port->nr, port->nr + 1,
  2277. port->name);
  2278. if (port->class == DDB_PORT_CI &&
  2279. port->type == DDB_CI_EXTERNAL_XO2) {
  2280. ddb_input_init(port, 2 * i, 0, 2 * i);
  2281. ddb_output_init(port, i);
  2282. continue;
  2283. }
  2284. if (port->class == DDB_PORT_CI &&
  2285. port->type == DDB_CI_EXTERNAL_XO2_B) {
  2286. ddb_input_init(port, 2 * i - 1, 0, 2 * i - 1);
  2287. ddb_output_init(port, i);
  2288. continue;
  2289. }
  2290. if (port->class == DDB_PORT_NONE)
  2291. continue;
  2292. switch (dev->link[l].info->type) {
  2293. case DDB_OCTOPUS_CI:
  2294. if (i >= 2) {
  2295. ddb_input_init(port, 2 + i, 0, 2 + i);
  2296. ddb_input_init(port, 4 + i, 1, 4 + i);
  2297. ddb_output_init(port, i);
  2298. break;
  2299. } /* fallthrough */
  2300. case DDB_OCTOPUS:
  2301. ddb_input_init(port, 2 * i, 0, 2 * i);
  2302. ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1);
  2303. ddb_output_init(port, i);
  2304. break;
  2305. case DDB_OCTOPUS_MAX:
  2306. case DDB_OCTOPUS_MAX_CT:
  2307. ddb_input_init(port, 2 * i, 0, 2 * p);
  2308. ddb_input_init(port, 2 * i + 1, 1, 2 * p + 1);
  2309. break;
  2310. default:
  2311. break;
  2312. }
  2313. }
  2314. }
  2315. dev->port_num = p;
  2316. }
  2317. void ddb_ports_release(struct ddb *dev)
  2318. {
  2319. int i;
  2320. struct ddb_port *port;
  2321. for (i = 0; i < dev->port_num; i++) {
  2322. port = &dev->port[i];
  2323. if (port->input[0] && port->input[0]->dma)
  2324. cancel_work_sync(&port->input[0]->dma->work);
  2325. if (port->input[1] && port->input[1]->dma)
  2326. cancel_work_sync(&port->input[1]->dma->work);
  2327. if (port->output && port->output->dma)
  2328. cancel_work_sync(&port->output->dma->work);
  2329. }
  2330. }
  2331. /****************************************************************************/
  2332. /****************************************************************************/
  2333. /****************************************************************************/
  2334. #define IRQ_HANDLE(_nr) \
  2335. do { if ((s & (1UL << ((_nr) & 0x1f))) && dev->handler[0][_nr]) \
  2336. dev->handler[0][_nr](dev->handler_data[0][_nr]); } \
  2337. while (0)
  2338. static void irq_handle_msg(struct ddb *dev, u32 s)
  2339. {
  2340. dev->i2c_irq++;
  2341. IRQ_HANDLE(0);
  2342. IRQ_HANDLE(1);
  2343. IRQ_HANDLE(2);
  2344. IRQ_HANDLE(3);
  2345. }
  2346. static void irq_handle_io(struct ddb *dev, u32 s)
  2347. {
  2348. dev->ts_irq++;
  2349. if ((s & 0x000000f0)) {
  2350. IRQ_HANDLE(4);
  2351. IRQ_HANDLE(5);
  2352. IRQ_HANDLE(6);
  2353. IRQ_HANDLE(7);
  2354. }
  2355. if ((s & 0x0000ff00)) {
  2356. IRQ_HANDLE(8);
  2357. IRQ_HANDLE(9);
  2358. IRQ_HANDLE(10);
  2359. IRQ_HANDLE(11);
  2360. IRQ_HANDLE(12);
  2361. IRQ_HANDLE(13);
  2362. IRQ_HANDLE(14);
  2363. IRQ_HANDLE(15);
  2364. }
  2365. if ((s & 0x00ff0000)) {
  2366. IRQ_HANDLE(16);
  2367. IRQ_HANDLE(17);
  2368. IRQ_HANDLE(18);
  2369. IRQ_HANDLE(19);
  2370. IRQ_HANDLE(20);
  2371. IRQ_HANDLE(21);
  2372. IRQ_HANDLE(22);
  2373. IRQ_HANDLE(23);
  2374. }
  2375. if ((s & 0xff000000)) {
  2376. IRQ_HANDLE(24);
  2377. IRQ_HANDLE(25);
  2378. IRQ_HANDLE(26);
  2379. IRQ_HANDLE(27);
  2380. IRQ_HANDLE(28);
  2381. IRQ_HANDLE(29);
  2382. IRQ_HANDLE(30);
  2383. IRQ_HANDLE(31);
  2384. }
  2385. }
  2386. irqreturn_t ddb_irq_handler0(int irq, void *dev_id)
  2387. {
  2388. struct ddb *dev = (struct ddb *) dev_id;
  2389. u32 s = ddbreadl(dev, INTERRUPT_STATUS);
  2390. do {
  2391. if (s & 0x80000000)
  2392. return IRQ_NONE;
  2393. if (!(s & 0xfffff00))
  2394. return IRQ_NONE;
  2395. ddbwritel(dev, s & 0xfffff00, INTERRUPT_ACK);
  2396. irq_handle_io(dev, s);
  2397. } while ((s = ddbreadl(dev, INTERRUPT_STATUS)));
  2398. return IRQ_HANDLED;
  2399. }
  2400. irqreturn_t ddb_irq_handler1(int irq, void *dev_id)
  2401. {
  2402. struct ddb *dev = (struct ddb *) dev_id;
  2403. u32 s = ddbreadl(dev, INTERRUPT_STATUS);
  2404. do {
  2405. if (s & 0x80000000)
  2406. return IRQ_NONE;
  2407. if (!(s & 0x0000f))
  2408. return IRQ_NONE;
  2409. ddbwritel(dev, s & 0x0000f, INTERRUPT_ACK);
  2410. irq_handle_msg(dev, s);
  2411. } while ((s = ddbreadl(dev, INTERRUPT_STATUS)));
  2412. return IRQ_HANDLED;
  2413. }
  2414. irqreturn_t ddb_irq_handler(int irq, void *dev_id)
  2415. {
  2416. struct ddb *dev = (struct ddb *) dev_id;
  2417. u32 s = ddbreadl(dev, INTERRUPT_STATUS);
  2418. int ret = IRQ_HANDLED;
  2419. if (!s)
  2420. return IRQ_NONE;
  2421. do {
  2422. if (s & 0x80000000)
  2423. return IRQ_NONE;
  2424. ddbwritel(dev, s, INTERRUPT_ACK);
  2425. if (s & 0x0000000f)
  2426. irq_handle_msg(dev, s);
  2427. if (s & 0x0fffff00)
  2428. irq_handle_io(dev, s);
  2429. } while ((s = ddbreadl(dev, INTERRUPT_STATUS)));
  2430. return ret;
  2431. }
  2432. /****************************************************************************/
  2433. /****************************************************************************/
  2434. /****************************************************************************/
  2435. static int reg_wait(struct ddb *dev, u32 reg, u32 bit)
  2436. {
  2437. u32 count = 0;
  2438. while (safe_ddbreadl(dev, reg) & bit) {
  2439. ndelay(10);
  2440. if (++count == 100)
  2441. return -1;
  2442. }
  2443. return 0;
  2444. }
  2445. static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf,
  2446. u32 rlen)
  2447. {
  2448. u32 data, shift;
  2449. u32 tag = DDB_LINK_TAG(lnr);
  2450. struct ddb_link *link = &dev->link[lnr];
  2451. mutex_lock(&link->flash_mutex);
  2452. if (wlen > 4)
  2453. ddbwritel(dev, 1, tag | SPI_CONTROL);
  2454. while (wlen > 4) {
  2455. /* FIXME: check for big-endian */
  2456. data = swab32(*(u32 *) wbuf);
  2457. wbuf += 4;
  2458. wlen -= 4;
  2459. ddbwritel(dev, data, tag | SPI_DATA);
  2460. if (reg_wait(dev, tag | SPI_CONTROL, 4))
  2461. goto fail;
  2462. }
  2463. if (rlen)
  2464. ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00),
  2465. tag | SPI_CONTROL);
  2466. else
  2467. ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00),
  2468. tag | SPI_CONTROL);
  2469. data = 0;
  2470. shift = ((4 - wlen) * 8);
  2471. while (wlen) {
  2472. data <<= 8;
  2473. data |= *wbuf;
  2474. wlen--;
  2475. wbuf++;
  2476. }
  2477. if (shift)
  2478. data <<= shift;
  2479. ddbwritel(dev, data, tag | SPI_DATA);
  2480. if (reg_wait(dev, tag | SPI_CONTROL, 4))
  2481. goto fail;
  2482. if (!rlen) {
  2483. ddbwritel(dev, 0, tag | SPI_CONTROL);
  2484. goto exit;
  2485. }
  2486. if (rlen > 4)
  2487. ddbwritel(dev, 1, tag | SPI_CONTROL);
  2488. while (rlen > 4) {
  2489. ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
  2490. if (reg_wait(dev, tag | SPI_CONTROL, 4))
  2491. goto fail;
  2492. data = ddbreadl(dev, tag | SPI_DATA);
  2493. *(u32 *) rbuf = swab32(data);
  2494. rbuf += 4;
  2495. rlen -= 4;
  2496. }
  2497. ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00),
  2498. tag | SPI_CONTROL);
  2499. ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
  2500. if (reg_wait(dev, tag | SPI_CONTROL, 4))
  2501. goto fail;
  2502. data = ddbreadl(dev, tag | SPI_DATA);
  2503. ddbwritel(dev, 0, tag | SPI_CONTROL);
  2504. if (rlen < 4)
  2505. data <<= ((4 - rlen) * 8);
  2506. while (rlen > 0) {
  2507. *rbuf = ((data >> 24) & 0xff);
  2508. data <<= 8;
  2509. rbuf++;
  2510. rlen--;
  2511. }
  2512. exit:
  2513. mutex_unlock(&link->flash_mutex);
  2514. return 0;
  2515. fail:
  2516. mutex_unlock(&link->flash_mutex);
  2517. return -1;
  2518. }
  2519. int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len)
  2520. {
  2521. u8 cmd[4] = {0x03, (addr >> 16) & 0xff,
  2522. (addr >> 8) & 0xff, addr & 0xff};
  2523. return flashio(dev, link, cmd, 4, buf, len);
  2524. }
  2525. /*
  2526. * TODO/FIXME: add/implement IOCTLs from upstream driver
  2527. */
  2528. #define DDB_NAME "ddbridge"
  2529. static u32 ddb_num;
  2530. static int ddb_major;
  2531. static DEFINE_MUTEX(ddb_mutex);
  2532. static int ddb_release(struct inode *inode, struct file *file)
  2533. {
  2534. struct ddb *dev = file->private_data;
  2535. dev->ddb_dev_users--;
  2536. return 0;
  2537. }
  2538. static int ddb_open(struct inode *inode, struct file *file)
  2539. {
  2540. struct ddb *dev = ddbs[iminor(inode)];
  2541. if (dev->ddb_dev_users)
  2542. return -EBUSY;
  2543. dev->ddb_dev_users++;
  2544. file->private_data = dev;
  2545. return 0;
  2546. }
  2547. static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  2548. {
  2549. struct ddb *dev = file->private_data;
  2550. dev_warn(dev->dev, "DDB IOCTLs unsupported (cmd: %d, arg: %lu)\n",
  2551. cmd, arg);
  2552. return -ENOTTY;
  2553. }
  2554. static const struct file_operations ddb_fops = {
  2555. .unlocked_ioctl = ddb_ioctl,
  2556. .open = ddb_open,
  2557. .release = ddb_release,
  2558. };
  2559. static char *ddb_devnode(struct device *device, umode_t *mode)
  2560. {
  2561. struct ddb *dev = dev_get_drvdata(device);
  2562. return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
  2563. }
  2564. #define __ATTR_MRO(_name, _show) { \
  2565. .attr = { .name = __stringify(_name), .mode = 0444 }, \
  2566. .show = _show, \
  2567. }
  2568. #define __ATTR_MWO(_name, _store) { \
  2569. .attr = { .name = __stringify(_name), .mode = 0222 }, \
  2570. .store = _store, \
  2571. }
  2572. static ssize_t ports_show(struct device *device,
  2573. struct device_attribute *attr, char *buf)
  2574. {
  2575. struct ddb *dev = dev_get_drvdata(device);
  2576. return sprintf(buf, "%d\n", dev->port_num);
  2577. }
  2578. static ssize_t ts_irq_show(struct device *device,
  2579. struct device_attribute *attr, char *buf)
  2580. {
  2581. struct ddb *dev = dev_get_drvdata(device);
  2582. return sprintf(buf, "%d\n", dev->ts_irq);
  2583. }
  2584. static ssize_t i2c_irq_show(struct device *device,
  2585. struct device_attribute *attr, char *buf)
  2586. {
  2587. struct ddb *dev = dev_get_drvdata(device);
  2588. return sprintf(buf, "%d\n", dev->i2c_irq);
  2589. }
  2590. static ssize_t fan_show(struct device *device,
  2591. struct device_attribute *attr, char *buf)
  2592. {
  2593. struct ddb *dev = dev_get_drvdata(device);
  2594. u32 val;
  2595. val = ddbreadl(dev, GPIO_OUTPUT) & 1;
  2596. return sprintf(buf, "%d\n", val);
  2597. }
  2598. static ssize_t fan_store(struct device *device, struct device_attribute *d,
  2599. const char *buf, size_t count)
  2600. {
  2601. struct ddb *dev = dev_get_drvdata(device);
  2602. u32 val;
  2603. if (sscanf(buf, "%u\n", &val) != 1)
  2604. return -EINVAL;
  2605. ddbwritel(dev, 1, GPIO_DIRECTION);
  2606. ddbwritel(dev, val & 1, GPIO_OUTPUT);
  2607. return count;
  2608. }
  2609. static ssize_t fanspeed_show(struct device *device,
  2610. struct device_attribute *attr, char *buf)
  2611. {
  2612. struct ddb *dev = dev_get_drvdata(device);
  2613. int num = attr->attr.name[8] - 0x30;
  2614. struct ddb_link *link = &dev->link[num];
  2615. u32 spd;
  2616. spd = ddblreadl(link, TEMPMON_FANCONTROL) & 0xff;
  2617. return sprintf(buf, "%u\n", spd * 100);
  2618. }
  2619. static ssize_t temp_show(struct device *device,
  2620. struct device_attribute *attr, char *buf)
  2621. {
  2622. struct ddb *dev = dev_get_drvdata(device);
  2623. struct ddb_link *link = &dev->link[0];
  2624. struct i2c_adapter *adap;
  2625. int temp, temp2;
  2626. u8 tmp[2];
  2627. if (!link->info->temp_num)
  2628. return sprintf(buf, "no sensor\n");
  2629. adap = &dev->i2c[link->info->temp_bus].adap;
  2630. if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0)
  2631. return sprintf(buf, "read_error\n");
  2632. temp = (tmp[0] << 3) | (tmp[1] >> 5);
  2633. temp *= 125;
  2634. if (link->info->temp_num == 2) {
  2635. if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0)
  2636. return sprintf(buf, "read_error\n");
  2637. temp2 = (tmp[0] << 3) | (tmp[1] >> 5);
  2638. temp2 *= 125;
  2639. return sprintf(buf, "%d %d\n", temp, temp2);
  2640. }
  2641. return sprintf(buf, "%d\n", temp);
  2642. }
  2643. static ssize_t ctemp_show(struct device *device,
  2644. struct device_attribute *attr, char *buf)
  2645. {
  2646. struct ddb *dev = dev_get_drvdata(device);
  2647. struct i2c_adapter *adap;
  2648. int temp;
  2649. u8 tmp[2];
  2650. int num = attr->attr.name[4] - 0x30;
  2651. adap = &dev->i2c[num].adap;
  2652. if (!adap)
  2653. return 0;
  2654. if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0)
  2655. if (i2c_read_regs(adap, 0x4d, 0, tmp, 2) < 0)
  2656. return sprintf(buf, "no sensor\n");
  2657. temp = tmp[0] * 1000;
  2658. return sprintf(buf, "%d\n", temp);
  2659. }
  2660. static ssize_t led_show(struct device *device,
  2661. struct device_attribute *attr, char *buf)
  2662. {
  2663. struct ddb *dev = dev_get_drvdata(device);
  2664. int num = attr->attr.name[3] - 0x30;
  2665. return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0);
  2666. }
  2667. static void ddb_set_led(struct ddb *dev, int num, int val)
  2668. {
  2669. if (!dev->link[0].info->led_num)
  2670. return;
  2671. switch (dev->port[num].class) {
  2672. case DDB_PORT_TUNER:
  2673. switch (dev->port[num].type) {
  2674. case DDB_TUNER_DVBS_ST:
  2675. i2c_write_reg16(&dev->i2c[num].adap,
  2676. 0x69, 0xf14c, val ? 2 : 0);
  2677. break;
  2678. case DDB_TUNER_DVBCT_ST:
  2679. i2c_write_reg16(&dev->i2c[num].adap,
  2680. 0x1f, 0xf00e, 0);
  2681. i2c_write_reg16(&dev->i2c[num].adap,
  2682. 0x1f, 0xf00f, val ? 1 : 0);
  2683. break;
  2684. case DDB_TUNER_XO2 ... DDB_TUNER_DVBC2T2I_SONY:
  2685. {
  2686. u8 v;
  2687. i2c_read_reg(&dev->i2c[num].adap, 0x10, 0x08, &v);
  2688. v = (v & ~0x10) | (val ? 0x10 : 0);
  2689. i2c_write_reg(&dev->i2c[num].adap, 0x10, 0x08, v);
  2690. break;
  2691. }
  2692. default:
  2693. break;
  2694. }
  2695. break;
  2696. }
  2697. }
  2698. static ssize_t led_store(struct device *device,
  2699. struct device_attribute *attr,
  2700. const char *buf, size_t count)
  2701. {
  2702. struct ddb *dev = dev_get_drvdata(device);
  2703. int num = attr->attr.name[3] - 0x30;
  2704. u32 val;
  2705. if (sscanf(buf, "%u\n", &val) != 1)
  2706. return -EINVAL;
  2707. if (val)
  2708. dev->leds |= (1 << num);
  2709. else
  2710. dev->leds &= ~(1 << num);
  2711. ddb_set_led(dev, num, val);
  2712. return count;
  2713. }
  2714. static ssize_t snr_show(struct device *device,
  2715. struct device_attribute *attr, char *buf)
  2716. {
  2717. struct ddb *dev = dev_get_drvdata(device);
  2718. char snr[32];
  2719. int num = attr->attr.name[3] - 0x30;
  2720. if (dev->port[num].type >= DDB_TUNER_XO2) {
  2721. if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0)
  2722. return sprintf(buf, "NO SNR\n");
  2723. snr[16] = 0;
  2724. } else {
  2725. /* serial number at 0x100-0x11f */
  2726. if (i2c_read_regs16(&dev->i2c[num].adap,
  2727. 0x57, 0x100, snr, 32) < 0)
  2728. if (i2c_read_regs16(&dev->i2c[num].adap,
  2729. 0x50, 0x100, snr, 32) < 0)
  2730. return sprintf(buf, "NO SNR\n");
  2731. snr[31] = 0; /* in case it is not terminated on EEPROM */
  2732. }
  2733. return sprintf(buf, "%s\n", snr);
  2734. }
  2735. static ssize_t bsnr_show(struct device *device,
  2736. struct device_attribute *attr, char *buf)
  2737. {
  2738. struct ddb *dev = dev_get_drvdata(device);
  2739. char snr[16];
  2740. ddbridge_flashread(dev, 0, snr, 0x10, 15);
  2741. snr[15] = 0; /* in case it is not terminated on EEPROM */
  2742. return sprintf(buf, "%s\n", snr);
  2743. }
  2744. static ssize_t bpsnr_show(struct device *device,
  2745. struct device_attribute *attr, char *buf)
  2746. {
  2747. struct ddb *dev = dev_get_drvdata(device);
  2748. unsigned char snr[32];
  2749. if (!dev->i2c_num)
  2750. return 0;
  2751. if (i2c_read_regs16(&dev->i2c[0].adap,
  2752. 0x50, 0x0000, snr, 32) < 0 ||
  2753. snr[0] == 0xff)
  2754. return sprintf(buf, "NO SNR\n");
  2755. snr[31] = 0; /* in case it is not terminated on EEPROM */
  2756. return sprintf(buf, "%s\n", snr);
  2757. }
  2758. static ssize_t redirect_show(struct device *device,
  2759. struct device_attribute *attr, char *buf)
  2760. {
  2761. return 0;
  2762. }
  2763. static ssize_t redirect_store(struct device *device,
  2764. struct device_attribute *attr,
  2765. const char *buf, size_t count)
  2766. {
  2767. unsigned int i, p;
  2768. int res;
  2769. if (sscanf(buf, "%x %x\n", &i, &p) != 2)
  2770. return -EINVAL;
  2771. res = ddb_redirect(i, p);
  2772. if (res < 0)
  2773. return res;
  2774. dev_info(device, "redirect: %02x, %02x\n", i, p);
  2775. return count;
  2776. }
  2777. static ssize_t gap_show(struct device *device,
  2778. struct device_attribute *attr, char *buf)
  2779. {
  2780. struct ddb *dev = dev_get_drvdata(device);
  2781. int num = attr->attr.name[3] - 0x30;
  2782. return sprintf(buf, "%d\n", dev->port[num].gap);
  2783. }
  2784. static ssize_t gap_store(struct device *device, struct device_attribute *attr,
  2785. const char *buf, size_t count)
  2786. {
  2787. struct ddb *dev = dev_get_drvdata(device);
  2788. int num = attr->attr.name[3] - 0x30;
  2789. unsigned int val;
  2790. if (sscanf(buf, "%u\n", &val) != 1)
  2791. return -EINVAL;
  2792. if (val > 128)
  2793. return -EINVAL;
  2794. if (val == 128)
  2795. val = 0xffffffff;
  2796. dev->port[num].gap = val;
  2797. return count;
  2798. }
  2799. static ssize_t version_show(struct device *device,
  2800. struct device_attribute *attr, char *buf)
  2801. {
  2802. struct ddb *dev = dev_get_drvdata(device);
  2803. return sprintf(buf, "%08x %08x\n",
  2804. dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
  2805. }
  2806. static ssize_t hwid_show(struct device *device,
  2807. struct device_attribute *attr, char *buf)
  2808. {
  2809. struct ddb *dev = dev_get_drvdata(device);
  2810. return sprintf(buf, "0x%08X\n", dev->link[0].ids.hwid);
  2811. }
  2812. static ssize_t regmap_show(struct device *device,
  2813. struct device_attribute *attr, char *buf)
  2814. {
  2815. struct ddb *dev = dev_get_drvdata(device);
  2816. return sprintf(buf, "0x%08X\n", dev->link[0].ids.regmapid);
  2817. }
  2818. static ssize_t fmode_show(struct device *device,
  2819. struct device_attribute *attr, char *buf)
  2820. {
  2821. int num = attr->attr.name[5] - 0x30;
  2822. struct ddb *dev = dev_get_drvdata(device);
  2823. return sprintf(buf, "%u\n", dev->link[num].lnb.fmode);
  2824. }
  2825. static ssize_t devid_show(struct device *device,
  2826. struct device_attribute *attr, char *buf)
  2827. {
  2828. int num = attr->attr.name[5] - 0x30;
  2829. struct ddb *dev = dev_get_drvdata(device);
  2830. return sprintf(buf, "%08x\n", dev->link[num].ids.devid);
  2831. }
  2832. static ssize_t fmode_store(struct device *device, struct device_attribute *attr,
  2833. const char *buf, size_t count)
  2834. {
  2835. struct ddb *dev = dev_get_drvdata(device);
  2836. int num = attr->attr.name[5] - 0x30;
  2837. unsigned int val;
  2838. if (sscanf(buf, "%u\n", &val) != 1)
  2839. return -EINVAL;
  2840. if (val > 3)
  2841. return -EINVAL;
  2842. lnb_init_fmode(dev, &dev->link[num], val);
  2843. return count;
  2844. }
  2845. static struct device_attribute ddb_attrs[] = {
  2846. __ATTR_RO(version),
  2847. __ATTR_RO(ports),
  2848. __ATTR_RO(ts_irq),
  2849. __ATTR_RO(i2c_irq),
  2850. __ATTR(gap0, 0664, gap_show, gap_store),
  2851. __ATTR(gap1, 0664, gap_show, gap_store),
  2852. __ATTR(gap2, 0664, gap_show, gap_store),
  2853. __ATTR(gap3, 0664, gap_show, gap_store),
  2854. __ATTR(fmode0, 0664, fmode_show, fmode_store),
  2855. __ATTR(fmode1, 0664, fmode_show, fmode_store),
  2856. __ATTR(fmode2, 0664, fmode_show, fmode_store),
  2857. __ATTR(fmode3, 0664, fmode_show, fmode_store),
  2858. __ATTR_MRO(devid0, devid_show),
  2859. __ATTR_MRO(devid1, devid_show),
  2860. __ATTR_MRO(devid2, devid_show),
  2861. __ATTR_MRO(devid3, devid_show),
  2862. __ATTR_RO(hwid),
  2863. __ATTR_RO(regmap),
  2864. __ATTR(redirect, 0664, redirect_show, redirect_store),
  2865. __ATTR_MRO(snr, bsnr_show),
  2866. __ATTR_RO(bpsnr),
  2867. __ATTR_NULL,
  2868. };
  2869. static struct device_attribute ddb_attrs_temp[] = {
  2870. __ATTR_RO(temp),
  2871. };
  2872. static struct device_attribute ddb_attrs_fan[] = {
  2873. __ATTR(fan, 0664, fan_show, fan_store),
  2874. };
  2875. static struct device_attribute ddb_attrs_snr[] = {
  2876. __ATTR_MRO(snr0, snr_show),
  2877. __ATTR_MRO(snr1, snr_show),
  2878. __ATTR_MRO(snr2, snr_show),
  2879. __ATTR_MRO(snr3, snr_show),
  2880. };
  2881. static struct device_attribute ddb_attrs_ctemp[] = {
  2882. __ATTR_MRO(temp0, ctemp_show),
  2883. __ATTR_MRO(temp1, ctemp_show),
  2884. __ATTR_MRO(temp2, ctemp_show),
  2885. __ATTR_MRO(temp3, ctemp_show),
  2886. };
  2887. static struct device_attribute ddb_attrs_led[] = {
  2888. __ATTR(led0, 0664, led_show, led_store),
  2889. __ATTR(led1, 0664, led_show, led_store),
  2890. __ATTR(led2, 0664, led_show, led_store),
  2891. __ATTR(led3, 0664, led_show, led_store),
  2892. };
  2893. static struct device_attribute ddb_attrs_fanspeed[] = {
  2894. __ATTR_MRO(fanspeed0, fanspeed_show),
  2895. __ATTR_MRO(fanspeed1, fanspeed_show),
  2896. __ATTR_MRO(fanspeed2, fanspeed_show),
  2897. __ATTR_MRO(fanspeed3, fanspeed_show),
  2898. };
  2899. static struct class ddb_class = {
  2900. .name = "ddbridge",
  2901. .owner = THIS_MODULE,
  2902. .devnode = ddb_devnode,
  2903. };
  2904. int ddb_class_create(void)
  2905. {
  2906. ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
  2907. if (ddb_major < 0)
  2908. return ddb_major;
  2909. if (class_register(&ddb_class) < 0)
  2910. return -1;
  2911. return 0;
  2912. }
  2913. void ddb_class_destroy(void)
  2914. {
  2915. class_unregister(&ddb_class);
  2916. unregister_chrdev(ddb_major, DDB_NAME);
  2917. }
  2918. static void ddb_device_attrs_del(struct ddb *dev)
  2919. {
  2920. int i;
  2921. for (i = 0; i < 4; i++)
  2922. if (dev->link[i].info && dev->link[i].info->tempmon_irq)
  2923. device_remove_file(dev->ddb_dev,
  2924. &ddb_attrs_fanspeed[i]);
  2925. for (i = 0; i < dev->link[0].info->temp_num; i++)
  2926. device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
  2927. for (i = 0; i < dev->link[0].info->fan_num; i++)
  2928. device_remove_file(dev->ddb_dev, &ddb_attrs_fan[i]);
  2929. for (i = 0; i < dev->i2c_num && i < 4; i++) {
  2930. if (dev->link[0].info->led_num)
  2931. device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]);
  2932. device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]);
  2933. device_remove_file(dev->ddb_dev, &ddb_attrs_ctemp[i]);
  2934. }
  2935. for (i = 0; ddb_attrs[i].attr.name != NULL; i++)
  2936. device_remove_file(dev->ddb_dev, &ddb_attrs[i]);
  2937. }
  2938. static int ddb_device_attrs_add(struct ddb *dev)
  2939. {
  2940. int i;
  2941. for (i = 0; ddb_attrs[i].attr.name != NULL; i++)
  2942. if (device_create_file(dev->ddb_dev, &ddb_attrs[i]))
  2943. goto fail;
  2944. for (i = 0; i < dev->link[0].info->temp_num; i++)
  2945. if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i]))
  2946. goto fail;
  2947. for (i = 0; i < dev->link[0].info->fan_num; i++)
  2948. if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i]))
  2949. goto fail;
  2950. for (i = 0; (i < dev->i2c_num) && (i < 4); i++) {
  2951. if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i]))
  2952. goto fail;
  2953. if (device_create_file(dev->ddb_dev, &ddb_attrs_ctemp[i]))
  2954. goto fail;
  2955. if (dev->link[0].info->led_num)
  2956. if (device_create_file(dev->ddb_dev,
  2957. &ddb_attrs_led[i]))
  2958. goto fail;
  2959. }
  2960. for (i = 0; i < 4; i++)
  2961. if (dev->link[i].info && dev->link[i].info->tempmon_irq)
  2962. if (device_create_file(dev->ddb_dev,
  2963. &ddb_attrs_fanspeed[i]))
  2964. goto fail;
  2965. return 0;
  2966. fail:
  2967. return -1;
  2968. }
  2969. int ddb_device_create(struct ddb *dev)
  2970. {
  2971. int res = 0;
  2972. if (ddb_num == DDB_MAX_ADAPTER)
  2973. return -ENOMEM;
  2974. mutex_lock(&ddb_mutex);
  2975. dev->nr = ddb_num;
  2976. ddbs[dev->nr] = dev;
  2977. dev->ddb_dev = device_create(&ddb_class, dev->dev,
  2978. MKDEV(ddb_major, dev->nr),
  2979. dev, "ddbridge%d", dev->nr);
  2980. if (IS_ERR(dev->ddb_dev)) {
  2981. res = PTR_ERR(dev->ddb_dev);
  2982. dev_info(dev->dev, "Could not create ddbridge%d\n", dev->nr);
  2983. goto fail;
  2984. }
  2985. res = ddb_device_attrs_add(dev);
  2986. if (res) {
  2987. ddb_device_attrs_del(dev);
  2988. device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr));
  2989. ddbs[dev->nr] = 0;
  2990. dev->ddb_dev = ERR_PTR(-ENODEV);
  2991. } else
  2992. ddb_num++;
  2993. fail:
  2994. mutex_unlock(&ddb_mutex);
  2995. return res;
  2996. }
  2997. void ddb_device_destroy(struct ddb *dev)
  2998. {
  2999. if (IS_ERR(dev->ddb_dev))
  3000. return;
  3001. ddb_device_attrs_del(dev);
  3002. device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr));
  3003. }
  3004. /****************************************************************************/
  3005. /****************************************************************************/
  3006. /****************************************************************************/
  3007. static void tempmon_setfan(struct ddb_link *link)
  3008. {
  3009. u32 temp, temp2, pwm;
  3010. if ((ddblreadl(link, TEMPMON_CONTROL) &
  3011. TEMPMON_CONTROL_OVERTEMP) != 0) {
  3012. dev_info(link->dev->dev, "Over temperature condition\n");
  3013. link->overtemperature_error = 1;
  3014. }
  3015. temp = (ddblreadl(link, TEMPMON_SENSOR0) >> 8) & 0xFF;
  3016. if (temp & 0x80)
  3017. temp = 0;
  3018. temp2 = (ddblreadl(link, TEMPMON_SENSOR1) >> 8) & 0xFF;
  3019. if (temp2 & 0x80)
  3020. temp2 = 0;
  3021. if (temp2 > temp)
  3022. temp = temp2;
  3023. pwm = (ddblreadl(link, TEMPMON_FANCONTROL) >> 8) & 0x0F;
  3024. if (pwm > 10)
  3025. pwm = 10;
  3026. if (temp >= link->temp_tab[pwm]) {
  3027. while (pwm < 10 && temp >= link->temp_tab[pwm + 1])
  3028. pwm += 1;
  3029. } else {
  3030. while (pwm > 1 && temp < link->temp_tab[pwm - 2])
  3031. pwm -= 1;
  3032. }
  3033. ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
  3034. }
  3035. static void temp_handler(unsigned long data)
  3036. {
  3037. struct ddb_link *link = (struct ddb_link *) data;
  3038. spin_lock(&link->temp_lock);
  3039. tempmon_setfan(link);
  3040. spin_unlock(&link->temp_lock);
  3041. }
  3042. static int tempmon_init(struct ddb_link *link, int first_time)
  3043. {
  3044. struct ddb *dev = link->dev;
  3045. int status = 0;
  3046. u32 l = link->nr;
  3047. spin_lock_irq(&link->temp_lock);
  3048. if (first_time) {
  3049. static u8 temperature_table[11] = {
  3050. 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80 };
  3051. memcpy(link->temp_tab, temperature_table,
  3052. sizeof(temperature_table));
  3053. }
  3054. dev->handler[l][link->info->tempmon_irq] = temp_handler;
  3055. dev->handler_data[l][link->info->tempmon_irq] = (unsigned long) link;
  3056. ddblwritel(link, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
  3057. TEMPMON_CONTROL_INTENABLE),
  3058. TEMPMON_CONTROL);
  3059. ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
  3060. link->overtemperature_error =
  3061. ((ddblreadl(link, TEMPMON_CONTROL) &
  3062. TEMPMON_CONTROL_OVERTEMP) != 0);
  3063. if (link->overtemperature_error) {
  3064. dev_info(link->dev->dev, "Over temperature condition\n");
  3065. status = -1;
  3066. }
  3067. tempmon_setfan(link);
  3068. spin_unlock_irq(&link->temp_lock);
  3069. return status;
  3070. }
  3071. static int ddb_init_tempmon(struct ddb_link *link)
  3072. {
  3073. struct ddb_info *info = link->info;
  3074. if (!info->tempmon_irq)
  3075. return 0;
  3076. if (info->type == DDB_OCTOPUS_MAX_CT)
  3077. if (link->ids.regmapid < 0x00010002)
  3078. return 0;
  3079. spin_lock_init(&link->temp_lock);
  3080. dev_dbg(link->dev->dev, "init_tempmon\n");
  3081. return tempmon_init(link, 1);
  3082. }
  3083. /****************************************************************************/
  3084. /****************************************************************************/
  3085. /****************************************************************************/
  3086. static int ddb_init_boards(struct ddb *dev)
  3087. {
  3088. struct ddb_info *info;
  3089. struct ddb_link *link;
  3090. u32 l;
  3091. for (l = 0; l < DDB_MAX_LINK; l++) {
  3092. link = &dev->link[l];
  3093. info = link->info;
  3094. if (!info)
  3095. continue;
  3096. if (info->board_control) {
  3097. ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
  3098. msleep(100);
  3099. ddbwritel(dev, info->board_control_2,
  3100. DDB_LINK_TAG(l) | BOARD_CONTROL);
  3101. usleep_range(2000, 3000);
  3102. ddbwritel(dev,
  3103. info->board_control_2 | info->board_control,
  3104. DDB_LINK_TAG(l) | BOARD_CONTROL);
  3105. usleep_range(2000, 3000);
  3106. }
  3107. ddb_init_tempmon(link);
  3108. }
  3109. return 0;
  3110. }
  3111. int ddb_init(struct ddb *dev)
  3112. {
  3113. mutex_init(&dev->link[0].lnb.lock);
  3114. mutex_init(&dev->link[0].flash_mutex);
  3115. if (no_init) {
  3116. ddb_device_create(dev);
  3117. return 0;
  3118. }
  3119. ddb_init_boards(dev);
  3120. if (ddb_i2c_init(dev) < 0)
  3121. goto fail;
  3122. ddb_ports_init(dev);
  3123. if (ddb_buffers_alloc(dev) < 0) {
  3124. dev_info(dev->dev, "Could not allocate buffer memory\n");
  3125. goto fail2;
  3126. }
  3127. if (ddb_ports_attach(dev) < 0)
  3128. goto fail3;
  3129. ddb_device_create(dev);
  3130. if (dev->link[0].info->fan_num) {
  3131. ddbwritel(dev, 1, GPIO_DIRECTION);
  3132. ddbwritel(dev, 1, GPIO_OUTPUT);
  3133. }
  3134. return 0;
  3135. fail3:
  3136. ddb_ports_detach(dev);
  3137. dev_err(dev->dev, "fail3\n");
  3138. ddb_ports_release(dev);
  3139. fail2:
  3140. dev_err(dev->dev, "fail2\n");
  3141. ddb_buffers_free(dev);
  3142. ddb_i2c_release(dev);
  3143. fail:
  3144. dev_err(dev->dev, "fail1\n");
  3145. return -1;
  3146. }