vdk_axc003_idu.dtsi 1.8 KB

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  1. /*
  2. * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /*
  9. * Device tree for AXC003 CPU card:
  10. * HS38x2 (Dual Core) with IDU intc (VDK version)
  11. */
  12. /include/ "skeleton_hs_idu.dtsi"
  13. / {
  14. compatible = "snps,arc";
  15. clock-frequency = <50000000>;
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. cpu_card {
  19. compatible = "simple-bus";
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. ranges = <0x00000000 0xf0000000 0x10000000>;
  23. core_clk: core_clk {
  24. #clock-cells = <0>;
  25. compatible = "fixed-clock";
  26. clock-frequency = <50000000>;
  27. };
  28. core_intc: archs-intc@cpu {
  29. compatible = "snps,archs-intc";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. };
  33. idu_intc: idu-interrupt-controller {
  34. compatible = "snps,archs-idu-intc";
  35. interrupt-controller;
  36. interrupt-parent = <&core_intc>;
  37. /*
  38. * <hwirq distribution>
  39. * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  40. */
  41. #interrupt-cells = <2>;
  42. interrupts = <24 25 26 27>;
  43. };
  44. debug_uart: dw-apb-uart@0x5000 {
  45. compatible = "snps,dw-apb-uart";
  46. reg = <0x5000 0x100>;
  47. clock-frequency = <2403200>;
  48. interrupt-parent = <&idu_intc>;
  49. interrupts = <2 0>;
  50. baud = <115200>;
  51. reg-shift = <2>;
  52. reg-io-width = <4>;
  53. };
  54. };
  55. mb_intc: dw-apb-ictl@0xe0012000 {
  56. #interrupt-cells = <1>;
  57. compatible = "snps,dw-apb-ictl";
  58. reg = < 0xe0012000 0x200 >;
  59. interrupt-controller;
  60. interrupt-parent = <&idu_intc>;
  61. interrupts = < 0 0 >;
  62. };
  63. memory {
  64. #address-cells = <1>;
  65. #size-cells = <1>;
  66. ranges = <0x00000000 0x80000000 0x40000000>;
  67. device_type = "memory";
  68. reg = <0x80000000 0x20000000>; /* 512MiB */
  69. };
  70. };