am335x-pdu001.dts 14 KB

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  1. /*
  2. * pdu001.dts
  3. *
  4. * EETS GmbH PDU001 board device tree file
  5. *
  6. * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  7. *
  8. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. /dts-v1/;
  13. #include "am33xx.dtsi"
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/leds/leds-pca9532.h>
  16. / {
  17. model = "EETS,PDU001";
  18. compatible = "ti,am33xx";
  19. chosen {
  20. stdout-path = &uart3;
  21. };
  22. cpus {
  23. cpu@0 {
  24. cpu0-supply = <&vdd1_reg>;
  25. };
  26. };
  27. memory {
  28. device_type = "memory";
  29. reg = <0x80000000 0x10000000>; /* 256 MB */
  30. };
  31. vbat: fixedregulator@0 {
  32. compatible = "regulator-fixed";
  33. regulator-name = "vbat";
  34. regulator-min-microvolt = <3600000>;
  35. regulator-max-microvolt = <3600000>;
  36. regulator-boot-on;
  37. };
  38. lis3_reg: fixedregulator@1 {
  39. compatible = "regulator-fixed";
  40. regulator-name = "lis3_reg";
  41. regulator-boot-on;
  42. };
  43. panel {
  44. compatible = "ti,tilcdc,panel";
  45. status = "okay";
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&lcd_pins_s0>;
  48. panel-info {
  49. ac-bias = <255>;
  50. ac-bias-intrpt = <0>;
  51. dma-burst-sz = <16>;
  52. bpp = <16>;
  53. fdd = <0x80>;
  54. sync-edge = <0>;
  55. sync-ctrl = <1>;
  56. raster-order = <0>;
  57. fifo-th = <0>;
  58. };
  59. display-timings {
  60. 240x320p16 {
  61. clock-frequency = <6500000>;
  62. hactive = <240>;
  63. vactive = <320>;
  64. hfront-porch = <6>;
  65. hback-porch = <6>;
  66. hsync-len = <1>;
  67. vback-porch = <6>;
  68. vfront-porch = <6>;
  69. vsync-len = <1>;
  70. hsync-active = <0>;
  71. vsync-active = <0>;
  72. pixelclk-active = <1>;
  73. de-active = <0>;
  74. };
  75. };
  76. };
  77. };
  78. &am33xx_pinmux {
  79. pinctrl-names = "default";
  80. pinctrl-0 = <&clkout2_pin>;
  81. i2c0_pins: pinmux_i2c0_pins {
  82. pinctrl-single,pins = <
  83. AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  84. AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  85. >;
  86. };
  87. i2c1_pins: pinmux_i2c1_pins {
  88. pinctrl-single,pins = <
  89. AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  90. AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  91. >;
  92. };
  93. i2c2_pins: pinmux_i2c2_pins {
  94. pinctrl-single,pins = <
  95. AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */
  96. AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */
  97. >;
  98. };
  99. spi1_pins: pinmux_spi1_pins {
  100. pinctrl-single,pins = <
  101. AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
  102. AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
  103. AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
  104. AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
  105. >;
  106. };
  107. uart0_pins: pinmux_uart0_pins {
  108. pinctrl-single,pins = <
  109. AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
  110. AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  111. AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  112. >;
  113. };
  114. uart1_pins: pinmux_uart1_pins {
  115. pinctrl-single,pins = <
  116. AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
  117. AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
  118. >;
  119. };
  120. uart3_pins: pinmux_uart3_pins {
  121. pinctrl-single,pins = <
  122. AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */
  123. AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
  124. >;
  125. };
  126. clkout2_pin: pinmux_clkout2_pin {
  127. pinctrl-single,pins = <
  128. AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  129. >;
  130. };
  131. cpsw_default: cpsw_default {
  132. pinctrl-single,pins = <
  133. /* Port 1 (emac0) */
  134. AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */
  135. AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */
  136. AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */
  137. AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */
  138. AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
  139. AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
  140. AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
  141. AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
  142. AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
  143. AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */
  144. AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
  145. AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
  146. AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
  147. AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
  148. AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
  149. /* Port 2 (emac1) */
  150. AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */
  151. AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
  152. AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */
  153. AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */
  154. AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */
  155. AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */
  156. AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */
  157. AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
  158. AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
  159. AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
  160. AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
  161. AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
  162. AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */
  163. AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */
  164. AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */
  165. >;
  166. };
  167. davinci_mdio_default: davinci_mdio_default {
  168. pinctrl-single,pins = <
  169. AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  170. AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  171. >;
  172. };
  173. mmc1_pins: pinmux_mmc1_pins {
  174. /* eMMC */
  175. pinctrl-single,pins = <
  176. AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
  177. AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
  178. AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
  179. AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
  180. AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
  181. AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
  182. >;
  183. };
  184. mmc2_pins: pinmux_mmc2_pins {
  185. /* SD cardcage */
  186. pinctrl-single,pins = <
  187. AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
  188. AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
  189. AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
  190. AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
  191. AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
  192. AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
  193. /* card change signal for frontpanel SD cardcage */
  194. AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
  195. >;
  196. };
  197. lcd_pins_s0: lcd_pins_s0 {
  198. pinctrl-single,pins = <
  199. AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  200. AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  201. AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  202. AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  203. AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  204. AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  205. AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  206. AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  207. AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  208. AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  209. AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  210. AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  211. AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  212. AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  213. AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  214. AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  215. AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  216. AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  217. AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  218. AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  219. >;
  220. };
  221. dcan0_pins: pinmux_dcan0_pins {
  222. pinctrl-single,pins = <
  223. AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
  224. AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
  225. >;
  226. };
  227. };
  228. &uart0 {
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&uart0_pins>;
  231. rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  232. rs485-rts-active-high;
  233. rs485-rts-delay = <0 0>;
  234. linux,rs485-enabled-at-boot-time;
  235. status = "okay";
  236. };
  237. &uart1 {
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&uart1_pins>;
  240. status = "okay";
  241. };
  242. &uart3 {
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&uart3_pins>;
  245. status = "okay";
  246. };
  247. &i2c0 {
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&i2c0_pins>;
  250. status = "okay";
  251. clock-frequency = <400000>;
  252. tps: tps@2d {
  253. reg = <0x2d>;
  254. };
  255. m2_eeprom: m2_eeprom@50 {
  256. compatible = "atmel,24c256";
  257. reg = <0x50>;
  258. status = "okay";
  259. };
  260. };
  261. &i2c1 {
  262. pinctrl-names = "default";
  263. pinctrl-0 = <&i2c1_pins>;
  264. status = "okay";
  265. clock-frequency = <100000>;
  266. board_24aa025e48: board_24aa025e48@50 {
  267. compatible = "atmel,24c02";
  268. reg = <0x50>;
  269. };
  270. backplane_24aa025e48: backplane_24aa025e48@53 {
  271. compatible = "atmel,24c02";
  272. reg = <0x53>;
  273. };
  274. pca9532: pca9532@60 {
  275. compatible = "nxp,pca9532";
  276. reg = <0x60>;
  277. psc0 = <0x97>;
  278. pwm0 = <0x80>;
  279. psc1 = <0x97>;
  280. pwm1 = <0x10>;
  281. run.red@0 {
  282. type = <PCA9532_TYPE_LED>;
  283. };
  284. run.green@1 {
  285. type = <PCA9532_TYPE_LED>;
  286. default-state = "on";
  287. };
  288. s2.red@2 {
  289. type = <PCA9532_TYPE_LED>;
  290. };
  291. s2.green@3 {
  292. type = <PCA9532_TYPE_LED>;
  293. };
  294. s1.yellow@4 {
  295. type = <PCA9532_TYPE_LED>;
  296. };
  297. s1.green@5 {
  298. type = <PCA9532_TYPE_LED>;
  299. };
  300. };
  301. pca9530: pca9530@61 {
  302. compatible = "nxp,pca9530";
  303. reg = <0x61>;
  304. tft-panel@0 {
  305. type = <PCA9532_TYPE_LED>;
  306. linux,default-trigger = "backlight";
  307. default-state = "on";
  308. };
  309. };
  310. mcp79400: mcp79400@6f {
  311. compatible = "microchip,mcp7940x";
  312. reg = <0x6f>;
  313. };
  314. };
  315. &i2c2 {
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&i2c2_pins>;
  318. status = "okay";
  319. clock-frequency = <100000>;
  320. };
  321. &spi1 {
  322. pinctrl-names = "default";
  323. pinctrl-0 = <&spi1_pins>;
  324. ti,pindir-d0-out-d1-in;
  325. status = "okay";
  326. cfaf240320a032t {
  327. compatible = "orisetech,otm3225a";
  328. reg = <0>;
  329. spi-max-frequency = <1000000>;
  330. // SPI mode 3
  331. spi-cpol;
  332. spi-cpha;
  333. status = "okay";
  334. };
  335. };
  336. &usb {
  337. status = "okay";
  338. };
  339. &usb_ctrl_mod {
  340. status = "okay";
  341. };
  342. &usb0_phy {
  343. status = "okay";
  344. };
  345. &usb1_phy {
  346. status = "okay";
  347. };
  348. &usb0 {
  349. status = "okay";
  350. };
  351. &usb1 {
  352. status = "okay";
  353. };
  354. &cppi41dma {
  355. status = "okay";
  356. };
  357. /*
  358. * Disable soc's rtc as we have no VBAT for it. This makes the board
  359. * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
  360. */
  361. &rtc {
  362. status = "disabled";
  363. };
  364. &lcdc {
  365. status = "okay";
  366. };
  367. &elm {
  368. status = "okay";
  369. };
  370. #include "tps65910.dtsi"
  371. &tps {
  372. vcc1-supply = <&vbat>;
  373. vcc2-supply = <&vbat>;
  374. vcc3-supply = <&vbat>;
  375. vcc4-supply = <&vbat>;
  376. vcc5-supply = <&vbat>;
  377. vcc6-supply = <&vbat>;
  378. vcc7-supply = <&vbat>;
  379. vccio-supply = <&vbat>;
  380. regulators {
  381. vrtc_reg: regulator@0 {
  382. regulator-name = "ldo_vrtc";
  383. regulator-always-on;
  384. };
  385. vio_reg: regulator@1 {
  386. regulator-name = "buck_vdd_ddr";
  387. regulator-always-on;
  388. };
  389. vdd1_reg: regulator@2 {
  390. /* VDD_MPU voltage limits */
  391. regulator-name = "buck_vdd_mpu";
  392. regulator-min-microvolt = <912500>;
  393. regulator-max-microvolt = <1312500>;
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. vdd2_reg: regulator@3 {
  398. /* VDD_CORE voltage limits */
  399. regulator-name = "buck_vdd_core";
  400. regulator-min-microvolt = <912500>;
  401. regulator-max-microvolt = <1150000>;
  402. regulator-boot-on;
  403. regulator-always-on;
  404. };
  405. vdd3_reg: regulator@4 {
  406. regulator-name = "boost_res";
  407. regulator-always-on;
  408. };
  409. vdig1_reg: regulator@5 {
  410. regulator-name = "ldo_vdig1";
  411. regulator-always-on;
  412. };
  413. vdig2_reg: regulator@6 {
  414. regulator-name = "ldo_vdig2";
  415. regulator-always-on;
  416. };
  417. vpll_reg: regulator@7 {
  418. regulator-name = "ldo_vpll";
  419. regulator-always-on;
  420. };
  421. vdac_reg: regulator@8 {
  422. regulator-name = "ldo_vdac";
  423. regulator-always-on;
  424. };
  425. vaux1_reg: regulator@9 {
  426. regulator-name = "ldo_vaux1";
  427. regulator-always-on;
  428. };
  429. vaux2_reg: regulator@10 {
  430. regulator-name = "ldo_vaux2";
  431. regulator-always-on;
  432. };
  433. vaux33_reg: regulator@11 {
  434. regulator-name = "ldo_vaux33";
  435. regulator-always-on;
  436. };
  437. vmmc_reg: regulator@12 {
  438. regulator-name = "ldo_vmmc";
  439. regulator-min-microvolt = <1800000>;
  440. regulator-max-microvolt = <3300000>;
  441. regulator-always-on;
  442. };
  443. vbb_reg: regulator@13 {
  444. regulator-name = "bat_vbb";
  445. };
  446. };
  447. };
  448. &mac {
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&cpsw_default>;
  451. dual_emac; /* no switch, two distinct MACs */
  452. status = "okay";
  453. };
  454. &davinci_mdio {
  455. pinctrl-names = "default";
  456. pinctrl-0 = <&davinci_mdio_default>;
  457. status = "okay";
  458. };
  459. &cpsw_emac0 {
  460. phy_id = <&davinci_mdio>, <0>;
  461. phy-mode = "mii";
  462. dual_emac_res_vlan = <1>;
  463. };
  464. &cpsw_emac1 {
  465. phy_id = <&davinci_mdio>, <1>;
  466. phy-mode = "mii";
  467. dual_emac_res_vlan = <2>;
  468. };
  469. &tscadc {
  470. status = "okay";
  471. tsc {
  472. ti,wires = <4>;
  473. ti,x-plate-resistance = <200>;
  474. ti,coordinate-readouts = <5>;
  475. ti,wire-config = <0x01 0x10 0x22 0x33>;
  476. ti,charge-delay = <0x400>;
  477. };
  478. adc {
  479. ti,adc-channels = <4 5 6 7>;
  480. };
  481. };
  482. &mmc1 {
  483. status = "okay";
  484. vmmc-supply = <&vmmc_reg>;
  485. bus-width = <4>;
  486. pinctrl-names = "default";
  487. pinctrl-0 = <&mmc1_pins>;
  488. non-removable;
  489. };
  490. &mmc2 {
  491. status = "okay";
  492. vmmc-supply = <&vmmc_reg>;
  493. bus-width = <4>;
  494. pinctrl-names = "default";
  495. pinctrl-0 = <&mmc2_pins>;
  496. cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  497. };
  498. &sham {
  499. status = "okay";
  500. };
  501. &aes {
  502. status = "okay";
  503. };
  504. &dcan0 {
  505. status = "okay";
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&dcan0_pins>;
  508. };