halbtc8192e2ant.c 119 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. /**************************************************************
  26. * Description:
  27. *
  28. * This file is for RTL8192E Co-exist mechanism
  29. *
  30. * History
  31. * 2012/11/15 Cosa first check in.
  32. *
  33. **************************************************************/
  34. /**************************************************************
  35. * include files
  36. **************************************************************/
  37. #include "halbt_precomp.h"
  38. /**************************************************************
  39. * Global variables, these are static variables
  40. **************************************************************/
  41. static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
  42. static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
  43. static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
  44. static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
  45. static const char *const GLBtInfoSrc8192e2Ant[] = {
  46. "BT Info[wifi fw]",
  47. "BT Info[bt rsp]",
  48. "BT Info[bt auto report]",
  49. };
  50. static u32 glcoex_ver_date_8192e_2ant = 20130902;
  51. static u32 glcoex_ver_8192e_2ant = 0x34;
  52. /**************************************************************
  53. * local function proto type if needed
  54. **************************************************************/
  55. /**************************************************************
  56. * local function start with halbtc8192e2ant_
  57. **************************************************************/
  58. static u8 halbtc8192e2ant_btrssi_state(u8 level_num, u8 rssi_thresh,
  59. u8 rssi_thresh1)
  60. {
  61. int btrssi = 0;
  62. u8 btrssi_state = coex_sta->pre_bt_rssi_state;
  63. btrssi = coex_sta->bt_rssi;
  64. if (level_num == 2) {
  65. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  66. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  67. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  68. "BT Rssi pre state = LOW\n");
  69. if (btrssi >= (rssi_thresh +
  70. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  71. btrssi_state = BTC_RSSI_STATE_HIGH;
  72. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  73. "BT Rssi state switch to High\n");
  74. } else {
  75. btrssi_state = BTC_RSSI_STATE_STAY_LOW;
  76. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  77. "BT Rssi state stay at Low\n");
  78. }
  79. } else {
  80. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  81. "BT Rssi pre state = HIGH\n");
  82. if (btrssi < rssi_thresh) {
  83. btrssi_state = BTC_RSSI_STATE_LOW;
  84. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  85. "BT Rssi state switch to Low\n");
  86. } else {
  87. btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
  88. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  89. "BT Rssi state stay at High\n");
  90. }
  91. }
  92. } else if (level_num == 3) {
  93. if (rssi_thresh > rssi_thresh1) {
  94. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  95. "BT Rssi thresh error!!\n");
  96. return coex_sta->pre_bt_rssi_state;
  97. }
  98. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  99. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  100. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  101. "BT Rssi pre state = LOW\n");
  102. if (btrssi >= (rssi_thresh +
  103. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  104. btrssi_state = BTC_RSSI_STATE_MEDIUM;
  105. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  106. "BT Rssi state switch to Medium\n");
  107. } else {
  108. btrssi_state = BTC_RSSI_STATE_STAY_LOW;
  109. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  110. "BT Rssi state stay at Low\n");
  111. }
  112. } else if ((coex_sta->pre_bt_rssi_state ==
  113. BTC_RSSI_STATE_MEDIUM) ||
  114. (coex_sta->pre_bt_rssi_state ==
  115. BTC_RSSI_STATE_STAY_MEDIUM)) {
  116. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  117. "[BTCoex], BT Rssi pre state = MEDIUM\n");
  118. if (btrssi >= (rssi_thresh1 +
  119. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  120. btrssi_state = BTC_RSSI_STATE_HIGH;
  121. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  122. "BT Rssi state switch to High\n");
  123. } else if (btrssi < rssi_thresh) {
  124. btrssi_state = BTC_RSSI_STATE_LOW;
  125. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  126. "BT Rssi state switch to Low\n");
  127. } else {
  128. btrssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  129. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  130. "BT Rssi state stay at Medium\n");
  131. }
  132. } else {
  133. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  134. "BT Rssi pre state = HIGH\n");
  135. if (btrssi < rssi_thresh1) {
  136. btrssi_state = BTC_RSSI_STATE_MEDIUM;
  137. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  138. "BT Rssi state switch to Medium\n");
  139. } else {
  140. btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
  141. btc_alg_dbg(ALGO_BT_RSSI_STATE,
  142. "BT Rssi state stay at High\n");
  143. }
  144. }
  145. }
  146. coex_sta->pre_bt_rssi_state = btrssi_state;
  147. return btrssi_state;
  148. }
  149. static u8 halbtc8192e2ant_wifirssi_state(struct btc_coexist *btcoexist,
  150. u8 index, u8 level_num, u8 rssi_thresh,
  151. u8 rssi_thresh1)
  152. {
  153. int wifirssi = 0;
  154. u8 wifirssi_state = coex_sta->pre_wifi_rssi_state[index];
  155. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
  156. if (level_num == 2) {
  157. if ((coex_sta->pre_wifi_rssi_state[index] ==
  158. BTC_RSSI_STATE_LOW) ||
  159. (coex_sta->pre_wifi_rssi_state[index] ==
  160. BTC_RSSI_STATE_STAY_LOW)) {
  161. if (wifirssi >= (rssi_thresh +
  162. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  163. wifirssi_state = BTC_RSSI_STATE_HIGH;
  164. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  165. "wifi RSSI state switch to High\n");
  166. } else {
  167. wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
  168. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  169. "wifi RSSI state stay at Low\n");
  170. }
  171. } else {
  172. if (wifirssi < rssi_thresh) {
  173. wifirssi_state = BTC_RSSI_STATE_LOW;
  174. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  175. "wifi RSSI state switch to Low\n");
  176. } else {
  177. wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
  178. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  179. "wifi RSSI state stay at High\n");
  180. }
  181. }
  182. } else if (level_num == 3) {
  183. if (rssi_thresh > rssi_thresh1) {
  184. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  185. "wifi RSSI thresh error!!\n");
  186. return coex_sta->pre_wifi_rssi_state[index];
  187. }
  188. if ((coex_sta->pre_wifi_rssi_state[index] ==
  189. BTC_RSSI_STATE_LOW) ||
  190. (coex_sta->pre_wifi_rssi_state[index] ==
  191. BTC_RSSI_STATE_STAY_LOW)) {
  192. if (wifirssi >= (rssi_thresh +
  193. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  194. wifirssi_state = BTC_RSSI_STATE_MEDIUM;
  195. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  196. "wifi RSSI state switch to Medium\n");
  197. } else {
  198. wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
  199. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  200. "wifi RSSI state stay at Low\n");
  201. }
  202. } else if ((coex_sta->pre_wifi_rssi_state[index] ==
  203. BTC_RSSI_STATE_MEDIUM) ||
  204. (coex_sta->pre_wifi_rssi_state[index] ==
  205. BTC_RSSI_STATE_STAY_MEDIUM)) {
  206. if (wifirssi >= (rssi_thresh1 +
  207. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
  208. wifirssi_state = BTC_RSSI_STATE_HIGH;
  209. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  210. "wifi RSSI state switch to High\n");
  211. } else if (wifirssi < rssi_thresh) {
  212. wifirssi_state = BTC_RSSI_STATE_LOW;
  213. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  214. "wifi RSSI state switch to Low\n");
  215. } else {
  216. wifirssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  217. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  218. "wifi RSSI state stay at Medium\n");
  219. }
  220. } else {
  221. if (wifirssi < rssi_thresh1) {
  222. wifirssi_state = BTC_RSSI_STATE_MEDIUM;
  223. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  224. "wifi RSSI state switch to Medium\n");
  225. } else {
  226. wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
  227. btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
  228. "wifi RSSI state stay at High\n");
  229. }
  230. }
  231. }
  232. coex_sta->pre_wifi_rssi_state[index] = wifirssi_state;
  233. return wifirssi_state;
  234. }
  235. static void btc8192e2ant_monitor_bt_enable_dis(struct btc_coexist *btcoexist)
  236. {
  237. static bool pre_bt_disabled;
  238. static u32 bt_disable_cnt;
  239. bool bt_active = true, bt_disabled = false;
  240. /* This function check if bt is disabled */
  241. if (coex_sta->high_priority_tx == 0 &&
  242. coex_sta->high_priority_rx == 0 &&
  243. coex_sta->low_priority_tx == 0 &&
  244. coex_sta->low_priority_rx == 0)
  245. bt_active = false;
  246. if (coex_sta->high_priority_tx == 0xffff &&
  247. coex_sta->high_priority_rx == 0xffff &&
  248. coex_sta->low_priority_tx == 0xffff &&
  249. coex_sta->low_priority_rx == 0xffff)
  250. bt_active = false;
  251. if (bt_active) {
  252. bt_disable_cnt = 0;
  253. bt_disabled = false;
  254. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  255. &bt_disabled);
  256. btc_alg_dbg(ALGO_BT_MONITOR,
  257. "[BTCoex], BT is enabled !!\n");
  258. } else {
  259. bt_disable_cnt++;
  260. btc_alg_dbg(ALGO_BT_MONITOR,
  261. "[BTCoex], bt all counters = 0, %d times!!\n",
  262. bt_disable_cnt);
  263. if (bt_disable_cnt >= 2) {
  264. bt_disabled = true;
  265. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  266. &bt_disabled);
  267. btc_alg_dbg(ALGO_BT_MONITOR,
  268. "[BTCoex], BT is disabled !!\n");
  269. }
  270. }
  271. if (pre_bt_disabled != bt_disabled) {
  272. btc_alg_dbg(ALGO_BT_MONITOR,
  273. "[BTCoex], BT is from %s to %s!!\n",
  274. (pre_bt_disabled ? "disabled" : "enabled"),
  275. (bt_disabled ? "disabled" : "enabled"));
  276. pre_bt_disabled = bt_disabled;
  277. }
  278. }
  279. static u32 halbtc8192e2ant_decidera_mask(struct btc_coexist *btcoexist,
  280. u8 sstype, u32 ra_masktype)
  281. {
  282. u32 disra_mask = 0x0;
  283. switch (ra_masktype) {
  284. case 0: /* normal mode */
  285. if (sstype == 2)
  286. disra_mask = 0x0; /* enable 2ss */
  287. else
  288. disra_mask = 0xfff00000;/* disable 2ss */
  289. break;
  290. case 1: /* disable cck 1/2 */
  291. if (sstype == 2)
  292. disra_mask = 0x00000003;/* enable 2ss */
  293. else
  294. disra_mask = 0xfff00003;/* disable 2ss */
  295. break;
  296. case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
  297. if (sstype == 2)
  298. disra_mask = 0x0001f1f7;/* enable 2ss */
  299. else
  300. disra_mask = 0xfff1f1f7;/* disable 2ss */
  301. break;
  302. default:
  303. break;
  304. }
  305. return disra_mask;
  306. }
  307. static void halbtc8192e2ant_Updatera_mask(struct btc_coexist *btcoexist,
  308. bool force_exec, u32 dis_ratemask)
  309. {
  310. coex_dm->curra_mask = dis_ratemask;
  311. if (force_exec || (coex_dm->prera_mask != coex_dm->curra_mask))
  312. btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_ra_mask,
  313. &coex_dm->curra_mask);
  314. coex_dm->prera_mask = coex_dm->curra_mask;
  315. }
  316. static void btc8192e2ant_autorate_fallback_retry(struct btc_coexist *btcoexist,
  317. bool force_exec, u8 type)
  318. {
  319. bool wifi_under_bmode = false;
  320. coex_dm->cur_arfrtype = type;
  321. if (force_exec || (coex_dm->pre_arfrtype != coex_dm->cur_arfrtype)) {
  322. switch (coex_dm->cur_arfrtype) {
  323. case 0: /* normal mode */
  324. btcoexist->btc_write_4byte(btcoexist, 0x430,
  325. coex_dm->backup_arfr_cnt1);
  326. btcoexist->btc_write_4byte(btcoexist, 0x434,
  327. coex_dm->backup_arfr_cnt2);
  328. break;
  329. case 1:
  330. btcoexist->btc_get(btcoexist,
  331. BTC_GET_BL_WIFI_UNDER_B_MODE,
  332. &wifi_under_bmode);
  333. if (wifi_under_bmode) {
  334. btcoexist->btc_write_4byte(btcoexist, 0x430,
  335. 0x0);
  336. btcoexist->btc_write_4byte(btcoexist, 0x434,
  337. 0x01010101);
  338. } else {
  339. btcoexist->btc_write_4byte(btcoexist, 0x430,
  340. 0x0);
  341. btcoexist->btc_write_4byte(btcoexist, 0x434,
  342. 0x04030201);
  343. }
  344. break;
  345. default:
  346. break;
  347. }
  348. }
  349. coex_dm->pre_arfrtype = coex_dm->cur_arfrtype;
  350. }
  351. static void halbtc8192e2ant_retrylimit(struct btc_coexist *btcoexist,
  352. bool force_exec, u8 type)
  353. {
  354. coex_dm->cur_retrylimit_type = type;
  355. if (force_exec || (coex_dm->pre_retrylimit_type !=
  356. coex_dm->cur_retrylimit_type)) {
  357. switch (coex_dm->cur_retrylimit_type) {
  358. case 0: /* normal mode */
  359. btcoexist->btc_write_2byte(btcoexist, 0x42a,
  360. coex_dm->backup_retrylimit);
  361. break;
  362. case 1: /* retry limit = 8 */
  363. btcoexist->btc_write_2byte(btcoexist, 0x42a,
  364. 0x0808);
  365. break;
  366. default:
  367. break;
  368. }
  369. }
  370. coex_dm->pre_retrylimit_type = coex_dm->cur_retrylimit_type;
  371. }
  372. static void halbtc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist,
  373. bool force_exec, u8 type)
  374. {
  375. coex_dm->cur_ampdutime_type = type;
  376. if (force_exec || (coex_dm->pre_ampdutime_type !=
  377. coex_dm->cur_ampdutime_type)) {
  378. switch (coex_dm->cur_ampdutime_type) {
  379. case 0: /* normal mode */
  380. btcoexist->btc_write_1byte(btcoexist, 0x456,
  381. coex_dm->backup_ampdu_maxtime);
  382. break;
  383. case 1: /* AMPDU timw = 0x38 * 32us */
  384. btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
  385. break;
  386. default:
  387. break;
  388. }
  389. }
  390. coex_dm->pre_ampdutime_type = coex_dm->cur_ampdutime_type;
  391. }
  392. static void halbtc8192e2ant_limited_tx(struct btc_coexist *btcoexist,
  393. bool force_exec, u8 ra_masktype,
  394. u8 arfr_type, u8 retrylimit_type,
  395. u8 ampdutime_type)
  396. {
  397. u32 disra_mask = 0x0;
  398. coex_dm->curra_masktype = ra_masktype;
  399. disra_mask = halbtc8192e2ant_decidera_mask(btcoexist,
  400. coex_dm->cur_sstype,
  401. ra_masktype);
  402. halbtc8192e2ant_Updatera_mask(btcoexist, force_exec, disra_mask);
  403. btc8192e2ant_autorate_fallback_retry(btcoexist, force_exec, arfr_type);
  404. halbtc8192e2ant_retrylimit(btcoexist, force_exec, retrylimit_type);
  405. halbtc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdutime_type);
  406. }
  407. static void halbtc8192e2ant_limited_rx(struct btc_coexist *btcoexist,
  408. bool force_exec, bool rej_ap_agg_pkt,
  409. bool bt_ctrl_agg_buf_size,
  410. u8 agg_buf_size)
  411. {
  412. bool reject_rx_agg = rej_ap_agg_pkt;
  413. bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
  414. u8 rx_agg_size = agg_buf_size;
  415. /*********************************************
  416. * Rx Aggregation related setting
  417. *********************************************/
  418. btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
  419. &reject_rx_agg);
  420. /* decide BT control aggregation buf size or not */
  421. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
  422. &bt_ctrl_rx_agg_size);
  423. /* aggregation buf size, only work
  424. * when BT control Rx aggregation size.
  425. */
  426. btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
  427. /* real update aggregation setting */
  428. btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
  429. }
  430. static void halbtc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
  431. {
  432. u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
  433. u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
  434. reg_hp_txrx = 0x770;
  435. reg_lp_txrx = 0x774;
  436. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
  437. reg_hp_tx = u32tmp & MASKLWORD;
  438. reg_hp_rx = (u32tmp & MASKHWORD)>>16;
  439. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
  440. reg_lp_tx = u32tmp & MASKLWORD;
  441. reg_lp_rx = (u32tmp & MASKHWORD)>>16;
  442. coex_sta->high_priority_tx = reg_hp_tx;
  443. coex_sta->high_priority_rx = reg_hp_rx;
  444. coex_sta->low_priority_tx = reg_lp_tx;
  445. coex_sta->low_priority_rx = reg_lp_rx;
  446. btc_alg_dbg(ALGO_BT_MONITOR,
  447. "[BTCoex] High Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  448. reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
  449. btc_alg_dbg(ALGO_BT_MONITOR,
  450. "[BTCoex] Low Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  451. reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
  452. /* reset counter */
  453. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
  454. }
  455. static void halbtc8192e2ant_querybt_info(struct btc_coexist *btcoexist)
  456. {
  457. u8 h2c_parameter[1] = {0};
  458. coex_sta->c2h_bt_info_req_sent = true;
  459. h2c_parameter[0] |= BIT0; /* trigger */
  460. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  461. "[BTCoex], Query Bt Info, FW write 0x61 = 0x%x\n",
  462. h2c_parameter[0]);
  463. btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
  464. }
  465. static void halbtc8192e2ant_update_btlink_info(struct btc_coexist *btcoexist)
  466. {
  467. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  468. bool bt_hson = false;
  469. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
  470. bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
  471. bt_link_info->sco_exist = coex_sta->sco_exist;
  472. bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
  473. bt_link_info->pan_exist = coex_sta->pan_exist;
  474. bt_link_info->hid_exist = coex_sta->hid_exist;
  475. /* work around for HS mode. */
  476. if (bt_hson) {
  477. bt_link_info->pan_exist = true;
  478. bt_link_info->bt_link_exist = true;
  479. }
  480. /* check if Sco only */
  481. if (bt_link_info->sco_exist &&
  482. !bt_link_info->a2dp_exist &&
  483. !bt_link_info->pan_exist &&
  484. !bt_link_info->hid_exist)
  485. bt_link_info->sco_only = true;
  486. else
  487. bt_link_info->sco_only = false;
  488. /* check if A2dp only */
  489. if (!bt_link_info->sco_exist &&
  490. bt_link_info->a2dp_exist &&
  491. !bt_link_info->pan_exist &&
  492. !bt_link_info->hid_exist)
  493. bt_link_info->a2dp_only = true;
  494. else
  495. bt_link_info->a2dp_only = false;
  496. /* check if Pan only */
  497. if (!bt_link_info->sco_exist &&
  498. !bt_link_info->a2dp_exist &&
  499. bt_link_info->pan_exist &&
  500. !bt_link_info->hid_exist)
  501. bt_link_info->pan_only = true;
  502. else
  503. bt_link_info->pan_only = false;
  504. /* check if Hid only */
  505. if (!bt_link_info->sco_exist &&
  506. !bt_link_info->a2dp_exist &&
  507. !bt_link_info->pan_exist &&
  508. bt_link_info->hid_exist)
  509. bt_link_info->hid_only = true;
  510. else
  511. bt_link_info->hid_only = false;
  512. }
  513. static u8 halbtc8192e2ant_action_algorithm(struct btc_coexist *btcoexist)
  514. {
  515. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  516. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  517. bool bt_hson = false;
  518. u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
  519. u8 numdiffprofile = 0;
  520. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
  521. if (!bt_link_info->bt_link_exist) {
  522. btc_alg_dbg(ALGO_TRACE,
  523. "No BT link exists!!!\n");
  524. return algorithm;
  525. }
  526. if (bt_link_info->sco_exist)
  527. numdiffprofile++;
  528. if (bt_link_info->hid_exist)
  529. numdiffprofile++;
  530. if (bt_link_info->pan_exist)
  531. numdiffprofile++;
  532. if (bt_link_info->a2dp_exist)
  533. numdiffprofile++;
  534. if (numdiffprofile == 1) {
  535. if (bt_link_info->sco_exist) {
  536. btc_alg_dbg(ALGO_TRACE,
  537. "SCO only\n");
  538. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  539. } else {
  540. if (bt_link_info->hid_exist) {
  541. btc_alg_dbg(ALGO_TRACE,
  542. "HID only\n");
  543. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  544. } else if (bt_link_info->a2dp_exist) {
  545. btc_alg_dbg(ALGO_TRACE,
  546. "A2DP only\n");
  547. algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
  548. } else if (bt_link_info->pan_exist) {
  549. if (bt_hson) {
  550. btc_alg_dbg(ALGO_TRACE,
  551. "PAN(HS) only\n");
  552. algorithm =
  553. BT_8192E_2ANT_COEX_ALGO_PANHS;
  554. } else {
  555. btc_alg_dbg(ALGO_TRACE,
  556. "PAN(EDR) only\n");
  557. algorithm =
  558. BT_8192E_2ANT_COEX_ALGO_PANEDR;
  559. }
  560. }
  561. }
  562. } else if (numdiffprofile == 2) {
  563. if (bt_link_info->sco_exist) {
  564. if (bt_link_info->hid_exist) {
  565. btc_alg_dbg(ALGO_TRACE,
  566. "SCO + HID\n");
  567. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  568. } else if (bt_link_info->a2dp_exist) {
  569. btc_alg_dbg(ALGO_TRACE,
  570. "SCO + A2DP ==> SCO\n");
  571. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  572. } else if (bt_link_info->pan_exist) {
  573. if (bt_hson) {
  574. btc_alg_dbg(ALGO_TRACE,
  575. "SCO + PAN(HS)\n");
  576. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  577. } else {
  578. btc_alg_dbg(ALGO_TRACE,
  579. "SCO + PAN(EDR)\n");
  580. algorithm =
  581. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  582. }
  583. }
  584. } else {
  585. if (bt_link_info->hid_exist &&
  586. bt_link_info->a2dp_exist) {
  587. if (stack_info->num_of_hid >= 2) {
  588. btc_alg_dbg(ALGO_TRACE,
  589. "HID*2 + A2DP\n");
  590. algorithm =
  591. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  592. } else {
  593. btc_alg_dbg(ALGO_TRACE,
  594. "HID + A2DP\n");
  595. algorithm =
  596. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  597. }
  598. } else if (bt_link_info->hid_exist &&
  599. bt_link_info->pan_exist) {
  600. if (bt_hson) {
  601. btc_alg_dbg(ALGO_TRACE,
  602. "HID + PAN(HS)\n");
  603. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  604. } else {
  605. btc_alg_dbg(ALGO_TRACE,
  606. "HID + PAN(EDR)\n");
  607. algorithm =
  608. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  609. }
  610. } else if (bt_link_info->pan_exist &&
  611. bt_link_info->a2dp_exist) {
  612. if (bt_hson) {
  613. btc_alg_dbg(ALGO_TRACE,
  614. "A2DP + PAN(HS)\n");
  615. algorithm =
  616. BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
  617. } else {
  618. btc_alg_dbg(ALGO_TRACE,
  619. "A2DP + PAN(EDR)\n");
  620. algorithm =
  621. BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
  622. }
  623. }
  624. }
  625. } else if (numdiffprofile == 3) {
  626. if (bt_link_info->sco_exist) {
  627. if (bt_link_info->hid_exist &&
  628. bt_link_info->a2dp_exist) {
  629. btc_alg_dbg(ALGO_TRACE,
  630. "SCO + HID + A2DP ==> HID\n");
  631. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  632. } else if (bt_link_info->hid_exist &&
  633. bt_link_info->pan_exist) {
  634. if (bt_hson) {
  635. btc_alg_dbg(ALGO_TRACE,
  636. "SCO + HID + PAN(HS)\n");
  637. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  638. } else {
  639. btc_alg_dbg(ALGO_TRACE,
  640. "SCO + HID + PAN(EDR)\n");
  641. algorithm =
  642. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  643. }
  644. } else if (bt_link_info->pan_exist &&
  645. bt_link_info->a2dp_exist) {
  646. if (bt_hson) {
  647. btc_alg_dbg(ALGO_TRACE,
  648. "SCO + A2DP + PAN(HS)\n");
  649. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  650. } else {
  651. btc_alg_dbg(ALGO_TRACE,
  652. "SCO + A2DP + PAN(EDR)\n");
  653. algorithm =
  654. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  655. }
  656. }
  657. } else {
  658. if (bt_link_info->hid_exist &&
  659. bt_link_info->pan_exist &&
  660. bt_link_info->a2dp_exist) {
  661. if (bt_hson) {
  662. btc_alg_dbg(ALGO_TRACE,
  663. "HID + A2DP + PAN(HS)\n");
  664. algorithm =
  665. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  666. } else {
  667. btc_alg_dbg(ALGO_TRACE,
  668. "HID + A2DP + PAN(EDR)\n");
  669. algorithm =
  670. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  671. }
  672. }
  673. }
  674. } else if (numdiffprofile >= 3) {
  675. if (bt_link_info->sco_exist) {
  676. if (bt_link_info->hid_exist &&
  677. bt_link_info->pan_exist &&
  678. bt_link_info->a2dp_exist) {
  679. if (bt_hson) {
  680. btc_alg_dbg(ALGO_TRACE,
  681. "ErrorSCO+HID+A2DP+PAN(HS)\n");
  682. } else {
  683. btc_alg_dbg(ALGO_TRACE,
  684. "SCO+HID+A2DP+PAN(EDR)\n");
  685. algorithm =
  686. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  687. }
  688. }
  689. }
  690. }
  691. return algorithm;
  692. }
  693. static void halbtc8192e2ant_setfw_dac_swinglevel(struct btc_coexist *btcoexist,
  694. u8 dac_swinglvl)
  695. {
  696. u8 h2c_parameter[1] = {0};
  697. /* There are several type of dacswing
  698. * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
  699. */
  700. h2c_parameter[0] = dac_swinglvl;
  701. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  702. "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swinglvl);
  703. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  704. "[BTCoex], FW write 0x64 = 0x%x\n", h2c_parameter[0]);
  705. btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
  706. }
  707. static void halbtc8192e2ant_set_fwdec_btpwr(struct btc_coexist *btcoexist,
  708. u8 dec_btpwr_lvl)
  709. {
  710. u8 h2c_parameter[1] = {0};
  711. h2c_parameter[0] = dec_btpwr_lvl;
  712. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  713. "[BTCoex] decrease Bt Power level = %d, FW write 0x62 = 0x%x\n",
  714. dec_btpwr_lvl, h2c_parameter[0]);
  715. btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
  716. }
  717. static void halbtc8192e2ant_dec_btpwr(struct btc_coexist *btcoexist,
  718. bool force_exec, u8 dec_btpwr_lvl)
  719. {
  720. btc_alg_dbg(ALGO_TRACE_FW,
  721. "[BTCoex], %s Dec BT power level = %d\n",
  722. (force_exec ? "force to" : ""), dec_btpwr_lvl);
  723. coex_dm->cur_dec_bt_pwr = dec_btpwr_lvl;
  724. if (!force_exec) {
  725. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  726. "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
  727. coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
  728. }
  729. halbtc8192e2ant_set_fwdec_btpwr(btcoexist, coex_dm->cur_dec_bt_pwr);
  730. coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
  731. }
  732. static void halbtc8192e2ant_set_bt_autoreport(struct btc_coexist *btcoexist,
  733. bool enable_autoreport)
  734. {
  735. u8 h2c_parameter[1] = {0};
  736. h2c_parameter[0] = 0;
  737. if (enable_autoreport)
  738. h2c_parameter[0] |= BIT0;
  739. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  740. "[BTCoex], BT FW auto report : %s, FW write 0x68 = 0x%x\n",
  741. (enable_autoreport ? "Enabled!!" : "Disabled!!"),
  742. h2c_parameter[0]);
  743. btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
  744. }
  745. static void halbtc8192e2ant_bt_autoreport(struct btc_coexist *btcoexist,
  746. bool force_exec,
  747. bool enable_autoreport)
  748. {
  749. btc_alg_dbg(ALGO_TRACE_FW,
  750. "[BTCoex], %s BT Auto report = %s\n",
  751. (force_exec ? "force to" : ""),
  752. ((enable_autoreport) ? "Enabled" : "Disabled"));
  753. coex_dm->cur_bt_auto_report = enable_autoreport;
  754. if (!force_exec) {
  755. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  756. "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
  757. coex_dm->pre_bt_auto_report,
  758. coex_dm->cur_bt_auto_report);
  759. if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
  760. return;
  761. }
  762. halbtc8192e2ant_set_bt_autoreport(btcoexist,
  763. coex_dm->cur_bt_auto_report);
  764. coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
  765. }
  766. static void halbtc8192e2ant_fw_dac_swinglvl(struct btc_coexist *btcoexist,
  767. bool force_exec, u8 fw_dac_swinglvl)
  768. {
  769. btc_alg_dbg(ALGO_TRACE_FW,
  770. "[BTCoex], %s set FW Dac Swing level = %d\n",
  771. (force_exec ? "force to" : ""), fw_dac_swinglvl);
  772. coex_dm->cur_fw_dac_swing_lvl = fw_dac_swinglvl;
  773. if (!force_exec) {
  774. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  775. "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
  776. coex_dm->pre_fw_dac_swing_lvl,
  777. coex_dm->cur_fw_dac_swing_lvl);
  778. if (coex_dm->pre_fw_dac_swing_lvl ==
  779. coex_dm->cur_fw_dac_swing_lvl)
  780. return;
  781. }
  782. halbtc8192e2ant_setfw_dac_swinglevel(btcoexist,
  783. coex_dm->cur_fw_dac_swing_lvl);
  784. coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
  785. }
  786. static void btc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
  787. bool rx_rf_shrink_on)
  788. {
  789. if (rx_rf_shrink_on) {
  790. /* Shrink RF Rx LPF corner */
  791. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  792. "[BTCoex], Shrink RF Rx LPF corner!!\n");
  793. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  794. 0xfffff, 0xffffc);
  795. } else {
  796. /* Resume RF Rx LPF corner
  797. * After initialized, we can use coex_dm->btRf0x1eBackup
  798. */
  799. if (btcoexist->initilized) {
  800. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  801. "[BTCoex], Resume RF Rx LPF corner!!\n");
  802. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  803. 0xfffff,
  804. coex_dm->bt_rf0x1e_backup);
  805. }
  806. }
  807. }
  808. static void halbtc8192e2ant_rf_shrink(struct btc_coexist *btcoexist,
  809. bool force_exec, bool rx_rf_shrink_on)
  810. {
  811. btc_alg_dbg(ALGO_TRACE_SW,
  812. "[BTCoex], %s turn Rx RF Shrink = %s\n",
  813. (force_exec ? "force to" : ""),
  814. ((rx_rf_shrink_on) ? "ON" : "OFF"));
  815. coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
  816. if (!force_exec) {
  817. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  818. "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n",
  819. coex_dm->pre_rf_rx_lpf_shrink,
  820. coex_dm->cur_rf_rx_lpf_shrink);
  821. if (coex_dm->pre_rf_rx_lpf_shrink ==
  822. coex_dm->cur_rf_rx_lpf_shrink)
  823. return;
  824. }
  825. btc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
  826. coex_dm->cur_rf_rx_lpf_shrink);
  827. coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
  828. }
  829. static void halbtc8192e2ant_set_dac_swingreg(struct btc_coexist *btcoexist,
  830. u32 level)
  831. {
  832. u8 val = (u8)level;
  833. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  834. "[BTCoex], Write SwDacSwing = 0x%x\n", level);
  835. btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
  836. }
  837. static void btc8192e2ant_setsw_full_swing(struct btc_coexist *btcoexist,
  838. bool sw_dac_swingon,
  839. u32 sw_dac_swinglvl)
  840. {
  841. if (sw_dac_swingon)
  842. halbtc8192e2ant_set_dac_swingreg(btcoexist, sw_dac_swinglvl);
  843. else
  844. halbtc8192e2ant_set_dac_swingreg(btcoexist, 0x18);
  845. }
  846. static void halbtc8192e2ant_DacSwing(struct btc_coexist *btcoexist,
  847. bool force_exec, bool dac_swingon,
  848. u32 dac_swinglvl)
  849. {
  850. btc_alg_dbg(ALGO_TRACE_SW,
  851. "[BTCoex], %s turn DacSwing=%s, dac_swinglvl = 0x%x\n",
  852. (force_exec ? "force to" : ""),
  853. ((dac_swingon) ? "ON" : "OFF"), dac_swinglvl);
  854. coex_dm->cur_dac_swing_on = dac_swingon;
  855. coex_dm->cur_dac_swing_lvl = dac_swinglvl;
  856. if (!force_exec) {
  857. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  858. "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl = 0x%x, ",
  859. coex_dm->pre_dac_swing_on,
  860. coex_dm->pre_dac_swing_lvl);
  861. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  862. "bCurDacSwingOn=%d, curDacSwingLvl = 0x%x\n",
  863. coex_dm->cur_dac_swing_on,
  864. coex_dm->cur_dac_swing_lvl);
  865. if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
  866. (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
  867. return;
  868. }
  869. mdelay(30);
  870. btc8192e2ant_setsw_full_swing(btcoexist, dac_swingon, dac_swinglvl);
  871. coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
  872. coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
  873. }
  874. static void halbtc8192e2ant_set_agc_table(struct btc_coexist *btcoexist,
  875. bool agc_table_en)
  876. {
  877. /* BB AGC Gain Table */
  878. if (agc_table_en) {
  879. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  880. "[BTCoex], BB Agc Table On!\n");
  881. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
  882. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
  883. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
  884. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
  885. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
  886. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
  887. } else {
  888. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  889. "[BTCoex], BB Agc Table Off!\n");
  890. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
  891. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
  892. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
  893. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
  894. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
  895. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
  896. }
  897. }
  898. static void halbtc8192e2ant_AgcTable(struct btc_coexist *btcoexist,
  899. bool force_exec, bool agc_table_en)
  900. {
  901. btc_alg_dbg(ALGO_TRACE_SW,
  902. "[BTCoex], %s %s Agc Table\n",
  903. (force_exec ? "force to" : ""),
  904. ((agc_table_en) ? "Enable" : "Disable"));
  905. coex_dm->cur_agc_table_en = agc_table_en;
  906. if (!force_exec) {
  907. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  908. "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
  909. coex_dm->pre_agc_table_en,
  910. coex_dm->cur_agc_table_en);
  911. if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
  912. return;
  913. }
  914. halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en);
  915. coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
  916. }
  917. static void halbtc8192e2ant_set_coex_table(struct btc_coexist *btcoexist,
  918. u32 val0x6c0, u32 val0x6c4,
  919. u32 val0x6c8, u8 val0x6cc)
  920. {
  921. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  922. "[BTCoex], set coex table, set 0x6c0 = 0x%x\n", val0x6c0);
  923. btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
  924. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  925. "[BTCoex], set coex table, set 0x6c4 = 0x%x\n", val0x6c4);
  926. btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
  927. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  928. "[BTCoex], set coex table, set 0x6c8 = 0x%x\n", val0x6c8);
  929. btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
  930. btc_alg_dbg(ALGO_TRACE_SW_EXEC,
  931. "[BTCoex], set coex table, set 0x6cc = 0x%x\n", val0x6cc);
  932. btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
  933. }
  934. static void halbtc8192e2ant_coex_table(struct btc_coexist *btcoexist,
  935. bool force_exec,
  936. u32 val0x6c0, u32 val0x6c4,
  937. u32 val0x6c8, u8 val0x6cc)
  938. {
  939. btc_alg_dbg(ALGO_TRACE_SW,
  940. "[BTCoex], %s write Coex Table 0x6c0 = 0x%x, ",
  941. (force_exec ? "force to" : ""), val0x6c0);
  942. btc_alg_dbg(ALGO_TRACE_SW,
  943. "0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x\n",
  944. val0x6c4, val0x6c8, val0x6cc);
  945. coex_dm->cur_val0x6c0 = val0x6c0;
  946. coex_dm->cur_val0x6c4 = val0x6c4;
  947. coex_dm->cur_val0x6c8 = val0x6c8;
  948. coex_dm->cur_val0x6cc = val0x6cc;
  949. if (!force_exec) {
  950. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  951. "[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, ",
  952. coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4);
  953. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  954. "preVal0x6c8 = 0x%x, preVal0x6cc = 0x%x !!\n",
  955. coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
  956. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  957. "[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x\n",
  958. coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4);
  959. btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
  960. "curVal0x6c8 = 0x%x, curVal0x6cc = 0x%x !!\n",
  961. coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
  962. if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
  963. (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
  964. (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
  965. (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
  966. return;
  967. }
  968. halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
  969. val0x6c8, val0x6cc);
  970. coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
  971. coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
  972. coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
  973. coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
  974. }
  975. static void btc8192e2ant_coex_tbl_w_type(struct btc_coexist *btcoexist,
  976. bool force_exec, u8 type)
  977. {
  978. switch (type) {
  979. case 0:
  980. halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  981. 0x5a5a5a5a, 0xffffff, 0x3);
  982. break;
  983. case 1:
  984. halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
  985. 0x5a5a5a5a, 0xffffff, 0x3);
  986. break;
  987. case 2:
  988. halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  989. 0x5ffb5ffb, 0xffffff, 0x3);
  990. break;
  991. case 3:
  992. halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  993. 0x5fdb5fdb, 0xffffff, 0x3);
  994. break;
  995. case 4:
  996. halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  997. 0x5ffb5ffb, 0xffffff, 0x3);
  998. break;
  999. default:
  1000. break;
  1001. }
  1002. }
  1003. static void halbtc8192e2ant_set_fw_ignore_wlanact(struct btc_coexist *btcoexist,
  1004. bool enable)
  1005. {
  1006. u8 h2c_parameter[1] = {0};
  1007. if (enable)
  1008. h2c_parameter[0] |= BIT0; /* function enable */
  1009. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  1010. "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63 = 0x%x\n",
  1011. h2c_parameter[0]);
  1012. btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
  1013. }
  1014. static void halbtc8192e2ant_IgnoreWlanAct(struct btc_coexist *btcoexist,
  1015. bool force_exec, bool enable)
  1016. {
  1017. btc_alg_dbg(ALGO_TRACE_FW,
  1018. "[BTCoex], %s turn Ignore WlanAct %s\n",
  1019. (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
  1020. coex_dm->cur_ignore_wlan_act = enable;
  1021. if (!force_exec) {
  1022. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1023. "[BTCoex], bPreIgnoreWlanAct = %d ",
  1024. coex_dm->pre_ignore_wlan_act);
  1025. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1026. "bCurIgnoreWlanAct = %d!!\n",
  1027. coex_dm->cur_ignore_wlan_act);
  1028. if (coex_dm->pre_ignore_wlan_act ==
  1029. coex_dm->cur_ignore_wlan_act)
  1030. return;
  1031. }
  1032. halbtc8192e2ant_set_fw_ignore_wlanact(btcoexist, enable);
  1033. coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
  1034. }
  1035. static void halbtc8192e2ant_SetFwPstdma(struct btc_coexist *btcoexist, u8 byte1,
  1036. u8 byte2, u8 byte3, u8 byte4, u8 byte5)
  1037. {
  1038. u8 h2c_parameter[5] = {0};
  1039. h2c_parameter[0] = byte1;
  1040. h2c_parameter[1] = byte2;
  1041. h2c_parameter[2] = byte3;
  1042. h2c_parameter[3] = byte4;
  1043. h2c_parameter[4] = byte5;
  1044. coex_dm->ps_tdma_para[0] = byte1;
  1045. coex_dm->ps_tdma_para[1] = byte2;
  1046. coex_dm->ps_tdma_para[2] = byte3;
  1047. coex_dm->ps_tdma_para[3] = byte4;
  1048. coex_dm->ps_tdma_para[4] = byte5;
  1049. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  1050. "[BTCoex], FW write 0x60(5bytes) = 0x%x%08x\n",
  1051. h2c_parameter[0],
  1052. h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
  1053. h2c_parameter[3] << 8 | h2c_parameter[4]);
  1054. btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
  1055. }
  1056. static void btc8192e2ant_sw_mec1(struct btc_coexist *btcoexist,
  1057. bool shrink_rx_lpf, bool low_penalty_ra,
  1058. bool limited_dig, bool btlan_constrain)
  1059. {
  1060. halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
  1061. }
  1062. static void btc8192e2ant_sw_mec2(struct btc_coexist *btcoexist,
  1063. bool agc_table_shift, bool adc_backoff,
  1064. bool sw_dac_swing, u32 dac_swinglvl)
  1065. {
  1066. halbtc8192e2ant_AgcTable(btcoexist, NORMAL_EXEC, agc_table_shift);
  1067. halbtc8192e2ant_DacSwing(btcoexist, NORMAL_EXEC, sw_dac_swing,
  1068. dac_swinglvl);
  1069. }
  1070. static void halbtc8192e2ant_ps_tdma(struct btc_coexist *btcoexist,
  1071. bool force_exec, bool turn_on, u8 type)
  1072. {
  1073. btc_alg_dbg(ALGO_TRACE_FW,
  1074. "[BTCoex], %s turn %s PS TDMA, type=%d\n",
  1075. (force_exec ? "force to" : ""),
  1076. (turn_on ? "ON" : "OFF"), type);
  1077. coex_dm->cur_ps_tdma_on = turn_on;
  1078. coex_dm->cur_ps_tdma = type;
  1079. if (!force_exec) {
  1080. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1081. "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
  1082. coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
  1083. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1084. "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
  1085. coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
  1086. if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
  1087. (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
  1088. return;
  1089. }
  1090. if (turn_on) {
  1091. switch (type) {
  1092. case 1:
  1093. default:
  1094. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
  1095. 0x1a, 0xe1, 0x90);
  1096. break;
  1097. case 2:
  1098. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
  1099. 0x12, 0xe1, 0x90);
  1100. break;
  1101. case 3:
  1102. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
  1103. 0x3, 0xf1, 0x90);
  1104. break;
  1105. case 4:
  1106. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
  1107. 0x3, 0xf1, 0x90);
  1108. break;
  1109. case 5:
  1110. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
  1111. 0x1a, 0x60, 0x90);
  1112. break;
  1113. case 6:
  1114. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
  1115. 0x12, 0x60, 0x90);
  1116. break;
  1117. case 7:
  1118. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
  1119. 0x3, 0x70, 0x90);
  1120. break;
  1121. case 8:
  1122. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xa3, 0x10,
  1123. 0x3, 0x70, 0x90);
  1124. break;
  1125. case 9:
  1126. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
  1127. 0x1a, 0xe1, 0x10);
  1128. break;
  1129. case 10:
  1130. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
  1131. 0x12, 0xe1, 0x10);
  1132. break;
  1133. case 11:
  1134. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
  1135. 0x3, 0xf1, 0x10);
  1136. break;
  1137. case 12:
  1138. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
  1139. 0x3, 0xf1, 0x10);
  1140. break;
  1141. case 13:
  1142. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
  1143. 0x1a, 0xe0, 0x10);
  1144. break;
  1145. case 14:
  1146. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
  1147. 0x12, 0xe0, 0x10);
  1148. break;
  1149. case 15:
  1150. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
  1151. 0x3, 0xf0, 0x10);
  1152. break;
  1153. case 16:
  1154. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
  1155. 0x3, 0xf0, 0x10);
  1156. break;
  1157. case 17:
  1158. halbtc8192e2ant_SetFwPstdma(btcoexist, 0x61, 0x20,
  1159. 0x03, 0x10, 0x10);
  1160. break;
  1161. case 18:
  1162. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x5,
  1163. 0x5, 0xe1, 0x90);
  1164. break;
  1165. case 19:
  1166. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
  1167. 0x25, 0xe1, 0x90);
  1168. break;
  1169. case 20:
  1170. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
  1171. 0x25, 0x60, 0x90);
  1172. break;
  1173. case 21:
  1174. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x15,
  1175. 0x03, 0x70, 0x90);
  1176. break;
  1177. case 71:
  1178. halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
  1179. 0x1a, 0xe1, 0x90);
  1180. break;
  1181. }
  1182. } else {
  1183. /* disable PS tdma */
  1184. switch (type) {
  1185. default:
  1186. case 0:
  1187. halbtc8192e2ant_SetFwPstdma(btcoexist, 0x8, 0x0, 0x0,
  1188. 0x0, 0x0);
  1189. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
  1190. break;
  1191. case 1:
  1192. halbtc8192e2ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0,
  1193. 0x8, 0x0);
  1194. mdelay(5);
  1195. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  1196. break;
  1197. }
  1198. }
  1199. /* update pre state */
  1200. coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
  1201. coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
  1202. }
  1203. static void halbtc8192e2ant_set_switch_sstype(struct btc_coexist *btcoexist,
  1204. u8 sstype)
  1205. {
  1206. u8 mimops = BTC_MIMO_PS_DYNAMIC;
  1207. u32 disra_mask = 0x0;
  1208. btc_alg_dbg(ALGO_TRACE,
  1209. "[BTCoex], REAL set SS Type = %d\n", sstype);
  1210. disra_mask = halbtc8192e2ant_decidera_mask(btcoexist, sstype,
  1211. coex_dm->curra_masktype);
  1212. halbtc8192e2ant_Updatera_mask(btcoexist, FORCE_EXEC, disra_mask);
  1213. if (sstype == 1) {
  1214. halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1215. /* switch ofdm path */
  1216. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
  1217. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
  1218. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
  1219. /* switch cck patch */
  1220. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1);
  1221. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81);
  1222. mimops = BTC_MIMO_PS_STATIC;
  1223. } else if (sstype == 2) {
  1224. halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
  1225. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
  1226. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
  1227. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
  1228. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0);
  1229. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41);
  1230. mimops = BTC_MIMO_PS_DYNAMIC;
  1231. }
  1232. /* set rx 1ss or 2ss */
  1233. btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops);
  1234. }
  1235. static void halbtc8192e2ant_switch_sstype(struct btc_coexist *btcoexist,
  1236. bool force_exec, u8 new_sstype)
  1237. {
  1238. btc_alg_dbg(ALGO_TRACE,
  1239. "[BTCoex], %s Switch SS Type = %d\n",
  1240. (force_exec ? "force to" : ""), new_sstype);
  1241. coex_dm->cur_sstype = new_sstype;
  1242. if (!force_exec) {
  1243. if (coex_dm->pre_sstype == coex_dm->cur_sstype)
  1244. return;
  1245. }
  1246. halbtc8192e2ant_set_switch_sstype(btcoexist, coex_dm->cur_sstype);
  1247. coex_dm->pre_sstype = coex_dm->cur_sstype;
  1248. }
  1249. static void halbtc8192e2ant_coex_alloff(struct btc_coexist *btcoexist)
  1250. {
  1251. /* fw all off */
  1252. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1253. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  1254. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  1255. /* sw all off */
  1256. btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
  1257. btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
  1258. /* hw all off */
  1259. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0);
  1260. }
  1261. static void halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  1262. {
  1263. /* force to reset coex mechanism */
  1264. halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1265. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, FORCE_EXEC, 6);
  1266. halbtc8192e2ant_dec_btpwr(btcoexist, FORCE_EXEC, 0);
  1267. btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0);
  1268. halbtc8192e2ant_switch_sstype(btcoexist, FORCE_EXEC, 2);
  1269. btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
  1270. btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
  1271. }
  1272. static void halbtc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
  1273. {
  1274. bool low_pwr_disable = true;
  1275. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1276. &low_pwr_disable);
  1277. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  1278. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  1279. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
  1280. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  1281. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  1282. btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
  1283. btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
  1284. }
  1285. static bool halbtc8192e2ant_is_common_action(struct btc_coexist *btcoexist)
  1286. {
  1287. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  1288. bool common = false, wifi_connected = false, wifi_busy = false;
  1289. bool bt_hson = false, low_pwr_disable = false;
  1290. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
  1291. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  1292. &wifi_connected);
  1293. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  1294. if (bt_link_info->sco_exist || bt_link_info->hid_exist)
  1295. halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
  1296. else
  1297. halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
  1298. if (!wifi_connected) {
  1299. low_pwr_disable = false;
  1300. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1301. &low_pwr_disable);
  1302. btc_alg_dbg(ALGO_TRACE,
  1303. "[BTCoex], Wifi non-connected idle!!\n");
  1304. if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1305. coex_dm->bt_status) ||
  1306. (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1307. coex_dm->bt_status)) {
  1308. halbtc8192e2ant_switch_sstype(btcoexist,
  1309. NORMAL_EXEC, 2);
  1310. btc8192e2ant_coex_tbl_w_type(btcoexist,
  1311. NORMAL_EXEC, 1);
  1312. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1313. false, 0);
  1314. } else {
  1315. halbtc8192e2ant_switch_sstype(btcoexist,
  1316. NORMAL_EXEC, 1);
  1317. btc8192e2ant_coex_tbl_w_type(btcoexist,
  1318. NORMAL_EXEC, 0);
  1319. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1320. false, 1);
  1321. }
  1322. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  1323. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  1324. btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
  1325. btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
  1326. common = true;
  1327. } else {
  1328. if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1329. coex_dm->bt_status) {
  1330. low_pwr_disable = false;
  1331. btcoexist->btc_set(btcoexist,
  1332. BTC_SET_ACT_DISABLE_LOW_POWER,
  1333. &low_pwr_disable);
  1334. btc_alg_dbg(ALGO_TRACE,
  1335. "Wifi connected + BT non connected-idle!!\n");
  1336. halbtc8192e2ant_switch_sstype(btcoexist,
  1337. NORMAL_EXEC, 2);
  1338. btc8192e2ant_coex_tbl_w_type(btcoexist,
  1339. NORMAL_EXEC, 1);
  1340. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1341. false, 0);
  1342. halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
  1343. NORMAL_EXEC, 6);
  1344. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  1345. btc8192e2ant_sw_mec1(btcoexist, false, false,
  1346. false, false);
  1347. btc8192e2ant_sw_mec2(btcoexist, false, false,
  1348. false, 0x18);
  1349. common = true;
  1350. } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1351. coex_dm->bt_status) {
  1352. low_pwr_disable = true;
  1353. btcoexist->btc_set(btcoexist,
  1354. BTC_SET_ACT_DISABLE_LOW_POWER,
  1355. &low_pwr_disable);
  1356. if (bt_hson)
  1357. return false;
  1358. btc_alg_dbg(ALGO_TRACE,
  1359. "Wifi connected + BT connected-idle!!\n");
  1360. halbtc8192e2ant_switch_sstype(btcoexist,
  1361. NORMAL_EXEC, 2);
  1362. btc8192e2ant_coex_tbl_w_type(btcoexist,
  1363. NORMAL_EXEC, 1);
  1364. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1365. false, 0);
  1366. halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
  1367. NORMAL_EXEC, 6);
  1368. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  1369. btc8192e2ant_sw_mec1(btcoexist, true, false,
  1370. false, false);
  1371. btc8192e2ant_sw_mec2(btcoexist, false, false,
  1372. false, 0x18);
  1373. common = true;
  1374. } else {
  1375. low_pwr_disable = true;
  1376. btcoexist->btc_set(btcoexist,
  1377. BTC_SET_ACT_DISABLE_LOW_POWER,
  1378. &low_pwr_disable);
  1379. if (wifi_busy) {
  1380. btc_alg_dbg(ALGO_TRACE,
  1381. "Wifi Connected-Busy + BT Busy!!\n");
  1382. common = false;
  1383. } else {
  1384. btc_alg_dbg(ALGO_TRACE,
  1385. "Wifi Connected-Idle + BT Busy!!\n");
  1386. halbtc8192e2ant_switch_sstype(btcoexist,
  1387. NORMAL_EXEC, 1);
  1388. btc8192e2ant_coex_tbl_w_type(btcoexist,
  1389. NORMAL_EXEC, 2);
  1390. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1391. true, 21);
  1392. halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
  1393. NORMAL_EXEC, 6);
  1394. halbtc8192e2ant_dec_btpwr(btcoexist,
  1395. NORMAL_EXEC, 0);
  1396. btc8192e2ant_sw_mec1(btcoexist, false,
  1397. false, false, false);
  1398. btc8192e2ant_sw_mec2(btcoexist, false,
  1399. false, false, 0x18);
  1400. common = true;
  1401. }
  1402. }
  1403. }
  1404. return common;
  1405. }
  1406. static void btc8192e_int1(struct btc_coexist *btcoexist, bool tx_pause,
  1407. int result)
  1408. {
  1409. if (tx_pause) {
  1410. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1411. "[BTCoex], TxPause = 1\n");
  1412. if (coex_dm->cur_ps_tdma == 71) {
  1413. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1414. true, 5);
  1415. coex_dm->tdma_adj_type = 5;
  1416. } else if (coex_dm->cur_ps_tdma == 1) {
  1417. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1418. true, 5);
  1419. coex_dm->tdma_adj_type = 5;
  1420. } else if (coex_dm->cur_ps_tdma == 2) {
  1421. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1422. true, 6);
  1423. coex_dm->tdma_adj_type = 6;
  1424. } else if (coex_dm->cur_ps_tdma == 3) {
  1425. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1426. true, 7);
  1427. coex_dm->tdma_adj_type = 7;
  1428. } else if (coex_dm->cur_ps_tdma == 4) {
  1429. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1430. true, 8);
  1431. coex_dm->tdma_adj_type = 8;
  1432. }
  1433. if (coex_dm->cur_ps_tdma == 9) {
  1434. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1435. true, 13);
  1436. coex_dm->tdma_adj_type = 13;
  1437. } else if (coex_dm->cur_ps_tdma == 10) {
  1438. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1439. true, 14);
  1440. coex_dm->tdma_adj_type = 14;
  1441. } else if (coex_dm->cur_ps_tdma == 11) {
  1442. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1443. true, 15);
  1444. coex_dm->tdma_adj_type = 15;
  1445. } else if (coex_dm->cur_ps_tdma == 12) {
  1446. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1447. true, 16);
  1448. coex_dm->tdma_adj_type = 16;
  1449. }
  1450. if (result == -1) {
  1451. if (coex_dm->cur_ps_tdma == 5) {
  1452. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1453. true, 6);
  1454. coex_dm->tdma_adj_type = 6;
  1455. } else if (coex_dm->cur_ps_tdma == 6) {
  1456. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1457. true, 7);
  1458. coex_dm->tdma_adj_type = 7;
  1459. } else if (coex_dm->cur_ps_tdma == 7) {
  1460. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1461. true, 8);
  1462. coex_dm->tdma_adj_type = 8;
  1463. } else if (coex_dm->cur_ps_tdma == 13) {
  1464. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1465. true, 14);
  1466. coex_dm->tdma_adj_type = 14;
  1467. } else if (coex_dm->cur_ps_tdma == 14) {
  1468. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1469. true, 15);
  1470. coex_dm->tdma_adj_type = 15;
  1471. } else if (coex_dm->cur_ps_tdma == 15) {
  1472. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1473. true, 16);
  1474. coex_dm->tdma_adj_type = 16;
  1475. }
  1476. } else if (result == 1) {
  1477. if (coex_dm->cur_ps_tdma == 8) {
  1478. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1479. true, 7);
  1480. coex_dm->tdma_adj_type = 7;
  1481. } else if (coex_dm->cur_ps_tdma == 7) {
  1482. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1483. true, 6);
  1484. coex_dm->tdma_adj_type = 6;
  1485. } else if (coex_dm->cur_ps_tdma == 6) {
  1486. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1487. true, 5);
  1488. coex_dm->tdma_adj_type = 5;
  1489. } else if (coex_dm->cur_ps_tdma == 16) {
  1490. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1491. true, 15);
  1492. coex_dm->tdma_adj_type = 15;
  1493. } else if (coex_dm->cur_ps_tdma == 15) {
  1494. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1495. true, 14);
  1496. coex_dm->tdma_adj_type = 14;
  1497. } else if (coex_dm->cur_ps_tdma == 14) {
  1498. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1499. true, 13);
  1500. coex_dm->tdma_adj_type = 13;
  1501. }
  1502. }
  1503. } else {
  1504. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1505. "[BTCoex], TxPause = 0\n");
  1506. if (coex_dm->cur_ps_tdma == 5) {
  1507. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1508. true, 71);
  1509. coex_dm->tdma_adj_type = 71;
  1510. } else if (coex_dm->cur_ps_tdma == 6) {
  1511. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1512. true, 2);
  1513. coex_dm->tdma_adj_type = 2;
  1514. } else if (coex_dm->cur_ps_tdma == 7) {
  1515. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1516. true, 3);
  1517. coex_dm->tdma_adj_type = 3;
  1518. } else if (coex_dm->cur_ps_tdma == 8) {
  1519. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1520. true, 4);
  1521. coex_dm->tdma_adj_type = 4;
  1522. }
  1523. if (coex_dm->cur_ps_tdma == 13) {
  1524. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1525. true, 9);
  1526. coex_dm->tdma_adj_type = 9;
  1527. } else if (coex_dm->cur_ps_tdma == 14) {
  1528. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1529. true, 10);
  1530. coex_dm->tdma_adj_type = 10;
  1531. } else if (coex_dm->cur_ps_tdma == 15) {
  1532. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1533. true, 11);
  1534. coex_dm->tdma_adj_type = 11;
  1535. } else if (coex_dm->cur_ps_tdma == 16) {
  1536. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1537. true, 12);
  1538. coex_dm->tdma_adj_type = 12;
  1539. }
  1540. if (result == -1) {
  1541. if (coex_dm->cur_ps_tdma == 71) {
  1542. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1543. true, 1);
  1544. coex_dm->tdma_adj_type = 1;
  1545. } else if (coex_dm->cur_ps_tdma == 1) {
  1546. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1547. true, 2);
  1548. coex_dm->tdma_adj_type = 2;
  1549. } else if (coex_dm->cur_ps_tdma == 2) {
  1550. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1551. true, 3);
  1552. coex_dm->tdma_adj_type = 3;
  1553. } else if (coex_dm->cur_ps_tdma == 3) {
  1554. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1555. true, 4);
  1556. coex_dm->tdma_adj_type = 4;
  1557. } else if (coex_dm->cur_ps_tdma == 9) {
  1558. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1559. true, 10);
  1560. coex_dm->tdma_adj_type = 10;
  1561. } else if (coex_dm->cur_ps_tdma == 10) {
  1562. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1563. true, 11);
  1564. coex_dm->tdma_adj_type = 11;
  1565. } else if (coex_dm->cur_ps_tdma == 11) {
  1566. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1567. true, 12);
  1568. coex_dm->tdma_adj_type = 12;
  1569. }
  1570. } else if (result == 1) {
  1571. if (coex_dm->cur_ps_tdma == 4) {
  1572. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1573. true, 3);
  1574. coex_dm->tdma_adj_type = 3;
  1575. } else if (coex_dm->cur_ps_tdma == 3) {
  1576. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1577. true, 2);
  1578. coex_dm->tdma_adj_type = 2;
  1579. } else if (coex_dm->cur_ps_tdma == 2) {
  1580. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1581. true, 1);
  1582. coex_dm->tdma_adj_type = 1;
  1583. } else if (coex_dm->cur_ps_tdma == 1) {
  1584. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1585. true, 71);
  1586. coex_dm->tdma_adj_type = 71;
  1587. } else if (coex_dm->cur_ps_tdma == 12) {
  1588. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1589. true, 11);
  1590. coex_dm->tdma_adj_type = 11;
  1591. } else if (coex_dm->cur_ps_tdma == 11) {
  1592. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1593. true, 10);
  1594. coex_dm->tdma_adj_type = 10;
  1595. } else if (coex_dm->cur_ps_tdma == 10) {
  1596. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1597. true, 9);
  1598. coex_dm->tdma_adj_type = 9;
  1599. }
  1600. }
  1601. }
  1602. }
  1603. static void btc8192e_int2(struct btc_coexist *btcoexist, bool tx_pause,
  1604. int result)
  1605. {
  1606. if (tx_pause) {
  1607. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1608. "[BTCoex], TxPause = 1\n");
  1609. if (coex_dm->cur_ps_tdma == 1) {
  1610. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1611. true, 6);
  1612. coex_dm->tdma_adj_type = 6;
  1613. } else if (coex_dm->cur_ps_tdma == 2) {
  1614. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1615. true, 6);
  1616. coex_dm->tdma_adj_type = 6;
  1617. } else if (coex_dm->cur_ps_tdma == 3) {
  1618. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1619. true, 7);
  1620. coex_dm->tdma_adj_type = 7;
  1621. } else if (coex_dm->cur_ps_tdma == 4) {
  1622. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1623. true, 8);
  1624. coex_dm->tdma_adj_type = 8;
  1625. }
  1626. if (coex_dm->cur_ps_tdma == 9) {
  1627. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1628. true, 14);
  1629. coex_dm->tdma_adj_type = 14;
  1630. } else if (coex_dm->cur_ps_tdma == 10) {
  1631. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1632. true, 14);
  1633. coex_dm->tdma_adj_type = 14;
  1634. } else if (coex_dm->cur_ps_tdma == 11) {
  1635. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1636. true, 15);
  1637. coex_dm->tdma_adj_type = 15;
  1638. } else if (coex_dm->cur_ps_tdma == 12) {
  1639. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1640. true, 16);
  1641. coex_dm->tdma_adj_type = 16;
  1642. }
  1643. if (result == -1) {
  1644. if (coex_dm->cur_ps_tdma == 5) {
  1645. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1646. true, 6);
  1647. coex_dm->tdma_adj_type = 6;
  1648. } else if (coex_dm->cur_ps_tdma == 6) {
  1649. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1650. true, 7);
  1651. coex_dm->tdma_adj_type = 7;
  1652. } else if (coex_dm->cur_ps_tdma == 7) {
  1653. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1654. true, 8);
  1655. coex_dm->tdma_adj_type = 8;
  1656. } else if (coex_dm->cur_ps_tdma == 13) {
  1657. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1658. true, 14);
  1659. coex_dm->tdma_adj_type = 14;
  1660. } else if (coex_dm->cur_ps_tdma == 14) {
  1661. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1662. true, 15);
  1663. coex_dm->tdma_adj_type = 15;
  1664. } else if (coex_dm->cur_ps_tdma == 15) {
  1665. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1666. true, 16);
  1667. coex_dm->tdma_adj_type = 16;
  1668. }
  1669. } else if (result == 1) {
  1670. if (coex_dm->cur_ps_tdma == 8) {
  1671. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1672. true, 7);
  1673. coex_dm->tdma_adj_type = 7;
  1674. } else if (coex_dm->cur_ps_tdma == 7) {
  1675. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1676. true, 6);
  1677. coex_dm->tdma_adj_type = 6;
  1678. } else if (coex_dm->cur_ps_tdma == 6) {
  1679. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1680. true, 6);
  1681. coex_dm->tdma_adj_type = 6;
  1682. } else if (coex_dm->cur_ps_tdma == 16) {
  1683. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1684. true, 15);
  1685. coex_dm->tdma_adj_type = 15;
  1686. } else if (coex_dm->cur_ps_tdma == 15) {
  1687. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1688. true, 14);
  1689. coex_dm->tdma_adj_type = 14;
  1690. } else if (coex_dm->cur_ps_tdma == 14) {
  1691. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1692. true, 14);
  1693. coex_dm->tdma_adj_type = 14;
  1694. }
  1695. }
  1696. } else {
  1697. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1698. "[BTCoex], TxPause = 0\n");
  1699. if (coex_dm->cur_ps_tdma == 5) {
  1700. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1701. true, 2);
  1702. coex_dm->tdma_adj_type = 2;
  1703. } else if (coex_dm->cur_ps_tdma == 6) {
  1704. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1705. true, 2);
  1706. coex_dm->tdma_adj_type = 2;
  1707. } else if (coex_dm->cur_ps_tdma == 7) {
  1708. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1709. true, 3);
  1710. coex_dm->tdma_adj_type = 3;
  1711. } else if (coex_dm->cur_ps_tdma == 8) {
  1712. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1713. true, 4);
  1714. coex_dm->tdma_adj_type = 4;
  1715. }
  1716. if (coex_dm->cur_ps_tdma == 13) {
  1717. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1718. true, 10);
  1719. coex_dm->tdma_adj_type = 10;
  1720. } else if (coex_dm->cur_ps_tdma == 14) {
  1721. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1722. true, 10);
  1723. coex_dm->tdma_adj_type = 10;
  1724. } else if (coex_dm->cur_ps_tdma == 15) {
  1725. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1726. true, 11);
  1727. coex_dm->tdma_adj_type = 11;
  1728. } else if (coex_dm->cur_ps_tdma == 16) {
  1729. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1730. true, 12);
  1731. coex_dm->tdma_adj_type = 12;
  1732. }
  1733. if (result == -1) {
  1734. if (coex_dm->cur_ps_tdma == 1) {
  1735. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1736. true, 2);
  1737. coex_dm->tdma_adj_type = 2;
  1738. } else if (coex_dm->cur_ps_tdma == 2) {
  1739. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1740. true, 3);
  1741. coex_dm->tdma_adj_type = 3;
  1742. } else if (coex_dm->cur_ps_tdma == 3) {
  1743. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1744. true, 4);
  1745. coex_dm->tdma_adj_type = 4;
  1746. } else if (coex_dm->cur_ps_tdma == 9) {
  1747. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1748. true, 10);
  1749. coex_dm->tdma_adj_type = 10;
  1750. } else if (coex_dm->cur_ps_tdma == 10) {
  1751. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1752. true, 11);
  1753. coex_dm->tdma_adj_type = 11;
  1754. } else if (coex_dm->cur_ps_tdma == 11) {
  1755. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1756. true, 12);
  1757. coex_dm->tdma_adj_type = 12;
  1758. }
  1759. } else if (result == 1) {
  1760. if (coex_dm->cur_ps_tdma == 4) {
  1761. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1762. true, 3);
  1763. coex_dm->tdma_adj_type = 3;
  1764. } else if (coex_dm->cur_ps_tdma == 3) {
  1765. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1766. true, 2);
  1767. coex_dm->tdma_adj_type = 2;
  1768. } else if (coex_dm->cur_ps_tdma == 2) {
  1769. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1770. true, 2);
  1771. coex_dm->tdma_adj_type = 2;
  1772. } else if (coex_dm->cur_ps_tdma == 12) {
  1773. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1774. true, 11);
  1775. coex_dm->tdma_adj_type = 11;
  1776. } else if (coex_dm->cur_ps_tdma == 11) {
  1777. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1778. true, 10);
  1779. coex_dm->tdma_adj_type = 10;
  1780. } else if (coex_dm->cur_ps_tdma == 10) {
  1781. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1782. true, 10);
  1783. coex_dm->tdma_adj_type = 10;
  1784. }
  1785. }
  1786. }
  1787. }
  1788. static void btc8192e_int3(struct btc_coexist *btcoexist, bool tx_pause,
  1789. int result)
  1790. {
  1791. if (tx_pause) {
  1792. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1793. "[BTCoex], TxPause = 1\n");
  1794. if (coex_dm->cur_ps_tdma == 1) {
  1795. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1796. true, 7);
  1797. coex_dm->tdma_adj_type = 7;
  1798. } else if (coex_dm->cur_ps_tdma == 2) {
  1799. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1800. true, 7);
  1801. coex_dm->tdma_adj_type = 7;
  1802. } else if (coex_dm->cur_ps_tdma == 3) {
  1803. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1804. true, 7);
  1805. coex_dm->tdma_adj_type = 7;
  1806. } else if (coex_dm->cur_ps_tdma == 4) {
  1807. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1808. true, 8);
  1809. coex_dm->tdma_adj_type = 8;
  1810. }
  1811. if (coex_dm->cur_ps_tdma == 9) {
  1812. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1813. true, 15);
  1814. coex_dm->tdma_adj_type = 15;
  1815. } else if (coex_dm->cur_ps_tdma == 10) {
  1816. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1817. true, 15);
  1818. coex_dm->tdma_adj_type = 15;
  1819. } else if (coex_dm->cur_ps_tdma == 11) {
  1820. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1821. true, 15);
  1822. coex_dm->tdma_adj_type = 15;
  1823. } else if (coex_dm->cur_ps_tdma == 12) {
  1824. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1825. true, 16);
  1826. coex_dm->tdma_adj_type = 16;
  1827. }
  1828. if (result == -1) {
  1829. if (coex_dm->cur_ps_tdma == 5) {
  1830. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1831. true, 7);
  1832. coex_dm->tdma_adj_type = 7;
  1833. } else if (coex_dm->cur_ps_tdma == 6) {
  1834. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1835. true, 7);
  1836. coex_dm->tdma_adj_type = 7;
  1837. } else if (coex_dm->cur_ps_tdma == 7) {
  1838. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1839. true, 8);
  1840. coex_dm->tdma_adj_type = 8;
  1841. } else if (coex_dm->cur_ps_tdma == 13) {
  1842. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1843. true, 15);
  1844. coex_dm->tdma_adj_type = 15;
  1845. } else if (coex_dm->cur_ps_tdma == 14) {
  1846. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1847. true, 15);
  1848. coex_dm->tdma_adj_type = 15;
  1849. } else if (coex_dm->cur_ps_tdma == 15) {
  1850. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1851. true, 16);
  1852. coex_dm->tdma_adj_type = 16;
  1853. }
  1854. } else if (result == 1) {
  1855. if (coex_dm->cur_ps_tdma == 8) {
  1856. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1857. true, 7);
  1858. coex_dm->tdma_adj_type = 7;
  1859. } else if (coex_dm->cur_ps_tdma == 7) {
  1860. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1861. true, 7);
  1862. coex_dm->tdma_adj_type = 7;
  1863. } else if (coex_dm->cur_ps_tdma == 6) {
  1864. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1865. true, 7);
  1866. coex_dm->tdma_adj_type = 7;
  1867. } else if (coex_dm->cur_ps_tdma == 16) {
  1868. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1869. true, 15);
  1870. coex_dm->tdma_adj_type = 15;
  1871. } else if (coex_dm->cur_ps_tdma == 15) {
  1872. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1873. true, 15);
  1874. coex_dm->tdma_adj_type = 15;
  1875. } else if (coex_dm->cur_ps_tdma == 14) {
  1876. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1877. true, 15);
  1878. coex_dm->tdma_adj_type = 15;
  1879. }
  1880. }
  1881. } else {
  1882. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1883. "[BTCoex], TxPause = 0\n");
  1884. if (coex_dm->cur_ps_tdma == 5) {
  1885. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1886. true, 3);
  1887. coex_dm->tdma_adj_type = 3;
  1888. } else if (coex_dm->cur_ps_tdma == 6) {
  1889. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1890. true, 3);
  1891. coex_dm->tdma_adj_type = 3;
  1892. } else if (coex_dm->cur_ps_tdma == 7) {
  1893. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1894. true, 3);
  1895. coex_dm->tdma_adj_type = 3;
  1896. } else if (coex_dm->cur_ps_tdma == 8) {
  1897. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1898. true, 4);
  1899. coex_dm->tdma_adj_type = 4;
  1900. }
  1901. if (coex_dm->cur_ps_tdma == 13) {
  1902. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1903. true, 11);
  1904. coex_dm->tdma_adj_type = 11;
  1905. } else if (coex_dm->cur_ps_tdma == 14) {
  1906. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1907. true, 11);
  1908. coex_dm->tdma_adj_type = 11;
  1909. } else if (coex_dm->cur_ps_tdma == 15) {
  1910. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1911. true, 11);
  1912. coex_dm->tdma_adj_type = 11;
  1913. } else if (coex_dm->cur_ps_tdma == 16) {
  1914. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1915. true, 12);
  1916. coex_dm->tdma_adj_type = 12;
  1917. }
  1918. if (result == -1) {
  1919. if (coex_dm->cur_ps_tdma == 1) {
  1920. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1921. true, 3);
  1922. coex_dm->tdma_adj_type = 3;
  1923. } else if (coex_dm->cur_ps_tdma == 2) {
  1924. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1925. true, 3);
  1926. coex_dm->tdma_adj_type = 3;
  1927. } else if (coex_dm->cur_ps_tdma == 3) {
  1928. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1929. true, 4);
  1930. coex_dm->tdma_adj_type = 4;
  1931. } else if (coex_dm->cur_ps_tdma == 9) {
  1932. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1933. true, 11);
  1934. coex_dm->tdma_adj_type = 11;
  1935. } else if (coex_dm->cur_ps_tdma == 10) {
  1936. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1937. true, 11);
  1938. coex_dm->tdma_adj_type = 11;
  1939. } else if (coex_dm->cur_ps_tdma == 11) {
  1940. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1941. true, 12);
  1942. coex_dm->tdma_adj_type = 12;
  1943. }
  1944. } else if (result == 1) {
  1945. if (coex_dm->cur_ps_tdma == 4) {
  1946. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1947. true, 3);
  1948. coex_dm->tdma_adj_type = 3;
  1949. } else if (coex_dm->cur_ps_tdma == 3) {
  1950. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1951. true, 3);
  1952. coex_dm->tdma_adj_type = 3;
  1953. } else if (coex_dm->cur_ps_tdma == 2) {
  1954. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1955. true, 3);
  1956. coex_dm->tdma_adj_type = 3;
  1957. } else if (coex_dm->cur_ps_tdma == 12) {
  1958. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1959. true, 11);
  1960. coex_dm->tdma_adj_type = 11;
  1961. } else if (coex_dm->cur_ps_tdma == 11) {
  1962. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1963. true, 11);
  1964. coex_dm->tdma_adj_type = 11;
  1965. } else if (coex_dm->cur_ps_tdma == 10) {
  1966. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1967. true, 11);
  1968. coex_dm->tdma_adj_type = 11;
  1969. }
  1970. }
  1971. }
  1972. }
  1973. static void halbtc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
  1974. bool sco_hid, bool tx_pause,
  1975. u8 max_interval)
  1976. {
  1977. static int up, dn, m, n, wait_cnt;
  1978. /* 0: no change, +1: increase WiFi duration,
  1979. * -1: decrease WiFi duration
  1980. */
  1981. int result;
  1982. u8 retry_cnt = 0;
  1983. btc_alg_dbg(ALGO_TRACE_FW,
  1984. "[BTCoex], TdmaDurationAdjust()\n");
  1985. if (!coex_dm->auto_tdma_adjust) {
  1986. coex_dm->auto_tdma_adjust = true;
  1987. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  1988. "[BTCoex], first run TdmaDurationAdjust()!!\n");
  1989. if (sco_hid) {
  1990. if (tx_pause) {
  1991. if (max_interval == 1) {
  1992. halbtc8192e2ant_ps_tdma(btcoexist,
  1993. NORMAL_EXEC,
  1994. true, 13);
  1995. coex_dm->tdma_adj_type = 13;
  1996. } else if (max_interval == 2) {
  1997. halbtc8192e2ant_ps_tdma(btcoexist,
  1998. NORMAL_EXEC,
  1999. true, 14);
  2000. coex_dm->tdma_adj_type = 14;
  2001. } else if (max_interval == 3) {
  2002. halbtc8192e2ant_ps_tdma(btcoexist,
  2003. NORMAL_EXEC,
  2004. true, 15);
  2005. coex_dm->tdma_adj_type = 15;
  2006. } else {
  2007. halbtc8192e2ant_ps_tdma(btcoexist,
  2008. NORMAL_EXEC,
  2009. true, 15);
  2010. coex_dm->tdma_adj_type = 15;
  2011. }
  2012. } else {
  2013. if (max_interval == 1) {
  2014. halbtc8192e2ant_ps_tdma(btcoexist,
  2015. NORMAL_EXEC,
  2016. true, 9);
  2017. coex_dm->tdma_adj_type = 9;
  2018. } else if (max_interval == 2) {
  2019. halbtc8192e2ant_ps_tdma(btcoexist,
  2020. NORMAL_EXEC,
  2021. true, 10);
  2022. coex_dm->tdma_adj_type = 10;
  2023. } else if (max_interval == 3) {
  2024. halbtc8192e2ant_ps_tdma(btcoexist,
  2025. NORMAL_EXEC,
  2026. true, 11);
  2027. coex_dm->tdma_adj_type = 11;
  2028. } else {
  2029. halbtc8192e2ant_ps_tdma(btcoexist,
  2030. NORMAL_EXEC,
  2031. true, 11);
  2032. coex_dm->tdma_adj_type = 11;
  2033. }
  2034. }
  2035. } else {
  2036. if (tx_pause) {
  2037. if (max_interval == 1) {
  2038. halbtc8192e2ant_ps_tdma(btcoexist,
  2039. NORMAL_EXEC,
  2040. true, 5);
  2041. coex_dm->tdma_adj_type = 5;
  2042. } else if (max_interval == 2) {
  2043. halbtc8192e2ant_ps_tdma(btcoexist,
  2044. NORMAL_EXEC,
  2045. true, 6);
  2046. coex_dm->tdma_adj_type = 6;
  2047. } else if (max_interval == 3) {
  2048. halbtc8192e2ant_ps_tdma(btcoexist,
  2049. NORMAL_EXEC,
  2050. true, 7);
  2051. coex_dm->tdma_adj_type = 7;
  2052. } else {
  2053. halbtc8192e2ant_ps_tdma(btcoexist,
  2054. NORMAL_EXEC,
  2055. true, 7);
  2056. coex_dm->tdma_adj_type = 7;
  2057. }
  2058. } else {
  2059. if (max_interval == 1) {
  2060. halbtc8192e2ant_ps_tdma(btcoexist,
  2061. NORMAL_EXEC,
  2062. true, 1);
  2063. coex_dm->tdma_adj_type = 1;
  2064. } else if (max_interval == 2) {
  2065. halbtc8192e2ant_ps_tdma(btcoexist,
  2066. NORMAL_EXEC,
  2067. true, 2);
  2068. coex_dm->tdma_adj_type = 2;
  2069. } else if (max_interval == 3) {
  2070. halbtc8192e2ant_ps_tdma(btcoexist,
  2071. NORMAL_EXEC,
  2072. true, 3);
  2073. coex_dm->tdma_adj_type = 3;
  2074. } else {
  2075. halbtc8192e2ant_ps_tdma(btcoexist,
  2076. NORMAL_EXEC,
  2077. true, 3);
  2078. coex_dm->tdma_adj_type = 3;
  2079. }
  2080. }
  2081. }
  2082. up = 0;
  2083. dn = 0;
  2084. m = 1;
  2085. n = 3;
  2086. result = 0;
  2087. wait_cnt = 0;
  2088. } else {
  2089. /* accquire the BT TRx retry count from BT_Info byte2 */
  2090. retry_cnt = coex_sta->bt_retry_cnt;
  2091. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2092. "[BTCoex], retry_cnt = %d\n", retry_cnt);
  2093. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2094. "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n",
  2095. up, dn, m, n, wait_cnt);
  2096. result = 0;
  2097. wait_cnt++;
  2098. /* no retry in the last 2-second duration */
  2099. if (retry_cnt == 0) {
  2100. up++;
  2101. dn--;
  2102. if (dn <= 0)
  2103. dn = 0;
  2104. if (up >= n) {
  2105. wait_cnt = 0;
  2106. n = 3;
  2107. up = 0;
  2108. dn = 0;
  2109. result = 1;
  2110. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2111. "[BTCoex]Increase wifi duration!!\n");
  2112. }
  2113. } else if (retry_cnt <= 3) {
  2114. up--;
  2115. dn++;
  2116. if (up <= 0)
  2117. up = 0;
  2118. if (dn == 2) {
  2119. if (wait_cnt <= 2)
  2120. m++;
  2121. else
  2122. m = 1;
  2123. if (m >= 20)
  2124. m = 20;
  2125. n = 3 * m;
  2126. up = 0;
  2127. dn = 0;
  2128. wait_cnt = 0;
  2129. result = -1;
  2130. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2131. "Reduce wifi duration for retry<3\n");
  2132. }
  2133. } else {
  2134. if (wait_cnt == 1)
  2135. m++;
  2136. else
  2137. m = 1;
  2138. if (m >= 20)
  2139. m = 20;
  2140. n = 3*m;
  2141. up = 0;
  2142. dn = 0;
  2143. wait_cnt = 0;
  2144. result = -1;
  2145. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2146. "Decrease wifi duration for retryCounter>3!!\n");
  2147. }
  2148. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2149. "[BTCoex], max Interval = %d\n", max_interval);
  2150. if (max_interval == 1)
  2151. btc8192e_int1(btcoexist, tx_pause, result);
  2152. else if (max_interval == 2)
  2153. btc8192e_int2(btcoexist, tx_pause, result);
  2154. else if (max_interval == 3)
  2155. btc8192e_int3(btcoexist, tx_pause, result);
  2156. }
  2157. /* if current PsTdma not match with
  2158. * the recorded one (when scan, dhcp...),
  2159. * then we have to adjust it back to the previous record one.
  2160. */
  2161. if (coex_dm->cur_ps_tdma != coex_dm->tdma_adj_type) {
  2162. bool scan = false, link = false, roam = false;
  2163. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2164. "[BTCoex], PsTdma type dismatch!!!, ");
  2165. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2166. "curPsTdma=%d, recordPsTdma=%d\n",
  2167. coex_dm->cur_ps_tdma, coex_dm->tdma_adj_type);
  2168. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  2169. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  2170. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  2171. if (!scan && !link && !roam)
  2172. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  2173. true,
  2174. coex_dm->tdma_adj_type);
  2175. else
  2176. btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
  2177. "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
  2178. }
  2179. }
  2180. /* SCO only or SCO+PAN(HS) */
  2181. static void halbtc8192e2ant_action_sco(struct btc_coexist *btcoexist)
  2182. {
  2183. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
  2184. u32 wifi_bw;
  2185. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2186. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2187. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2188. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2189. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4);
  2190. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2191. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2192. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2193. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2194. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  2195. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2196. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2197. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2198. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  2199. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2200. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2201. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2202. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  2203. }
  2204. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2205. /* sw mechanism */
  2206. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2207. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2208. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2209. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2210. false, false);
  2211. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2212. false, 0x6);
  2213. } else {
  2214. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2215. false, false);
  2216. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2217. false, 0x6);
  2218. }
  2219. } else {
  2220. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2221. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2222. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2223. false, false);
  2224. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2225. false, 0x6);
  2226. } else {
  2227. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2228. false, false);
  2229. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2230. false, 0x6);
  2231. }
  2232. }
  2233. }
  2234. static void halbtc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist)
  2235. {
  2236. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
  2237. u32 wifi_bw;
  2238. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2239. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2240. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2241. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2242. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4);
  2243. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2244. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2245. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2246. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2247. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  2248. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2249. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2250. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2251. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  2252. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2253. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2254. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2255. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  2256. }
  2257. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2258. /* sw mechanism */
  2259. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2260. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2261. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2262. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2263. false, false);
  2264. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2265. false, 0x6);
  2266. } else {
  2267. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2268. false, false);
  2269. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2270. false, 0x6);
  2271. }
  2272. } else {
  2273. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2274. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2275. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2276. false, false);
  2277. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2278. false, 0x6);
  2279. } else {
  2280. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2281. false, false);
  2282. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2283. false, 0x6);
  2284. }
  2285. }
  2286. }
  2287. static void halbtc8192e2ant_action_hid(struct btc_coexist *btcoexist)
  2288. {
  2289. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2290. u32 wifi_bw;
  2291. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2292. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2293. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2294. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2295. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2296. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2297. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
  2298. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2299. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2300. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2301. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  2302. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2303. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2304. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2305. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  2306. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2307. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2308. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2309. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  2310. }
  2311. /* sw mechanism */
  2312. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2313. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2314. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2315. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2316. false, false);
  2317. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2318. false, 0x18);
  2319. } else {
  2320. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2321. false, false);
  2322. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2323. false, 0x18);
  2324. }
  2325. } else {
  2326. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2327. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2328. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2329. false, false);
  2330. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2331. false, 0x18);
  2332. } else {
  2333. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2334. false, false);
  2335. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2336. false, 0x18);
  2337. }
  2338. }
  2339. }
  2340. /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
  2341. static void halbtc8192e2ant_action_a2dp(struct btc_coexist *btcoexist)
  2342. {
  2343. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2344. u32 wifi_bw;
  2345. bool long_dist = false;
  2346. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2347. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2348. if ((btrssi_state == BTC_RSSI_STATE_LOW ||
  2349. btrssi_state == BTC_RSSI_STATE_STAY_LOW) &&
  2350. (wifirssi_state == BTC_RSSI_STATE_LOW ||
  2351. wifirssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2352. btc_alg_dbg(ALGO_TRACE,
  2353. "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
  2354. long_dist = true;
  2355. }
  2356. if (long_dist) {
  2357. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 2);
  2358. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
  2359. 0x4);
  2360. } else {
  2361. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2362. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
  2363. 0x8);
  2364. }
  2365. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2366. if (long_dist)
  2367. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0);
  2368. else
  2369. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  2370. if (long_dist) {
  2371. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
  2372. coex_dm->auto_tdma_adjust = false;
  2373. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2374. } else {
  2375. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2376. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2377. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2378. true, 1);
  2379. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2380. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2381. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2382. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2383. false, 1);
  2384. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2385. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2386. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2387. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2388. false, 1);
  2389. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2390. }
  2391. }
  2392. /* sw mechanism */
  2393. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2394. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2395. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2396. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2397. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2398. false, false);
  2399. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2400. false, 0x18);
  2401. } else {
  2402. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2403. false, false);
  2404. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2405. false, 0x18);
  2406. }
  2407. } else {
  2408. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2409. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2410. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2411. false, false);
  2412. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2413. false, 0x18);
  2414. } else {
  2415. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2416. false, false);
  2417. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2418. false, 0x18);
  2419. }
  2420. }
  2421. }
  2422. static void halbtc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
  2423. {
  2424. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2425. u32 wifi_bw;
  2426. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2427. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2428. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2429. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2430. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2431. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  2432. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2433. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2434. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
  2435. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2436. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2437. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2438. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2439. false, 2);
  2440. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2441. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2442. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2443. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2444. false, 2);
  2445. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2446. }
  2447. /* sw mechanism */
  2448. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2449. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2450. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2451. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2452. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2453. false, false);
  2454. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2455. true, 0x6);
  2456. } else {
  2457. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2458. false, false);
  2459. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2460. true, 0x6);
  2461. }
  2462. } else {
  2463. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2464. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2465. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2466. false, false);
  2467. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2468. true, 0x6);
  2469. } else {
  2470. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2471. false, false);
  2472. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2473. true, 0x6);
  2474. }
  2475. }
  2476. }
  2477. static void halbtc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist)
  2478. {
  2479. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2480. u32 wifi_bw;
  2481. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2482. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2483. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2484. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2485. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2486. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  2487. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2488. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2489. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2490. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
  2491. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2492. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2493. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2494. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  2495. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2496. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2497. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2498. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  2499. }
  2500. /* sw mechanism */
  2501. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2502. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2503. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2504. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2505. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2506. false, false);
  2507. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2508. false, 0x18);
  2509. } else {
  2510. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2511. false, false);
  2512. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2513. false, 0x18);
  2514. }
  2515. } else {
  2516. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2517. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2518. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2519. false, false);
  2520. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2521. false, 0x18);
  2522. } else {
  2523. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2524. false, false);
  2525. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2526. false, 0x18);
  2527. }
  2528. }
  2529. }
  2530. /* PAN(HS) only */
  2531. static void halbtc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist)
  2532. {
  2533. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2534. u32 wifi_bw;
  2535. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2536. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2537. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2538. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2539. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2540. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  2541. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2542. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2543. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2544. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2545. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2546. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2547. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2548. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2549. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2550. }
  2551. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  2552. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2553. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2554. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2555. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2556. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2557. false, false);
  2558. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2559. false, 0x18);
  2560. } else {
  2561. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2562. false, false);
  2563. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2564. false, 0x18);
  2565. }
  2566. } else {
  2567. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2568. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2569. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2570. false, false);
  2571. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2572. false, 0x18);
  2573. } else {
  2574. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2575. false, false);
  2576. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2577. false, 0x18);
  2578. }
  2579. }
  2580. }
  2581. /* PAN(EDR)+A2DP */
  2582. static void halbtc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
  2583. {
  2584. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2585. u32 wifi_bw;
  2586. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2587. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2588. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2589. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2590. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2591. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
  2592. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2593. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2594. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2595. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2596. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
  2597. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2598. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2599. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2600. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2601. false, 3);
  2602. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2603. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2604. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2605. halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
  2606. false, 3);
  2607. }
  2608. /* sw mechanism */
  2609. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2610. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2611. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2612. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2613. false, false);
  2614. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2615. false, 0x18);
  2616. } else {
  2617. btc8192e2ant_sw_mec1(btcoexist, true, false,
  2618. false, false);
  2619. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2620. false, 0x18);
  2621. }
  2622. } else {
  2623. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2624. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2625. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2626. false, false);
  2627. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2628. false, 0x18);
  2629. } else {
  2630. btc8192e2ant_sw_mec1(btcoexist, false, false,
  2631. false, false);
  2632. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2633. false, 0x18);
  2634. }
  2635. }
  2636. }
  2637. static void halbtc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
  2638. {
  2639. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2640. u32 wifi_bw;
  2641. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2642. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2643. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2644. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2645. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2646. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2647. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
  2648. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2649. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2650. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2651. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  2652. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2653. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2654. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2655. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  2656. true, 10);
  2657. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2658. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2659. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2660. halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  2661. true, 10);
  2662. }
  2663. /* sw mechanism */
  2664. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2665. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2666. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2667. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2668. false, false);
  2669. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2670. false, 0x18);
  2671. } else {
  2672. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2673. false, false);
  2674. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2675. false, 0x18);
  2676. }
  2677. } else {
  2678. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2679. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2680. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2681. false, false);
  2682. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2683. false, 0x18);
  2684. } else {
  2685. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2686. false, false);
  2687. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2688. false, 0x18);
  2689. }
  2690. }
  2691. }
  2692. /* HID+A2DP+PAN(EDR) */
  2693. static void btc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
  2694. {
  2695. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2696. u32 wifi_bw;
  2697. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2698. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2699. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2700. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2701. halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
  2702. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2703. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
  2704. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2705. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2706. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2707. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
  2708. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2709. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2710. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2711. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2712. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2713. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2714. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2715. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2716. }
  2717. /* sw mechanism */
  2718. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2719. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2720. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2721. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2722. false, false);
  2723. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2724. false, 0x18);
  2725. } else {
  2726. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2727. false, false);
  2728. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2729. false, 0x18);
  2730. }
  2731. } else {
  2732. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2733. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2734. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2735. false, false);
  2736. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2737. false, 0x18);
  2738. } else {
  2739. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2740. false, false);
  2741. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2742. false, 0x18);
  2743. }
  2744. }
  2745. }
  2746. static void halbtc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
  2747. {
  2748. u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
  2749. u32 wifi_bw;
  2750. wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
  2751. btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
  2752. halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
  2753. halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2754. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2755. btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
  2756. if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
  2757. (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2758. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
  2759. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
  2760. } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2761. (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2762. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
  2763. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2764. } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
  2765. (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2766. halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
  2767. halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2768. }
  2769. /* sw mechanism */
  2770. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2771. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2772. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2773. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2774. false, false);
  2775. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2776. false, 0x18);
  2777. } else {
  2778. btc8192e2ant_sw_mec1(btcoexist, true, true,
  2779. false, false);
  2780. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2781. false, 0x18);
  2782. }
  2783. } else {
  2784. if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
  2785. (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2786. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2787. false, false);
  2788. btc8192e2ant_sw_mec2(btcoexist, true, false,
  2789. false, 0x18);
  2790. } else {
  2791. btc8192e2ant_sw_mec1(btcoexist, false, true,
  2792. false, false);
  2793. btc8192e2ant_sw_mec2(btcoexist, false, false,
  2794. false, 0x18);
  2795. }
  2796. }
  2797. }
  2798. static void halbtc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
  2799. {
  2800. u8 algorithm = 0;
  2801. btc_alg_dbg(ALGO_TRACE,
  2802. "[BTCoex], RunCoexistMechanism()===>\n");
  2803. if (btcoexist->manual_control) {
  2804. btc_alg_dbg(ALGO_TRACE,
  2805. "[BTCoex], return for Manual CTRL <===\n");
  2806. return;
  2807. }
  2808. if (coex_sta->under_ips) {
  2809. btc_alg_dbg(ALGO_TRACE,
  2810. "[BTCoex], wifi is under IPS !!!\n");
  2811. return;
  2812. }
  2813. algorithm = halbtc8192e2ant_action_algorithm(btcoexist);
  2814. if (coex_sta->c2h_bt_inquiry_page &&
  2815. (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
  2816. btc_alg_dbg(ALGO_TRACE,
  2817. "[BTCoex], BT is under inquiry/page scan !!\n");
  2818. halbtc8192e2ant_action_bt_inquiry(btcoexist);
  2819. return;
  2820. }
  2821. coex_dm->cur_algorithm = algorithm;
  2822. btc_alg_dbg(ALGO_TRACE,
  2823. "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
  2824. if (halbtc8192e2ant_is_common_action(btcoexist)) {
  2825. btc_alg_dbg(ALGO_TRACE,
  2826. "[BTCoex], Action 2-Ant common\n");
  2827. coex_dm->auto_tdma_adjust = false;
  2828. } else {
  2829. if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
  2830. btc_alg_dbg(ALGO_TRACE,
  2831. "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n",
  2832. coex_dm->pre_algorithm,
  2833. coex_dm->cur_algorithm);
  2834. coex_dm->auto_tdma_adjust = false;
  2835. }
  2836. switch (coex_dm->cur_algorithm) {
  2837. case BT_8192E_2ANT_COEX_ALGO_SCO:
  2838. btc_alg_dbg(ALGO_TRACE,
  2839. "Action 2-Ant, algorithm = SCO\n");
  2840. halbtc8192e2ant_action_sco(btcoexist);
  2841. break;
  2842. case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
  2843. btc_alg_dbg(ALGO_TRACE,
  2844. "Action 2-Ant, algorithm = SCO+PAN(EDR)\n");
  2845. halbtc8192e2ant_action_sco_pan(btcoexist);
  2846. break;
  2847. case BT_8192E_2ANT_COEX_ALGO_HID:
  2848. btc_alg_dbg(ALGO_TRACE,
  2849. "Action 2-Ant, algorithm = HID\n");
  2850. halbtc8192e2ant_action_hid(btcoexist);
  2851. break;
  2852. case BT_8192E_2ANT_COEX_ALGO_A2DP:
  2853. btc_alg_dbg(ALGO_TRACE,
  2854. "Action 2-Ant, algorithm = A2DP\n");
  2855. halbtc8192e2ant_action_a2dp(btcoexist);
  2856. break;
  2857. case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
  2858. btc_alg_dbg(ALGO_TRACE,
  2859. "Action 2-Ant, algorithm = A2DP+PAN(HS)\n");
  2860. halbtc8192e2ant_action_a2dp_pan_hs(btcoexist);
  2861. break;
  2862. case BT_8192E_2ANT_COEX_ALGO_PANEDR:
  2863. btc_alg_dbg(ALGO_TRACE,
  2864. "Action 2-Ant, algorithm = PAN(EDR)\n");
  2865. halbtc8192e2ant_action_pan_edr(btcoexist);
  2866. break;
  2867. case BT_8192E_2ANT_COEX_ALGO_PANHS:
  2868. btc_alg_dbg(ALGO_TRACE,
  2869. "Action 2-Ant, algorithm = HS mode\n");
  2870. halbtc8192e2ant_action_pan_hs(btcoexist);
  2871. break;
  2872. case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
  2873. btc_alg_dbg(ALGO_TRACE,
  2874. "Action 2-Ant, algorithm = PAN+A2DP\n");
  2875. halbtc8192e2ant_action_pan_edr_a2dp(btcoexist);
  2876. break;
  2877. case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
  2878. btc_alg_dbg(ALGO_TRACE,
  2879. "Action 2-Ant, algorithm = PAN(EDR)+HID\n");
  2880. halbtc8192e2ant_action_pan_edr_hid(btcoexist);
  2881. break;
  2882. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
  2883. btc_alg_dbg(ALGO_TRACE,
  2884. "Action 2-Ant, algorithm = HID+A2DP+PAN\n");
  2885. btc8192e2ant_action_hid_a2dp_pan_edr(btcoexist);
  2886. break;
  2887. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
  2888. btc_alg_dbg(ALGO_TRACE,
  2889. "Action 2-Ant, algorithm = HID+A2DP\n");
  2890. halbtc8192e2ant_action_hid_a2dp(btcoexist);
  2891. break;
  2892. default:
  2893. btc_alg_dbg(ALGO_TRACE,
  2894. "Action 2-Ant, algorithm = unknown!!\n");
  2895. /* halbtc8192e2ant_coex_alloff(btcoexist); */
  2896. break;
  2897. }
  2898. coex_dm->pre_algorithm = coex_dm->cur_algorithm;
  2899. }
  2900. }
  2901. static void halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist,
  2902. bool backup)
  2903. {
  2904. u16 u16tmp = 0;
  2905. u8 u8tmp = 0;
  2906. btc_iface_dbg(INTF_INIT,
  2907. "[BTCoex], 2Ant Init HW Config!!\n");
  2908. if (backup) {
  2909. /* backup rf 0x1e value */
  2910. coex_dm->bt_rf0x1e_backup =
  2911. btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A,
  2912. 0x1e, 0xfffff);
  2913. coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
  2914. 0x430);
  2915. coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
  2916. 0x434);
  2917. coex_dm->backup_retrylimit = btcoexist->btc_read_2byte(
  2918. btcoexist,
  2919. 0x42a);
  2920. coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte(
  2921. btcoexist,
  2922. 0x456);
  2923. }
  2924. /* antenna sw ctrl to bt */
  2925. btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6);
  2926. btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
  2927. btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
  2928. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  2929. if (btcoexist->chip_interface == BTC_INTF_USB)
  2930. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
  2931. else
  2932. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
  2933. btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0);
  2934. /* antenna switch control parameter */
  2935. btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
  2936. /* coex parameters */
  2937. btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
  2938. /* 0x790[5:0] = 0x5 */
  2939. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
  2940. u8tmp &= 0xc0;
  2941. u8tmp |= 0x5;
  2942. btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
  2943. /* enable counter statistics */
  2944. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
  2945. /* enable PTA */
  2946. btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
  2947. /* enable mailbox interface */
  2948. u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
  2949. u16tmp |= BIT9;
  2950. btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
  2951. /* enable PTA I2C mailbox */
  2952. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
  2953. u8tmp |= BIT4;
  2954. btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
  2955. /* enable bt clock when wifi is disabled. */
  2956. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
  2957. u8tmp |= BIT0;
  2958. btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
  2959. /* enable bt clock when suspend. */
  2960. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
  2961. u8tmp |= BIT0;
  2962. btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
  2963. }
  2964. /*************************************************************
  2965. * work around function start with wa_halbtc8192e2ant_
  2966. *************************************************************/
  2967. /************************************************************
  2968. * extern function start with EXhalbtc8192e2ant_
  2969. ************************************************************/
  2970. void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist)
  2971. {
  2972. halbtc8192e2ant_init_hwconfig(btcoexist, true);
  2973. }
  2974. void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  2975. {
  2976. btc_iface_dbg(INTF_INIT,
  2977. "[BTCoex], Coex Mechanism Init!!\n");
  2978. halbtc8192e2ant_init_coex_dm(btcoexist);
  2979. }
  2980. void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist)
  2981. {
  2982. struct btc_board_info *board_info = &btcoexist->board_info;
  2983. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  2984. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2985. u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
  2986. u16 u16tmp[4];
  2987. u32 u32tmp[4];
  2988. bool roam = false, scan = false, link = false, wifi_under_5g = false;
  2989. bool bt_hson = false, wifi_busy = false;
  2990. int wifirssi = 0, bt_hs_rssi = 0;
  2991. u32 wifi_bw, wifi_traffic_dir;
  2992. u8 wifi_dot11_chnl, wifi_hs_chnl;
  2993. u32 fw_ver = 0, bt_patch_ver = 0;
  2994. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2995. "\r\n ============[BT Coexist info]============");
  2996. if (btcoexist->manual_control) {
  2997. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2998. "\r\n ===========[Under Manual Control]===========");
  2999. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3000. "\r\n ==========================================");
  3001. }
  3002. if (!board_info->bt_exist) {
  3003. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n BT not exists !!!");
  3004. return;
  3005. }
  3006. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3007. "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:",
  3008. board_info->pg_ant_num, board_info->btdm_ant_num);
  3009. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %d",
  3010. "BT stack/ hci ext ver",
  3011. ((stack_info->profile_notified) ? "Yes" : "No"),
  3012. stack_info->hci_version);
  3013. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
  3014. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  3015. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3016. "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
  3017. "CoexVer/ FwVer/ PatchVer",
  3018. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  3019. fw_ver, bt_patch_ver, bt_patch_ver);
  3020. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
  3021. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
  3022. &wifi_dot11_chnl);
  3023. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
  3024. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d(%d)",
  3025. "Dot11 channel / HsMode(HsChnl)",
  3026. wifi_dot11_chnl, bt_hson, wifi_hs_chnl);
  3027. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %3ph ",
  3028. "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info);
  3029. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
  3030. btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
  3031. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  3032. "Wifi rssi/ HS rssi", wifirssi, bt_hs_rssi);
  3033. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  3034. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  3035. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  3036. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
  3037. "Wifi link/ roam/ scan", link, roam, scan);
  3038. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
  3039. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  3040. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  3041. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
  3042. &wifi_traffic_dir);
  3043. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %s/ %s ",
  3044. "Wifi status", (wifi_under_5g ? "5G" : "2.4G"),
  3045. ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" :
  3046. (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))),
  3047. ((!wifi_busy) ? "idle" :
  3048. ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ?
  3049. "uplink" : "downlink")));
  3050. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = [%s/ %d/ %d] ",
  3051. "BT [status/ rssi/ retryCnt]",
  3052. ((btcoexist->bt_info.bt_disabled) ? ("disabled") :
  3053. ((coex_sta->c2h_bt_inquiry_page) ?
  3054. ("inquiry/page scan") :
  3055. ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  3056. coex_dm->bt_status) ? "non-connected idle" :
  3057. ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  3058. coex_dm->bt_status) ? "connected-idle" : "busy")))),
  3059. coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
  3060. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d / %d / %d",
  3061. "SCO/HID/PAN/A2DP", stack_info->sco_exist,
  3062. stack_info->hid_exist, stack_info->pan_exist,
  3063. stack_info->a2dp_exist);
  3064. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
  3065. bt_info_ext = coex_sta->bt_info_ext;
  3066. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s",
  3067. "BT Info A2DP rate",
  3068. (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
  3069. for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
  3070. if (coex_sta->bt_info_c2h_cnt[i]) {
  3071. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3072. "\r\n %-35s = %7ph(%d)",
  3073. GLBtInfoSrc8192e2Ant[i],
  3074. coex_sta->bt_info_c2h[i],
  3075. coex_sta->bt_info_c2h_cnt[i]);
  3076. }
  3077. }
  3078. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s/%s",
  3079. "PS state, IPS/LPS",
  3080. ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")),
  3081. ((coex_sta->under_lps ? "LPS ON" : "LPS OFF")));
  3082. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
  3083. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "SS Type",
  3084. coex_dm->cur_sstype);
  3085. /* Sw mechanism */
  3086. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  3087. "============[Sw mechanism]============");
  3088. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
  3089. "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
  3090. coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
  3091. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
  3092. "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
  3093. coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
  3094. coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
  3095. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "Rate Mask",
  3096. btcoexist->bt_info.ra_mask);
  3097. /* Fw mechanism */
  3098. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  3099. "============[Fw mechanism]============");
  3100. ps_tdma_case = coex_dm->cur_ps_tdma;
  3101. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3102. "\r\n %-35s = %5ph case-%d (auto:%d)",
  3103. "PS TDMA", coex_dm->ps_tdma_para,
  3104. ps_tdma_case, coex_dm->auto_tdma_adjust);
  3105. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d ",
  3106. "DecBtPwr/ IgnWlanAct",
  3107. coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
  3108. /* Hw setting */
  3109. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  3110. "============[Hw setting]============");
  3111. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x",
  3112. "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
  3113. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  3114. "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
  3115. coex_dm->backup_arfr_cnt2, coex_dm->backup_retrylimit,
  3116. coex_dm->backup_ampdu_maxtime);
  3117. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
  3118. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
  3119. u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
  3120. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
  3121. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  3122. "0x430/0x434/0x42a/0x456",
  3123. u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
  3124. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
  3125. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
  3126. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
  3127. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
  3128. "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]);
  3129. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
  3130. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0x778",
  3131. u8tmp[0]);
  3132. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
  3133. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
  3134. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  3135. "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]);
  3136. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
  3137. u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
  3138. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  3139. "0x40/ 0x4f", u8tmp[0], u8tmp[1]);
  3140. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
  3141. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
  3142. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  3143. "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
  3144. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
  3145. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0xc50(dig)",
  3146. u32tmp[0]);
  3147. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
  3148. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
  3149. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
  3150. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
  3151. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  3152. "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
  3153. "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
  3154. u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
  3155. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  3156. "0x770(hp rx[31:16]/tx[15:0])",
  3157. coex_sta->high_priority_rx, coex_sta->high_priority_tx);
  3158. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  3159. "0x774(lp rx[31:16]/tx[15:0])",
  3160. coex_sta->low_priority_rx, coex_sta->low_priority_tx);
  3161. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
  3162. halbtc8192e2ant_monitor_bt_ctr(btcoexist);
  3163. #endif
  3164. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
  3165. }
  3166. void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
  3167. {
  3168. if (BTC_IPS_ENTER == type) {
  3169. btc_iface_dbg(INTF_NOTIFY,
  3170. "[BTCoex], IPS ENTER notify\n");
  3171. coex_sta->under_ips = true;
  3172. halbtc8192e2ant_coex_alloff(btcoexist);
  3173. } else if (BTC_IPS_LEAVE == type) {
  3174. btc_iface_dbg(INTF_NOTIFY,
  3175. "[BTCoex], IPS LEAVE notify\n");
  3176. coex_sta->under_ips = false;
  3177. }
  3178. }
  3179. void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
  3180. {
  3181. if (BTC_LPS_ENABLE == type) {
  3182. btc_iface_dbg(INTF_NOTIFY,
  3183. "[BTCoex], LPS ENABLE notify\n");
  3184. coex_sta->under_lps = true;
  3185. } else if (BTC_LPS_DISABLE == type) {
  3186. btc_iface_dbg(INTF_NOTIFY,
  3187. "[BTCoex], LPS DISABLE notify\n");
  3188. coex_sta->under_lps = false;
  3189. }
  3190. }
  3191. void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
  3192. {
  3193. if (BTC_SCAN_START == type)
  3194. btc_iface_dbg(INTF_NOTIFY,
  3195. "[BTCoex], SCAN START notify\n");
  3196. else if (BTC_SCAN_FINISH == type)
  3197. btc_iface_dbg(INTF_NOTIFY,
  3198. "[BTCoex], SCAN FINISH notify\n");
  3199. }
  3200. void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
  3201. {
  3202. if (BTC_ASSOCIATE_START == type)
  3203. btc_iface_dbg(INTF_NOTIFY,
  3204. "[BTCoex], CONNECT START notify\n");
  3205. else if (BTC_ASSOCIATE_FINISH == type)
  3206. btc_iface_dbg(INTF_NOTIFY,
  3207. "[BTCoex], CONNECT FINISH notify\n");
  3208. }
  3209. void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
  3210. u8 type)
  3211. {
  3212. u8 h2c_parameter[3] = {0};
  3213. u32 wifi_bw;
  3214. u8 wifi_center_chnl;
  3215. if (btcoexist->manual_control ||
  3216. btcoexist->stop_coex_dm ||
  3217. btcoexist->bt_info.bt_disabled)
  3218. return;
  3219. if (BTC_MEDIA_CONNECT == type)
  3220. btc_iface_dbg(INTF_NOTIFY,
  3221. "[BTCoex], MEDIA connect notify\n");
  3222. else
  3223. btc_iface_dbg(INTF_NOTIFY,
  3224. "[BTCoex], MEDIA disconnect notify\n");
  3225. /* only 2.4G we need to inform bt the chnl mask */
  3226. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
  3227. &wifi_center_chnl);
  3228. if ((BTC_MEDIA_CONNECT == type) &&
  3229. (wifi_center_chnl <= 14)) {
  3230. h2c_parameter[0] = 0x1;
  3231. h2c_parameter[1] = wifi_center_chnl;
  3232. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  3233. if (BTC_WIFI_BW_HT40 == wifi_bw)
  3234. h2c_parameter[2] = 0x30;
  3235. else
  3236. h2c_parameter[2] = 0x20;
  3237. }
  3238. coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
  3239. coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
  3240. coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
  3241. btc_alg_dbg(ALGO_TRACE_FW_EXEC,
  3242. "[BTCoex], FW write 0x66 = 0x%x\n",
  3243. h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
  3244. h2c_parameter[2]);
  3245. btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
  3246. }
  3247. void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
  3248. u8 type)
  3249. {
  3250. if (type == BTC_PACKET_DHCP)
  3251. btc_iface_dbg(INTF_NOTIFY,
  3252. "[BTCoex], DHCP Packet notify\n");
  3253. }
  3254. void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
  3255. u8 *tmp_buf, u8 length)
  3256. {
  3257. u8 bt_info = 0;
  3258. u8 i, rsp_source = 0;
  3259. bool bt_busy = false, limited_dig = false;
  3260. bool wifi_connected = false;
  3261. coex_sta->c2h_bt_info_req_sent = false;
  3262. rsp_source = tmp_buf[0] & 0xf;
  3263. if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
  3264. rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
  3265. coex_sta->bt_info_c2h_cnt[rsp_source]++;
  3266. btc_iface_dbg(INTF_NOTIFY,
  3267. "[BTCoex], Bt info[%d], length=%d, hex data = [",
  3268. rsp_source, length);
  3269. for (i = 0; i < length; i++) {
  3270. coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
  3271. if (i == 1)
  3272. bt_info = tmp_buf[i];
  3273. if (i == length-1)
  3274. btc_iface_dbg(INTF_NOTIFY,
  3275. "0x%02x]\n", tmp_buf[i]);
  3276. else
  3277. btc_iface_dbg(INTF_NOTIFY,
  3278. "0x%02x, ", tmp_buf[i]);
  3279. }
  3280. if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
  3281. coex_sta->bt_retry_cnt = /* [3:0] */
  3282. coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
  3283. coex_sta->bt_rssi =
  3284. coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
  3285. coex_sta->bt_info_ext =
  3286. coex_sta->bt_info_c2h[rsp_source][4];
  3287. /* Here we need to resend some wifi info to BT
  3288. * because bt is reset and loss of the info.
  3289. */
  3290. if ((coex_sta->bt_info_ext & BIT1)) {
  3291. btc_alg_dbg(ALGO_TRACE,
  3292. "bit1, send wifi BW&Chnl to BT!!\n");
  3293. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  3294. &wifi_connected);
  3295. if (wifi_connected)
  3296. ex_halbtc8192e2ant_media_status_notify(
  3297. btcoexist,
  3298. BTC_MEDIA_CONNECT);
  3299. else
  3300. ex_halbtc8192e2ant_media_status_notify(
  3301. btcoexist,
  3302. BTC_MEDIA_DISCONNECT);
  3303. }
  3304. if ((coex_sta->bt_info_ext & BIT3)) {
  3305. if (!btcoexist->manual_control &&
  3306. !btcoexist->stop_coex_dm) {
  3307. btc_alg_dbg(ALGO_TRACE,
  3308. "bit3, BT NOT ignore Wlan active!\n");
  3309. halbtc8192e2ant_IgnoreWlanAct(btcoexist,
  3310. FORCE_EXEC,
  3311. false);
  3312. }
  3313. } else {
  3314. /* BT already NOT ignore Wlan active,
  3315. * do nothing here.
  3316. */
  3317. }
  3318. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
  3319. if ((coex_sta->bt_info_ext & BIT4)) {
  3320. /* BT auto report already enabled, do nothing */
  3321. } else {
  3322. halbtc8192e2ant_bt_autoreport(btcoexist, FORCE_EXEC,
  3323. true);
  3324. }
  3325. #endif
  3326. }
  3327. /* check BIT2 first ==> check if bt is under inquiry or page scan */
  3328. if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
  3329. coex_sta->c2h_bt_inquiry_page = true;
  3330. else
  3331. coex_sta->c2h_bt_inquiry_page = false;
  3332. /* set link exist status */
  3333. if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
  3334. coex_sta->bt_link_exist = false;
  3335. coex_sta->pan_exist = false;
  3336. coex_sta->a2dp_exist = false;
  3337. coex_sta->hid_exist = false;
  3338. coex_sta->sco_exist = false;
  3339. } else {/* connection exists */
  3340. coex_sta->bt_link_exist = true;
  3341. if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
  3342. coex_sta->pan_exist = true;
  3343. else
  3344. coex_sta->pan_exist = false;
  3345. if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
  3346. coex_sta->a2dp_exist = true;
  3347. else
  3348. coex_sta->a2dp_exist = false;
  3349. if (bt_info & BT_INFO_8192E_2ANT_B_HID)
  3350. coex_sta->hid_exist = true;
  3351. else
  3352. coex_sta->hid_exist = false;
  3353. if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
  3354. coex_sta->sco_exist = true;
  3355. else
  3356. coex_sta->sco_exist = false;
  3357. }
  3358. halbtc8192e2ant_update_btlink_info(btcoexist);
  3359. if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
  3360. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
  3361. btc_alg_dbg(ALGO_TRACE,
  3362. "[BTCoex], BT Non-Connected idle!!!\n");
  3363. } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) {
  3364. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
  3365. btc_alg_dbg(ALGO_TRACE,
  3366. "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n");
  3367. } else if ((bt_info&BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
  3368. (bt_info&BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
  3369. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
  3370. btc_alg_dbg(ALGO_TRACE,
  3371. "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n");
  3372. } else if (bt_info&BT_INFO_8192E_2ANT_B_ACL_BUSY) {
  3373. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
  3374. btc_alg_dbg(ALGO_TRACE,
  3375. "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n");
  3376. } else {
  3377. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
  3378. btc_alg_dbg(ALGO_TRACE,
  3379. "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n");
  3380. }
  3381. if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
  3382. (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
  3383. (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
  3384. bt_busy = true;
  3385. limited_dig = true;
  3386. } else {
  3387. bt_busy = false;
  3388. limited_dig = false;
  3389. }
  3390. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
  3391. coex_dm->limited_dig = limited_dig;
  3392. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
  3393. halbtc8192e2ant_run_coexist_mechanism(btcoexist);
  3394. }
  3395. void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
  3396. u8 type)
  3397. {
  3398. }
  3399. void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist)
  3400. {
  3401. btc_iface_dbg(INTF_NOTIFY, "[BTCoex], Halt notify\n");
  3402. halbtc8192e2ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true);
  3403. ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
  3404. }
  3405. void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist)
  3406. {
  3407. static u8 dis_ver_info_cnt;
  3408. u32 fw_ver = 0, bt_patch_ver = 0;
  3409. struct btc_board_info *board_info = &btcoexist->board_info;
  3410. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  3411. btc_alg_dbg(ALGO_TRACE,
  3412. "=======================Periodical=======================\n");
  3413. if (dis_ver_info_cnt <= 5) {
  3414. dis_ver_info_cnt += 1;
  3415. btc_iface_dbg(INTF_INIT,
  3416. "************************************************\n");
  3417. btc_iface_dbg(INTF_INIT,
  3418. "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
  3419. board_info->pg_ant_num, board_info->btdm_ant_num,
  3420. board_info->btdm_ant_pos);
  3421. btc_iface_dbg(INTF_INIT,
  3422. "BT stack/ hci ext ver = %s / %d\n",
  3423. ((stack_info->profile_notified) ? "Yes" : "No"),
  3424. stack_info->hci_version);
  3425. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
  3426. &bt_patch_ver);
  3427. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  3428. btc_iface_dbg(INTF_INIT,
  3429. "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
  3430. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  3431. fw_ver, bt_patch_ver, bt_patch_ver);
  3432. btc_iface_dbg(INTF_INIT,
  3433. "************************************************\n");
  3434. }
  3435. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
  3436. halbtc8192e2ant_querybt_info(btcoexist);
  3437. halbtc8192e2ant_monitor_bt_ctr(btcoexist);
  3438. btc8192e2ant_monitor_bt_enable_dis(btcoexist);
  3439. #else
  3440. if (halbtc8192e2ant_iswifi_status_changed(btcoexist) ||
  3441. coex_dm->auto_tdma_adjust)
  3442. halbtc8192e2ant_run_coexist_mechanism(btcoexist);
  3443. #endif
  3444. }