am437x-gp-evm.dts 13 KB

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  1. /*
  2. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /* AM437x GP EVM */
  9. /dts-v1/;
  10. #include "am4372.dtsi"
  11. #include <dt-bindings/pinctrl/am43xx.h>
  12. #include <dt-bindings/pwm/pwm.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "TI AM437x GP EVM";
  16. compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  17. aliases {
  18. display0 = &lcd0;
  19. };
  20. vmmcsd_fixed: fixedregulator-sd {
  21. compatible = "regulator-fixed";
  22. regulator-name = "vmmcsd_fixed";
  23. regulator-min-microvolt = <3300000>;
  24. regulator-max-microvolt = <3300000>;
  25. enable-active-high;
  26. };
  27. vtt_fixed: fixedregulator-vtt {
  28. compatible = "regulator-fixed";
  29. regulator-name = "vtt_fixed";
  30. regulator-min-microvolt = <1500000>;
  31. regulator-max-microvolt = <1500000>;
  32. regulator-always-on;
  33. regulator-boot-on;
  34. enable-active-high;
  35. gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  36. };
  37. backlight {
  38. compatible = "pwm-backlight";
  39. pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  40. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  41. default-brightness-level = <8>;
  42. };
  43. matrix_keypad: matrix_keypad@0 {
  44. compatible = "gpio-matrix-keypad";
  45. debounce-delay-ms = <5>;
  46. col-scan-delay-us = <2>;
  47. row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  48. &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  49. &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  50. col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  51. &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  52. linux,keymap = <0x00000201 /* P1 */
  53. 0x00010202 /* P2 */
  54. 0x01000067 /* UP */
  55. 0x0101006a /* RIGHT */
  56. 0x02000069 /* LEFT */
  57. 0x0201006c>; /* DOWN */
  58. };
  59. lcd0: display {
  60. compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  61. label = "lcd";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&lcd_pins>;
  64. /*
  65. * SelLCDorHDMI, LOW to select HDMI. This is not really the
  66. * panel's enable GPIO, but we don't have HDMI driver support nor
  67. * support to switch between two displays, so using this gpio as
  68. * panel's enable should be safe.
  69. */
  70. enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
  71. panel-timing {
  72. clock-frequency = <33000000>;
  73. hactive = <800>;
  74. vactive = <480>;
  75. hfront-porch = <210>;
  76. hback-porch = <16>;
  77. hsync-len = <30>;
  78. vback-porch = <10>;
  79. vfront-porch = <22>;
  80. vsync-len = <13>;
  81. hsync-active = <0>;
  82. vsync-active = <0>;
  83. de-active = <1>;
  84. pixelclk-active = <1>;
  85. };
  86. port {
  87. lcd_in: endpoint {
  88. remote-endpoint = <&dpi_out>;
  89. };
  90. };
  91. };
  92. };
  93. &am43xx_pinmux {
  94. i2c0_pins: i2c0_pins {
  95. pinctrl-single,pins = <
  96. 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  97. 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  98. >;
  99. };
  100. i2c1_pins: i2c1_pins {
  101. pinctrl-single,pins = <
  102. 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  103. 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
  104. >;
  105. };
  106. mmc1_pins: pinmux_mmc1_pins {
  107. pinctrl-single,pins = <
  108. 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  109. >;
  110. };
  111. ecap0_pins: backlight_pins {
  112. pinctrl-single,pins = <
  113. 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  114. >;
  115. };
  116. pixcir_ts_pins: pixcir_ts_pins {
  117. pinctrl-single,pins = <
  118. 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
  119. >;
  120. };
  121. cpsw_default: cpsw_default {
  122. pinctrl-single,pins = <
  123. /* Slave 1 */
  124. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
  125. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
  126. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
  127. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
  128. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
  129. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
  130. 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
  131. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
  132. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
  133. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
  134. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
  135. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
  136. >;
  137. };
  138. cpsw_sleep: cpsw_sleep {
  139. pinctrl-single,pins = <
  140. /* Slave 1 reset value */
  141. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  142. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  143. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  144. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  145. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  146. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  147. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  148. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  149. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  150. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  151. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  152. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  153. >;
  154. };
  155. davinci_mdio_default: davinci_mdio_default {
  156. pinctrl-single,pins = <
  157. /* MDIO */
  158. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  159. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  160. >;
  161. };
  162. davinci_mdio_sleep: davinci_mdio_sleep {
  163. pinctrl-single,pins = <
  164. /* MDIO reset value */
  165. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  166. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  167. >;
  168. };
  169. nand_flash_x8: nand_flash_x8 {
  170. pinctrl-single,pins = <
  171. 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
  172. 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  173. 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  174. 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  175. 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  176. 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  177. 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  178. 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  179. 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  180. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  181. 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
  182. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  183. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  184. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  185. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  186. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  187. >;
  188. };
  189. dss_pins: dss_pins {
  190. pinctrl-single,pins = <
  191. 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
  192. 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  193. 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  194. 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
  195. 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  196. 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  197. 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  198. 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
  199. 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
  200. 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  201. 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  202. 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
  203. 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  204. 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  205. 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  206. 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
  207. 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  208. 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  209. 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  210. 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
  211. 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  212. 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  213. 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  214. 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
  215. 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
  216. 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
  217. 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
  218. 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
  219. >;
  220. };
  221. lcd_pins: lcd_pins {
  222. pinctrl-single,pins = <
  223. /* GPIO 5_8 to select LCD / HDMI */
  224. 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
  225. >;
  226. };
  227. };
  228. &i2c0 {
  229. status = "okay";
  230. pinctrl-names = "default";
  231. pinctrl-0 = <&i2c0_pins>;
  232. clock-frequency = <100000>;
  233. tps65218: tps65218@24 {
  234. reg = <0x24>;
  235. compatible = "ti,tps65218";
  236. interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
  237. interrupt-parent = <&gic>;
  238. interrupt-controller;
  239. #interrupt-cells = <2>;
  240. dcdc1: regulator-dcdc1 {
  241. compatible = "ti,tps65218-dcdc1";
  242. regulator-name = "vdd_core";
  243. regulator-min-microvolt = <912000>;
  244. regulator-max-microvolt = <1144000>;
  245. regulator-boot-on;
  246. regulator-always-on;
  247. };
  248. dcdc2: regulator-dcdc2 {
  249. compatible = "ti,tps65218-dcdc2";
  250. regulator-name = "vdd_mpu";
  251. regulator-min-microvolt = <912000>;
  252. regulator-max-microvolt = <1378000>;
  253. regulator-boot-on;
  254. regulator-always-on;
  255. };
  256. dcdc3: regulator-dcdc3 {
  257. compatible = "ti,tps65218-dcdc3";
  258. regulator-name = "vdcdc3";
  259. regulator-min-microvolt = <1500000>;
  260. regulator-max-microvolt = <1500000>;
  261. regulator-boot-on;
  262. regulator-always-on;
  263. };
  264. dcdc5: regulator-dcdc5 {
  265. compatible = "ti,tps65218-dcdc5";
  266. regulator-name = "v1_0bat";
  267. regulator-min-microvolt = <1000000>;
  268. regulator-max-microvolt = <1000000>;
  269. };
  270. dcdc6: regulator-dcdc6 {
  271. compatible = "ti,tps65218-dcdc6";
  272. regulator-name = "v1_8bat";
  273. regulator-min-microvolt = <1800000>;
  274. regulator-max-microvolt = <1800000>;
  275. };
  276. ldo1: regulator-ldo1 {
  277. compatible = "ti,tps65218-ldo1";
  278. regulator-min-microvolt = <1800000>;
  279. regulator-max-microvolt = <1800000>;
  280. regulator-boot-on;
  281. regulator-always-on;
  282. };
  283. };
  284. };
  285. &i2c1 {
  286. status = "okay";
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&i2c1_pins>;
  289. pixcir_ts@5c {
  290. compatible = "pixcir,pixcir_tangoc";
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pixcir_ts_pins>;
  293. reg = <0x5c>;
  294. interrupt-parent = <&gpio3>;
  295. interrupts = <22 0>;
  296. attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  297. touchscreen-size-x = <1024>;
  298. touchscreen-size-y = <600>;
  299. };
  300. };
  301. &epwmss0 {
  302. status = "okay";
  303. };
  304. &ecap0 {
  305. status = "okay";
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&ecap0_pins>;
  308. };
  309. &gpio0 {
  310. status = "okay";
  311. };
  312. &gpio3 {
  313. status = "okay";
  314. };
  315. &gpio4 {
  316. status = "okay";
  317. };
  318. &gpio5 {
  319. status = "okay";
  320. ti,no-reset-on-init;
  321. };
  322. &mmc1 {
  323. status = "okay";
  324. vmmc-supply = <&vmmcsd_fixed>;
  325. bus-width = <4>;
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&mmc1_pins>;
  328. cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
  329. };
  330. &usb2_phy1 {
  331. status = "okay";
  332. };
  333. &usb1 {
  334. dr_mode = "peripheral";
  335. status = "okay";
  336. };
  337. &usb2_phy2 {
  338. status = "okay";
  339. };
  340. &usb2 {
  341. dr_mode = "host";
  342. status = "okay";
  343. };
  344. &mac {
  345. slaves = <1>;
  346. pinctrl-names = "default", "sleep";
  347. pinctrl-0 = <&cpsw_default>;
  348. pinctrl-1 = <&cpsw_sleep>;
  349. status = "okay";
  350. };
  351. &davinci_mdio {
  352. pinctrl-names = "default", "sleep";
  353. pinctrl-0 = <&davinci_mdio_default>;
  354. pinctrl-1 = <&davinci_mdio_sleep>;
  355. status = "okay";
  356. };
  357. &cpsw_emac0 {
  358. phy_id = <&davinci_mdio>, <0>;
  359. phy-mode = "rgmii";
  360. };
  361. &elm {
  362. status = "okay";
  363. };
  364. &gpmc {
  365. status = "okay";
  366. pinctrl-names = "default";
  367. pinctrl-0 = <&nand_flash_x8>;
  368. ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
  369. nand@0,0 {
  370. reg = <0 0 4>; /* device IO registers */
  371. ti,nand-ecc-opt = "bch16";
  372. ti,elm-id = <&elm>;
  373. nand-bus-width = <8>;
  374. gpmc,device-width = <1>;
  375. gpmc,sync-clk-ps = <0>;
  376. gpmc,cs-on-ns = <0>;
  377. gpmc,cs-rd-off-ns = <40>;
  378. gpmc,cs-wr-off-ns = <40>;
  379. gpmc,adv-on-ns = <0>;
  380. gpmc,adv-rd-off-ns = <25>;
  381. gpmc,adv-wr-off-ns = <25>;
  382. gpmc,we-on-ns = <0>;
  383. gpmc,we-off-ns = <20>;
  384. gpmc,oe-on-ns = <3>;
  385. gpmc,oe-off-ns = <30>;
  386. gpmc,access-ns = <30>;
  387. gpmc,rd-cycle-ns = <40>;
  388. gpmc,wr-cycle-ns = <40>;
  389. gpmc,wait-pin = <0>;
  390. gpmc,bus-turnaround-ns = <0>;
  391. gpmc,cycle2cycle-delay-ns = <0>;
  392. gpmc,clk-activation-ns = <0>;
  393. gpmc,wait-monitoring-ns = <0>;
  394. gpmc,wr-access-ns = <40>;
  395. gpmc,wr-data-mux-bus-ns = <0>;
  396. /* MTD partition table */
  397. /* All SPL-* partitions are sized to minimal length
  398. * which can be independently programmable. For
  399. * NAND flash this is equal to size of erase-block */
  400. #address-cells = <1>;
  401. #size-cells = <1>;
  402. partition@0 {
  403. label = "NAND.SPL";
  404. reg = <0x00000000 0x00040000>;
  405. };
  406. partition@1 {
  407. label = "NAND.SPL.backup1";
  408. reg = <0x00040000 0x00040000>;
  409. };
  410. partition@2 {
  411. label = "NAND.SPL.backup2";
  412. reg = <0x00080000 0x00040000>;
  413. };
  414. partition@3 {
  415. label = "NAND.SPL.backup3";
  416. reg = <0x000c0000 0x00040000>;
  417. };
  418. partition@4 {
  419. label = "NAND.u-boot-spl-os";
  420. reg = <0x00100000 0x00080000>;
  421. };
  422. partition@5 {
  423. label = "NAND.u-boot";
  424. reg = <0x00180000 0x00100000>;
  425. };
  426. partition@6 {
  427. label = "NAND.u-boot-env";
  428. reg = <0x00280000 0x00040000>;
  429. };
  430. partition@7 {
  431. label = "NAND.u-boot-env.backup1";
  432. reg = <0x002c0000 0x00040000>;
  433. };
  434. partition@8 {
  435. label = "NAND.kernel";
  436. reg = <0x00300000 0x00700000>;
  437. };
  438. partition@9 {
  439. label = "NAND.file-system";
  440. reg = <0x00a00000 0x1f600000>;
  441. };
  442. };
  443. };
  444. &dss {
  445. status = "ok";
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&dss_pins>;
  448. port {
  449. dpi_out: endpoint@0 {
  450. remote-endpoint = <&lcd_in>;
  451. data-lines = <24>;
  452. };
  453. };
  454. };