ti_am335x_tscadc.c 10.0 KB

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  1. /*
  2. * TI Touch Screen / ADC MFD driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/slab.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/clk.h>
  21. #include <linux/regmap.h>
  22. #include <linux/mfd/core.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/of.h>
  25. #include <linux/of_device.h>
  26. #include <linux/sched.h>
  27. #include <linux/mfd/ti_am335x_tscadc.h>
  28. static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
  29. {
  30. unsigned int val;
  31. regmap_read(tsadc->regmap_tscadc, reg, &val);
  32. return val;
  33. }
  34. static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
  35. unsigned int val)
  36. {
  37. regmap_write(tsadc->regmap_tscadc, reg, val);
  38. }
  39. static const struct regmap_config tscadc_regmap_config = {
  40. .name = "ti_tscadc",
  41. .reg_bits = 32,
  42. .reg_stride = 4,
  43. .val_bits = 32,
  44. };
  45. void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
  46. {
  47. unsigned long flags;
  48. spin_lock_irqsave(&tsadc->reg_lock, flags);
  49. tsadc->reg_se_cache = val;
  50. if (tsadc->adc_waiting)
  51. wake_up(&tsadc->reg_se_wait);
  52. else if (!tsadc->adc_in_use)
  53. tscadc_writel(tsadc, REG_SE, val);
  54. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  55. }
  56. EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
  57. static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
  58. {
  59. DEFINE_WAIT(wait);
  60. u32 reg;
  61. /*
  62. * disable TSC steps so it does not run while the ADC is using it. If
  63. * write 0 while it is running (it just started or was already running)
  64. * then it completes all steps that were enabled and stops then.
  65. */
  66. tscadc_writel(tsadc, REG_SE, 0);
  67. reg = tscadc_readl(tsadc, REG_ADCFSM);
  68. if (reg & SEQ_STATUS) {
  69. tsadc->adc_waiting = true;
  70. prepare_to_wait(&tsadc->reg_se_wait, &wait,
  71. TASK_UNINTERRUPTIBLE);
  72. spin_unlock_irq(&tsadc->reg_lock);
  73. schedule();
  74. spin_lock_irq(&tsadc->reg_lock);
  75. finish_wait(&tsadc->reg_se_wait, &wait);
  76. reg = tscadc_readl(tsadc, REG_ADCFSM);
  77. WARN_ON(reg & SEQ_STATUS);
  78. tsadc->adc_waiting = false;
  79. }
  80. tsadc->adc_in_use = true;
  81. }
  82. void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
  83. {
  84. spin_lock_irq(&tsadc->reg_lock);
  85. am335x_tscadc_need_adc(tsadc);
  86. tscadc_writel(tsadc, REG_SE, val);
  87. spin_unlock_irq(&tsadc->reg_lock);
  88. }
  89. EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
  90. void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
  91. {
  92. unsigned long flags;
  93. spin_lock_irqsave(&tsadc->reg_lock, flags);
  94. tsadc->adc_in_use = false;
  95. tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
  96. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  97. }
  98. EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
  99. void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
  100. {
  101. unsigned long flags;
  102. spin_lock_irqsave(&tsadc->reg_lock, flags);
  103. tsadc->reg_se_cache &= ~val;
  104. tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
  105. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  106. }
  107. EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
  108. static void tscadc_idle_config(struct ti_tscadc_dev *config)
  109. {
  110. unsigned int idleconfig;
  111. idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
  112. STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
  113. tscadc_writel(config, REG_IDLECONFIG, idleconfig);
  114. }
  115. static int ti_tscadc_probe(struct platform_device *pdev)
  116. {
  117. struct ti_tscadc_dev *tscadc;
  118. struct resource *res;
  119. struct clk *clk;
  120. struct device_node *node = pdev->dev.of_node;
  121. struct mfd_cell *cell;
  122. struct property *prop;
  123. const __be32 *cur;
  124. u32 val;
  125. int err, ctrl;
  126. int clock_rate;
  127. int tsc_wires = 0, adc_channels = 0, total_channels;
  128. int readouts = 0;
  129. if (!pdev->dev.of_node) {
  130. dev_err(&pdev->dev, "Could not find valid DT data.\n");
  131. return -EINVAL;
  132. }
  133. node = of_get_child_by_name(pdev->dev.of_node, "tsc");
  134. of_property_read_u32(node, "ti,wires", &tsc_wires);
  135. of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
  136. node = of_get_child_by_name(pdev->dev.of_node, "adc");
  137. of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
  138. adc_channels++;
  139. if (val > 7) {
  140. dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
  141. val);
  142. return -EINVAL;
  143. }
  144. }
  145. total_channels = tsc_wires + adc_channels;
  146. if (total_channels > 8) {
  147. dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
  148. return -EINVAL;
  149. }
  150. if (total_channels == 0) {
  151. dev_err(&pdev->dev, "Need atleast one channel.\n");
  152. return -EINVAL;
  153. }
  154. if (readouts * 2 + 2 + adc_channels > 16) {
  155. dev_err(&pdev->dev, "Too many step configurations requested\n");
  156. return -EINVAL;
  157. }
  158. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  159. if (!res) {
  160. dev_err(&pdev->dev, "no memory resource defined.\n");
  161. return -EINVAL;
  162. }
  163. /* Allocate memory for device */
  164. tscadc = devm_kzalloc(&pdev->dev,
  165. sizeof(struct ti_tscadc_dev), GFP_KERNEL);
  166. if (!tscadc) {
  167. dev_err(&pdev->dev, "failed to allocate memory.\n");
  168. return -ENOMEM;
  169. }
  170. tscadc->dev = &pdev->dev;
  171. err = platform_get_irq(pdev, 0);
  172. if (err < 0) {
  173. dev_err(&pdev->dev, "no irq ID is specified.\n");
  174. goto ret;
  175. } else
  176. tscadc->irq = err;
  177. res = devm_request_mem_region(&pdev->dev,
  178. res->start, resource_size(res), pdev->name);
  179. if (!res) {
  180. dev_err(&pdev->dev, "failed to reserve registers.\n");
  181. return -EBUSY;
  182. }
  183. tscadc->tscadc_base = devm_ioremap(&pdev->dev,
  184. res->start, resource_size(res));
  185. if (!tscadc->tscadc_base) {
  186. dev_err(&pdev->dev, "failed to map registers.\n");
  187. return -ENOMEM;
  188. }
  189. tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
  190. tscadc->tscadc_base, &tscadc_regmap_config);
  191. if (IS_ERR(tscadc->regmap_tscadc)) {
  192. dev_err(&pdev->dev, "regmap init failed\n");
  193. err = PTR_ERR(tscadc->regmap_tscadc);
  194. goto ret;
  195. }
  196. spin_lock_init(&tscadc->reg_lock);
  197. init_waitqueue_head(&tscadc->reg_se_wait);
  198. pm_runtime_enable(&pdev->dev);
  199. pm_runtime_get_sync(&pdev->dev);
  200. /*
  201. * The TSC_ADC_Subsystem has 2 clock domains
  202. * OCP_CLK and ADC_CLK.
  203. * The ADC clock is expected to run at target of 3MHz,
  204. * and expected to capture 12-bit data at a rate of 200 KSPS.
  205. * The TSC_ADC_SS controller design assumes the OCP clock is
  206. * at least 6x faster than the ADC clock.
  207. */
  208. clk = clk_get(&pdev->dev, "adc_tsc_fck");
  209. if (IS_ERR(clk)) {
  210. dev_err(&pdev->dev, "failed to get TSC fck\n");
  211. err = PTR_ERR(clk);
  212. goto err_disable_clk;
  213. }
  214. clock_rate = clk_get_rate(clk);
  215. clk_put(clk);
  216. tscadc->clk_div = clock_rate / ADC_CLK;
  217. /* TSCADC_CLKDIV needs to be configured to the value minus 1 */
  218. tscadc->clk_div--;
  219. tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
  220. /* Set the control register bits */
  221. ctrl = CNTRLREG_STEPCONFIGWRT |
  222. CNTRLREG_STEPID;
  223. if (tsc_wires > 0)
  224. ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
  225. tscadc_writel(tscadc, REG_CTRL, ctrl);
  226. /* Set register bits for Idle Config Mode */
  227. if (tsc_wires > 0)
  228. tscadc_idle_config(tscadc);
  229. /* Enable the TSC module enable bit */
  230. ctrl = tscadc_readl(tscadc, REG_CTRL);
  231. ctrl |= CNTRLREG_TSCSSENB;
  232. tscadc_writel(tscadc, REG_CTRL, ctrl);
  233. tscadc->used_cells = 0;
  234. tscadc->tsc_cell = -1;
  235. tscadc->adc_cell = -1;
  236. /* TSC Cell */
  237. if (tsc_wires > 0) {
  238. tscadc->tsc_cell = tscadc->used_cells;
  239. cell = &tscadc->cells[tscadc->used_cells++];
  240. cell->name = "TI-am335x-tsc";
  241. cell->of_compatible = "ti,am3359-tsc";
  242. cell->platform_data = &tscadc;
  243. cell->pdata_size = sizeof(tscadc);
  244. }
  245. /* ADC Cell */
  246. if (adc_channels > 0) {
  247. tscadc->adc_cell = tscadc->used_cells;
  248. cell = &tscadc->cells[tscadc->used_cells++];
  249. cell->name = "TI-am335x-adc";
  250. cell->of_compatible = "ti,am3359-adc";
  251. cell->platform_data = &tscadc;
  252. cell->pdata_size = sizeof(tscadc);
  253. }
  254. err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
  255. tscadc->used_cells, NULL, 0, NULL);
  256. if (err < 0)
  257. goto err_disable_clk;
  258. device_init_wakeup(&pdev->dev, true);
  259. platform_set_drvdata(pdev, tscadc);
  260. return 0;
  261. err_disable_clk:
  262. pm_runtime_put_sync(&pdev->dev);
  263. pm_runtime_disable(&pdev->dev);
  264. ret:
  265. return err;
  266. }
  267. static int ti_tscadc_remove(struct platform_device *pdev)
  268. {
  269. struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
  270. tscadc_writel(tscadc, REG_SE, 0x00);
  271. pm_runtime_put_sync(&pdev->dev);
  272. pm_runtime_disable(&pdev->dev);
  273. mfd_remove_devices(tscadc->dev);
  274. return 0;
  275. }
  276. #ifdef CONFIG_PM
  277. static int tscadc_suspend(struct device *dev)
  278. {
  279. struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
  280. tscadc_writel(tscadc_dev, REG_SE, 0x00);
  281. pm_runtime_put_sync(dev);
  282. return 0;
  283. }
  284. static int tscadc_resume(struct device *dev)
  285. {
  286. struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
  287. unsigned int restore, ctrl;
  288. pm_runtime_get_sync(dev);
  289. /* context restore */
  290. ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
  291. if (tscadc_dev->tsc_cell != -1)
  292. ctrl |= CNTRLREG_TSCENB | CNTRLREG_4WIRE;
  293. tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
  294. if (tscadc_dev->tsc_cell != -1)
  295. tscadc_idle_config(tscadc_dev);
  296. restore = tscadc_readl(tscadc_dev, REG_CTRL);
  297. tscadc_writel(tscadc_dev, REG_CTRL,
  298. (restore | CNTRLREG_TSCSSENB));
  299. tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
  300. return 0;
  301. }
  302. static const struct dev_pm_ops tscadc_pm_ops = {
  303. .suspend = tscadc_suspend,
  304. .resume = tscadc_resume,
  305. };
  306. #define TSCADC_PM_OPS (&tscadc_pm_ops)
  307. #else
  308. #define TSCADC_PM_OPS NULL
  309. #endif
  310. static const struct of_device_id ti_tscadc_dt_ids[] = {
  311. { .compatible = "ti,am3359-tscadc", },
  312. { }
  313. };
  314. MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
  315. static struct platform_driver ti_tscadc_driver = {
  316. .driver = {
  317. .name = "ti_am3359-tscadc",
  318. .owner = THIS_MODULE,
  319. .pm = TSCADC_PM_OPS,
  320. .of_match_table = ti_tscadc_dt_ids,
  321. },
  322. .probe = ti_tscadc_probe,
  323. .remove = ti_tscadc_remove,
  324. };
  325. module_platform_driver(ti_tscadc_driver);
  326. MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
  327. MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
  328. MODULE_LICENSE("GPL");