enic_main.c 77 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086
  1. /*
  2. * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/string.h>
  22. #include <linux/errno.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/if.h>
  31. #include <linux/if_ether.h>
  32. #include <linux/if_vlan.h>
  33. #include <linux/in.h>
  34. #include <linux/ip.h>
  35. #include <linux/ipv6.h>
  36. #include <linux/tcp.h>
  37. #include <linux/rtnetlink.h>
  38. #include <linux/prefetch.h>
  39. #include <net/ip6_checksum.h>
  40. #include <linux/ktime.h>
  41. #include <linux/numa.h>
  42. #ifdef CONFIG_RFS_ACCEL
  43. #include <linux/cpu_rmap.h>
  44. #endif
  45. #include <linux/crash_dump.h>
  46. #include <net/busy_poll.h>
  47. #include <net/vxlan.h>
  48. #include "cq_enet_desc.h"
  49. #include "vnic_dev.h"
  50. #include "vnic_intr.h"
  51. #include "vnic_stats.h"
  52. #include "vnic_vic.h"
  53. #include "enic_res.h"
  54. #include "enic.h"
  55. #include "enic_dev.h"
  56. #include "enic_pp.h"
  57. #include "enic_clsf.h"
  58. #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
  59. #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
  60. #define MAX_TSO (1 << 16)
  61. #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
  62. #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
  63. #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
  64. #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
  65. #define RX_COPYBREAK_DEFAULT 256
  66. /* Supported devices */
  67. static const struct pci_device_id enic_id_table[] = {
  68. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
  69. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
  70. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
  71. { 0, } /* end of table */
  72. };
  73. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  74. MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
  75. MODULE_LICENSE("GPL");
  76. MODULE_VERSION(DRV_VERSION);
  77. MODULE_DEVICE_TABLE(pci, enic_id_table);
  78. #define ENIC_LARGE_PKT_THRESHOLD 1000
  79. #define ENIC_MAX_COALESCE_TIMERS 10
  80. /* Interrupt moderation table, which will be used to decide the
  81. * coalescing timer values
  82. * {rx_rate in Mbps, mapping percentage of the range}
  83. */
  84. static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
  85. {4000, 0},
  86. {4400, 10},
  87. {5060, 20},
  88. {5230, 30},
  89. {5540, 40},
  90. {5820, 50},
  91. {6120, 60},
  92. {6435, 70},
  93. {6745, 80},
  94. {7000, 90},
  95. {0xFFFFFFFF, 100}
  96. };
  97. /* This table helps the driver to pick different ranges for rx coalescing
  98. * timer depending on the link speed.
  99. */
  100. static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
  101. {0, 0}, /* 0 - 4 Gbps */
  102. {0, 3}, /* 4 - 10 Gbps */
  103. {3, 6}, /* 10 - 40 Gbps */
  104. };
  105. static void enic_init_affinity_hint(struct enic *enic)
  106. {
  107. int numa_node = dev_to_node(&enic->pdev->dev);
  108. int i;
  109. for (i = 0; i < enic->intr_count; i++) {
  110. if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i) ||
  111. (enic->msix[i].affinity_mask &&
  112. !cpumask_empty(enic->msix[i].affinity_mask)))
  113. continue;
  114. if (zalloc_cpumask_var(&enic->msix[i].affinity_mask,
  115. GFP_KERNEL))
  116. cpumask_set_cpu(cpumask_local_spread(i, numa_node),
  117. enic->msix[i].affinity_mask);
  118. }
  119. }
  120. static void enic_free_affinity_hint(struct enic *enic)
  121. {
  122. int i;
  123. for (i = 0; i < enic->intr_count; i++) {
  124. if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i))
  125. continue;
  126. free_cpumask_var(enic->msix[i].affinity_mask);
  127. }
  128. }
  129. static void enic_set_affinity_hint(struct enic *enic)
  130. {
  131. int i;
  132. int err;
  133. for (i = 0; i < enic->intr_count; i++) {
  134. if (enic_is_err_intr(enic, i) ||
  135. enic_is_notify_intr(enic, i) ||
  136. !enic->msix[i].affinity_mask ||
  137. cpumask_empty(enic->msix[i].affinity_mask))
  138. continue;
  139. err = irq_set_affinity_hint(enic->msix_entry[i].vector,
  140. enic->msix[i].affinity_mask);
  141. if (err)
  142. netdev_warn(enic->netdev, "irq_set_affinity_hint failed, err %d\n",
  143. err);
  144. }
  145. for (i = 0; i < enic->wq_count; i++) {
  146. int wq_intr = enic_msix_wq_intr(enic, i);
  147. if (enic->msix[wq_intr].affinity_mask &&
  148. !cpumask_empty(enic->msix[wq_intr].affinity_mask))
  149. netif_set_xps_queue(enic->netdev,
  150. enic->msix[wq_intr].affinity_mask,
  151. i);
  152. }
  153. }
  154. static void enic_unset_affinity_hint(struct enic *enic)
  155. {
  156. int i;
  157. for (i = 0; i < enic->intr_count; i++)
  158. irq_set_affinity_hint(enic->msix_entry[i].vector, NULL);
  159. }
  160. static void enic_udp_tunnel_add(struct net_device *netdev,
  161. struct udp_tunnel_info *ti)
  162. {
  163. struct enic *enic = netdev_priv(netdev);
  164. __be16 port = ti->port;
  165. int err;
  166. spin_lock_bh(&enic->devcmd_lock);
  167. if (ti->type != UDP_TUNNEL_TYPE_VXLAN) {
  168. netdev_info(netdev, "udp_tnl: only vxlan tunnel offload supported");
  169. goto error;
  170. }
  171. switch (ti->sa_family) {
  172. case AF_INET6:
  173. if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6)) {
  174. netdev_info(netdev, "vxlan: only IPv4 offload supported");
  175. goto error;
  176. }
  177. /* Fall through */
  178. case AF_INET:
  179. break;
  180. default:
  181. goto error;
  182. }
  183. if (enic->vxlan.vxlan_udp_port_number) {
  184. if (ntohs(port) == enic->vxlan.vxlan_udp_port_number)
  185. netdev_warn(netdev, "vxlan: udp port already offloaded");
  186. else
  187. netdev_info(netdev, "vxlan: offload supported for only one UDP port");
  188. goto error;
  189. }
  190. if ((vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ) != 1) &&
  191. !(enic->vxlan.flags & ENIC_VXLAN_MULTI_WQ)) {
  192. netdev_info(netdev, "vxlan: vxlan offload with multi wq not supported on this adapter");
  193. goto error;
  194. }
  195. err = vnic_dev_overlay_offload_cfg(enic->vdev,
  196. OVERLAY_CFG_VXLAN_PORT_UPDATE,
  197. ntohs(port));
  198. if (err)
  199. goto error;
  200. err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
  201. enic->vxlan.patch_level);
  202. if (err)
  203. goto error;
  204. enic->vxlan.vxlan_udp_port_number = ntohs(port);
  205. netdev_info(netdev, "vxlan fw-vers-%d: offload enabled for udp port: %d, sa_family: %d ",
  206. (int)enic->vxlan.patch_level, ntohs(port), ti->sa_family);
  207. goto unlock;
  208. error:
  209. netdev_info(netdev, "failed to offload udp port: %d, sa_family: %d, type: %d",
  210. ntohs(port), ti->sa_family, ti->type);
  211. unlock:
  212. spin_unlock_bh(&enic->devcmd_lock);
  213. }
  214. static void enic_udp_tunnel_del(struct net_device *netdev,
  215. struct udp_tunnel_info *ti)
  216. {
  217. struct enic *enic = netdev_priv(netdev);
  218. int err;
  219. spin_lock_bh(&enic->devcmd_lock);
  220. if ((ti->sa_family != AF_INET) ||
  221. ((ntohs(ti->port) != enic->vxlan.vxlan_udp_port_number)) ||
  222. (ti->type != UDP_TUNNEL_TYPE_VXLAN)) {
  223. netdev_info(netdev, "udp_tnl: port:%d, sa_family: %d, type: %d not offloaded",
  224. ntohs(ti->port), ti->sa_family, ti->type);
  225. goto unlock;
  226. }
  227. err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
  228. OVERLAY_OFFLOAD_DISABLE);
  229. if (err) {
  230. netdev_err(netdev, "vxlan: del offload udp port: %d failed",
  231. ntohs(ti->port));
  232. goto unlock;
  233. }
  234. enic->vxlan.vxlan_udp_port_number = 0;
  235. netdev_info(netdev, "vxlan: del offload udp port %d, family %d\n",
  236. ntohs(ti->port), ti->sa_family);
  237. unlock:
  238. spin_unlock_bh(&enic->devcmd_lock);
  239. }
  240. static netdev_features_t enic_features_check(struct sk_buff *skb,
  241. struct net_device *dev,
  242. netdev_features_t features)
  243. {
  244. const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
  245. struct enic *enic = netdev_priv(dev);
  246. struct udphdr *udph;
  247. u16 port = 0;
  248. u8 proto;
  249. if (!skb->encapsulation)
  250. return features;
  251. features = vxlan_features_check(skb, features);
  252. switch (vlan_get_protocol(skb)) {
  253. case htons(ETH_P_IPV6):
  254. if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6))
  255. goto out;
  256. proto = ipv6_hdr(skb)->nexthdr;
  257. break;
  258. case htons(ETH_P_IP):
  259. proto = ip_hdr(skb)->protocol;
  260. break;
  261. default:
  262. goto out;
  263. }
  264. switch (eth->h_proto) {
  265. case ntohs(ETH_P_IPV6):
  266. if (!(enic->vxlan.flags & ENIC_VXLAN_INNER_IPV6))
  267. goto out;
  268. /* Fall through */
  269. case ntohs(ETH_P_IP):
  270. break;
  271. default:
  272. goto out;
  273. }
  274. if (proto == IPPROTO_UDP) {
  275. udph = udp_hdr(skb);
  276. port = be16_to_cpu(udph->dest);
  277. }
  278. /* HW supports offload of only one UDP port. Remove CSUM and GSO MASK
  279. * for other UDP port tunnels
  280. */
  281. if (port != enic->vxlan.vxlan_udp_port_number)
  282. goto out;
  283. return features;
  284. out:
  285. return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  286. }
  287. int enic_is_dynamic(struct enic *enic)
  288. {
  289. return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
  290. }
  291. int enic_sriov_enabled(struct enic *enic)
  292. {
  293. return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
  294. }
  295. static int enic_is_sriov_vf(struct enic *enic)
  296. {
  297. return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
  298. }
  299. int enic_is_valid_vf(struct enic *enic, int vf)
  300. {
  301. #ifdef CONFIG_PCI_IOV
  302. return vf >= 0 && vf < enic->num_vfs;
  303. #else
  304. return 0;
  305. #endif
  306. }
  307. static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
  308. {
  309. struct enic *enic = vnic_dev_priv(wq->vdev);
  310. if (buf->sop)
  311. pci_unmap_single(enic->pdev, buf->dma_addr,
  312. buf->len, PCI_DMA_TODEVICE);
  313. else
  314. pci_unmap_page(enic->pdev, buf->dma_addr,
  315. buf->len, PCI_DMA_TODEVICE);
  316. if (buf->os_buf)
  317. dev_kfree_skb_any(buf->os_buf);
  318. }
  319. static void enic_wq_free_buf(struct vnic_wq *wq,
  320. struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
  321. {
  322. enic_free_wq_buf(wq, buf);
  323. }
  324. static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  325. u8 type, u16 q_number, u16 completed_index, void *opaque)
  326. {
  327. struct enic *enic = vnic_dev_priv(vdev);
  328. spin_lock(&enic->wq_lock[q_number]);
  329. vnic_wq_service(&enic->wq[q_number], cq_desc,
  330. completed_index, enic_wq_free_buf,
  331. opaque);
  332. if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
  333. vnic_wq_desc_avail(&enic->wq[q_number]) >=
  334. (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
  335. netif_wake_subqueue(enic->netdev, q_number);
  336. spin_unlock(&enic->wq_lock[q_number]);
  337. return 0;
  338. }
  339. static bool enic_log_q_error(struct enic *enic)
  340. {
  341. unsigned int i;
  342. u32 error_status;
  343. bool err = false;
  344. for (i = 0; i < enic->wq_count; i++) {
  345. error_status = vnic_wq_error_status(&enic->wq[i]);
  346. err |= error_status;
  347. if (error_status)
  348. netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
  349. i, error_status);
  350. }
  351. for (i = 0; i < enic->rq_count; i++) {
  352. error_status = vnic_rq_error_status(&enic->rq[i]);
  353. err |= error_status;
  354. if (error_status)
  355. netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
  356. i, error_status);
  357. }
  358. return err;
  359. }
  360. static void enic_msglvl_check(struct enic *enic)
  361. {
  362. u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
  363. if (msg_enable != enic->msg_enable) {
  364. netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
  365. enic->msg_enable, msg_enable);
  366. enic->msg_enable = msg_enable;
  367. }
  368. }
  369. static void enic_mtu_check(struct enic *enic)
  370. {
  371. u32 mtu = vnic_dev_mtu(enic->vdev);
  372. struct net_device *netdev = enic->netdev;
  373. if (mtu && mtu != enic->port_mtu) {
  374. enic->port_mtu = mtu;
  375. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
  376. mtu = max_t(int, ENIC_MIN_MTU,
  377. min_t(int, ENIC_MAX_MTU, mtu));
  378. if (mtu != netdev->mtu)
  379. schedule_work(&enic->change_mtu_work);
  380. } else {
  381. if (mtu < netdev->mtu)
  382. netdev_warn(netdev,
  383. "interface MTU (%d) set higher "
  384. "than switch port MTU (%d)\n",
  385. netdev->mtu, mtu);
  386. }
  387. }
  388. }
  389. static void enic_link_check(struct enic *enic)
  390. {
  391. int link_status = vnic_dev_link_status(enic->vdev);
  392. int carrier_ok = netif_carrier_ok(enic->netdev);
  393. if (link_status && !carrier_ok) {
  394. netdev_info(enic->netdev, "Link UP\n");
  395. netif_carrier_on(enic->netdev);
  396. } else if (!link_status && carrier_ok) {
  397. netdev_info(enic->netdev, "Link DOWN\n");
  398. netif_carrier_off(enic->netdev);
  399. }
  400. }
  401. static void enic_notify_check(struct enic *enic)
  402. {
  403. enic_msglvl_check(enic);
  404. enic_mtu_check(enic);
  405. enic_link_check(enic);
  406. }
  407. #define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
  408. static irqreturn_t enic_isr_legacy(int irq, void *data)
  409. {
  410. struct net_device *netdev = data;
  411. struct enic *enic = netdev_priv(netdev);
  412. unsigned int io_intr = enic_legacy_io_intr();
  413. unsigned int err_intr = enic_legacy_err_intr();
  414. unsigned int notify_intr = enic_legacy_notify_intr();
  415. u32 pba;
  416. vnic_intr_mask(&enic->intr[io_intr]);
  417. pba = vnic_intr_legacy_pba(enic->legacy_pba);
  418. if (!pba) {
  419. vnic_intr_unmask(&enic->intr[io_intr]);
  420. return IRQ_NONE; /* not our interrupt */
  421. }
  422. if (ENIC_TEST_INTR(pba, notify_intr)) {
  423. enic_notify_check(enic);
  424. vnic_intr_return_all_credits(&enic->intr[notify_intr]);
  425. }
  426. if (ENIC_TEST_INTR(pba, err_intr)) {
  427. vnic_intr_return_all_credits(&enic->intr[err_intr]);
  428. enic_log_q_error(enic);
  429. /* schedule recovery from WQ/RQ error */
  430. schedule_work(&enic->reset);
  431. return IRQ_HANDLED;
  432. }
  433. if (ENIC_TEST_INTR(pba, io_intr))
  434. napi_schedule_irqoff(&enic->napi[0]);
  435. else
  436. vnic_intr_unmask(&enic->intr[io_intr]);
  437. return IRQ_HANDLED;
  438. }
  439. static irqreturn_t enic_isr_msi(int irq, void *data)
  440. {
  441. struct enic *enic = data;
  442. /* With MSI, there is no sharing of interrupts, so this is
  443. * our interrupt and there is no need to ack it. The device
  444. * is not providing per-vector masking, so the OS will not
  445. * write to PCI config space to mask/unmask the interrupt.
  446. * We're using mask_on_assertion for MSI, so the device
  447. * automatically masks the interrupt when the interrupt is
  448. * generated. Later, when exiting polling, the interrupt
  449. * will be unmasked (see enic_poll).
  450. *
  451. * Also, the device uses the same PCIe Traffic Class (TC)
  452. * for Memory Write data and MSI, so there are no ordering
  453. * issues; the MSI will always arrive at the Root Complex
  454. * _after_ corresponding Memory Writes (i.e. descriptor
  455. * writes).
  456. */
  457. napi_schedule_irqoff(&enic->napi[0]);
  458. return IRQ_HANDLED;
  459. }
  460. static irqreturn_t enic_isr_msix(int irq, void *data)
  461. {
  462. struct napi_struct *napi = data;
  463. napi_schedule_irqoff(napi);
  464. return IRQ_HANDLED;
  465. }
  466. static irqreturn_t enic_isr_msix_err(int irq, void *data)
  467. {
  468. struct enic *enic = data;
  469. unsigned int intr = enic_msix_err_intr(enic);
  470. vnic_intr_return_all_credits(&enic->intr[intr]);
  471. if (enic_log_q_error(enic))
  472. /* schedule recovery from WQ/RQ error */
  473. schedule_work(&enic->reset);
  474. return IRQ_HANDLED;
  475. }
  476. static irqreturn_t enic_isr_msix_notify(int irq, void *data)
  477. {
  478. struct enic *enic = data;
  479. unsigned int intr = enic_msix_notify_intr(enic);
  480. enic_notify_check(enic);
  481. vnic_intr_return_all_credits(&enic->intr[intr]);
  482. return IRQ_HANDLED;
  483. }
  484. static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq,
  485. struct sk_buff *skb, unsigned int len_left,
  486. int loopback)
  487. {
  488. const skb_frag_t *frag;
  489. dma_addr_t dma_addr;
  490. /* Queue additional data fragments */
  491. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  492. len_left -= skb_frag_size(frag);
  493. dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
  494. skb_frag_size(frag),
  495. DMA_TO_DEVICE);
  496. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  497. return -ENOMEM;
  498. enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
  499. (len_left == 0), /* EOP? */
  500. loopback);
  501. }
  502. return 0;
  503. }
  504. static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq,
  505. struct sk_buff *skb, int vlan_tag_insert,
  506. unsigned int vlan_tag, int loopback)
  507. {
  508. unsigned int head_len = skb_headlen(skb);
  509. unsigned int len_left = skb->len - head_len;
  510. int eop = (len_left == 0);
  511. dma_addr_t dma_addr;
  512. int err = 0;
  513. dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
  514. PCI_DMA_TODEVICE);
  515. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  516. return -ENOMEM;
  517. /* Queue the main skb fragment. The fragments are no larger
  518. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  519. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  520. * per fragment is queued.
  521. */
  522. enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert,
  523. vlan_tag, eop, loopback);
  524. if (!eop)
  525. err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
  526. return err;
  527. }
  528. static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq,
  529. struct sk_buff *skb, int vlan_tag_insert,
  530. unsigned int vlan_tag, int loopback)
  531. {
  532. unsigned int head_len = skb_headlen(skb);
  533. unsigned int len_left = skb->len - head_len;
  534. unsigned int hdr_len = skb_checksum_start_offset(skb);
  535. unsigned int csum_offset = hdr_len + skb->csum_offset;
  536. int eop = (len_left == 0);
  537. dma_addr_t dma_addr;
  538. int err = 0;
  539. dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
  540. PCI_DMA_TODEVICE);
  541. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  542. return -ENOMEM;
  543. /* Queue the main skb fragment. The fragments are no larger
  544. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  545. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  546. * per fragment is queued.
  547. */
  548. enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset,
  549. hdr_len, vlan_tag_insert, vlan_tag, eop,
  550. loopback);
  551. if (!eop)
  552. err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
  553. return err;
  554. }
  555. static void enic_preload_tcp_csum_encap(struct sk_buff *skb)
  556. {
  557. const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
  558. switch (eth->h_proto) {
  559. case ntohs(ETH_P_IP):
  560. inner_ip_hdr(skb)->check = 0;
  561. inner_tcp_hdr(skb)->check =
  562. ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
  563. inner_ip_hdr(skb)->daddr, 0,
  564. IPPROTO_TCP, 0);
  565. break;
  566. case ntohs(ETH_P_IPV6):
  567. inner_tcp_hdr(skb)->check =
  568. ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
  569. &inner_ipv6_hdr(skb)->daddr, 0,
  570. IPPROTO_TCP, 0);
  571. break;
  572. default:
  573. WARN_ONCE(1, "Non ipv4/ipv6 inner pkt for encap offload");
  574. break;
  575. }
  576. }
  577. static void enic_preload_tcp_csum(struct sk_buff *skb)
  578. {
  579. /* Preload TCP csum field with IP pseudo hdr calculated
  580. * with IP length set to zero. HW will later add in length
  581. * to each TCP segment resulting from the TSO.
  582. */
  583. if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
  584. ip_hdr(skb)->check = 0;
  585. tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
  586. ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  587. } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
  588. tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
  589. &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  590. }
  591. }
  592. static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq,
  593. struct sk_buff *skb, unsigned int mss,
  594. int vlan_tag_insert, unsigned int vlan_tag,
  595. int loopback)
  596. {
  597. unsigned int frag_len_left = skb_headlen(skb);
  598. unsigned int len_left = skb->len - frag_len_left;
  599. int eop = (len_left == 0);
  600. unsigned int offset = 0;
  601. unsigned int hdr_len;
  602. dma_addr_t dma_addr;
  603. unsigned int len;
  604. skb_frag_t *frag;
  605. if (skb->encapsulation) {
  606. hdr_len = skb_inner_transport_header(skb) - skb->data;
  607. hdr_len += inner_tcp_hdrlen(skb);
  608. enic_preload_tcp_csum_encap(skb);
  609. } else {
  610. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  611. enic_preload_tcp_csum(skb);
  612. }
  613. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  614. * for the main skb fragment
  615. */
  616. while (frag_len_left) {
  617. len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
  618. dma_addr = pci_map_single(enic->pdev, skb->data + offset, len,
  619. PCI_DMA_TODEVICE);
  620. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  621. return -ENOMEM;
  622. enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
  623. vlan_tag_insert, vlan_tag,
  624. eop && (len == frag_len_left), loopback);
  625. frag_len_left -= len;
  626. offset += len;
  627. }
  628. if (eop)
  629. return 0;
  630. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  631. * for additional data fragments
  632. */
  633. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  634. len_left -= skb_frag_size(frag);
  635. frag_len_left = skb_frag_size(frag);
  636. offset = 0;
  637. while (frag_len_left) {
  638. len = min(frag_len_left,
  639. (unsigned int)WQ_ENET_MAX_DESC_LEN);
  640. dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
  641. offset, len,
  642. DMA_TO_DEVICE);
  643. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  644. return -ENOMEM;
  645. enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
  646. (len_left == 0) &&
  647. (len == frag_len_left),/*EOP*/
  648. loopback);
  649. frag_len_left -= len;
  650. offset += len;
  651. }
  652. }
  653. return 0;
  654. }
  655. static inline int enic_queue_wq_skb_encap(struct enic *enic, struct vnic_wq *wq,
  656. struct sk_buff *skb,
  657. int vlan_tag_insert,
  658. unsigned int vlan_tag, int loopback)
  659. {
  660. unsigned int head_len = skb_headlen(skb);
  661. unsigned int len_left = skb->len - head_len;
  662. /* Hardware will overwrite the checksum fields, calculating from
  663. * scratch and ignoring the value placed by software.
  664. * Offload mode = 00
  665. * mss[2], mss[1], mss[0] bits are set
  666. */
  667. unsigned int mss_or_csum = 7;
  668. int eop = (len_left == 0);
  669. dma_addr_t dma_addr;
  670. int err = 0;
  671. dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
  672. PCI_DMA_TODEVICE);
  673. if (unlikely(enic_dma_map_check(enic, dma_addr)))
  674. return -ENOMEM;
  675. enic_queue_wq_desc_ex(wq, skb, dma_addr, head_len, mss_or_csum, 0,
  676. vlan_tag_insert, vlan_tag,
  677. WQ_ENET_OFFLOAD_MODE_CSUM, eop, 1 /* SOP */, eop,
  678. loopback);
  679. if (!eop)
  680. err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
  681. return err;
  682. }
  683. static inline void enic_queue_wq_skb(struct enic *enic,
  684. struct vnic_wq *wq, struct sk_buff *skb)
  685. {
  686. unsigned int mss = skb_shinfo(skb)->gso_size;
  687. unsigned int vlan_tag = 0;
  688. int vlan_tag_insert = 0;
  689. int loopback = 0;
  690. int err;
  691. if (skb_vlan_tag_present(skb)) {
  692. /* VLAN tag from trunking driver */
  693. vlan_tag_insert = 1;
  694. vlan_tag = skb_vlan_tag_get(skb);
  695. } else if (enic->loop_enable) {
  696. vlan_tag = enic->loop_tag;
  697. loopback = 1;
  698. }
  699. if (mss)
  700. err = enic_queue_wq_skb_tso(enic, wq, skb, mss,
  701. vlan_tag_insert, vlan_tag,
  702. loopback);
  703. else if (skb->encapsulation)
  704. err = enic_queue_wq_skb_encap(enic, wq, skb, vlan_tag_insert,
  705. vlan_tag, loopback);
  706. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  707. err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert,
  708. vlan_tag, loopback);
  709. else
  710. err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert,
  711. vlan_tag, loopback);
  712. if (unlikely(err)) {
  713. struct vnic_wq_buf *buf;
  714. buf = wq->to_use->prev;
  715. /* while not EOP of previous pkt && queue not empty.
  716. * For all non EOP bufs, os_buf is NULL.
  717. */
  718. while (!buf->os_buf && (buf->next != wq->to_clean)) {
  719. enic_free_wq_buf(wq, buf);
  720. wq->ring.desc_avail++;
  721. buf = buf->prev;
  722. }
  723. wq->to_use = buf->next;
  724. dev_kfree_skb(skb);
  725. }
  726. }
  727. /* netif_tx_lock held, process context with BHs disabled, or BH */
  728. static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
  729. struct net_device *netdev)
  730. {
  731. struct enic *enic = netdev_priv(netdev);
  732. struct vnic_wq *wq;
  733. unsigned int txq_map;
  734. struct netdev_queue *txq;
  735. if (skb->len <= 0) {
  736. dev_kfree_skb_any(skb);
  737. return NETDEV_TX_OK;
  738. }
  739. txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
  740. wq = &enic->wq[txq_map];
  741. txq = netdev_get_tx_queue(netdev, txq_map);
  742. /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
  743. * which is very likely. In the off chance it's going to take
  744. * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
  745. */
  746. if (skb_shinfo(skb)->gso_size == 0 &&
  747. skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
  748. skb_linearize(skb)) {
  749. dev_kfree_skb_any(skb);
  750. return NETDEV_TX_OK;
  751. }
  752. spin_lock(&enic->wq_lock[txq_map]);
  753. if (vnic_wq_desc_avail(wq) <
  754. skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
  755. netif_tx_stop_queue(txq);
  756. /* This is a hard error, log it */
  757. netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
  758. spin_unlock(&enic->wq_lock[txq_map]);
  759. return NETDEV_TX_BUSY;
  760. }
  761. enic_queue_wq_skb(enic, wq, skb);
  762. if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
  763. netif_tx_stop_queue(txq);
  764. skb_tx_timestamp(skb);
  765. if (!skb->xmit_more || netif_xmit_stopped(txq))
  766. vnic_wq_doorbell(wq);
  767. spin_unlock(&enic->wq_lock[txq_map]);
  768. return NETDEV_TX_OK;
  769. }
  770. /* dev_base_lock rwlock held, nominally process context */
  771. static void enic_get_stats(struct net_device *netdev,
  772. struct rtnl_link_stats64 *net_stats)
  773. {
  774. struct enic *enic = netdev_priv(netdev);
  775. struct vnic_stats *stats;
  776. int err;
  777. err = enic_dev_stats_dump(enic, &stats);
  778. /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump
  779. * For other failures, like devcmd failure, we return previously
  780. * recorded stats.
  781. */
  782. if (err == -ENOMEM)
  783. return;
  784. net_stats->tx_packets = stats->tx.tx_frames_ok;
  785. net_stats->tx_bytes = stats->tx.tx_bytes_ok;
  786. net_stats->tx_errors = stats->tx.tx_errors;
  787. net_stats->tx_dropped = stats->tx.tx_drops;
  788. net_stats->rx_packets = stats->rx.rx_frames_ok;
  789. net_stats->rx_bytes = stats->rx.rx_bytes_ok;
  790. net_stats->rx_errors = stats->rx.rx_errors;
  791. net_stats->multicast = stats->rx.rx_multicast_frames_ok;
  792. net_stats->rx_over_errors = enic->rq_truncated_pkts;
  793. net_stats->rx_crc_errors = enic->rq_bad_fcs;
  794. net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
  795. }
  796. static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
  797. {
  798. struct enic *enic = netdev_priv(netdev);
  799. if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
  800. unsigned int mc_count = netdev_mc_count(netdev);
  801. netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
  802. ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
  803. return -ENOSPC;
  804. }
  805. enic_dev_add_addr(enic, mc_addr);
  806. enic->mc_count++;
  807. return 0;
  808. }
  809. static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
  810. {
  811. struct enic *enic = netdev_priv(netdev);
  812. enic_dev_del_addr(enic, mc_addr);
  813. enic->mc_count--;
  814. return 0;
  815. }
  816. static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
  817. {
  818. struct enic *enic = netdev_priv(netdev);
  819. if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
  820. unsigned int uc_count = netdev_uc_count(netdev);
  821. netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
  822. ENIC_UNICAST_PERFECT_FILTERS, uc_count);
  823. return -ENOSPC;
  824. }
  825. enic_dev_add_addr(enic, uc_addr);
  826. enic->uc_count++;
  827. return 0;
  828. }
  829. static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
  830. {
  831. struct enic *enic = netdev_priv(netdev);
  832. enic_dev_del_addr(enic, uc_addr);
  833. enic->uc_count--;
  834. return 0;
  835. }
  836. void enic_reset_addr_lists(struct enic *enic)
  837. {
  838. struct net_device *netdev = enic->netdev;
  839. __dev_uc_unsync(netdev, NULL);
  840. __dev_mc_unsync(netdev, NULL);
  841. enic->mc_count = 0;
  842. enic->uc_count = 0;
  843. enic->flags = 0;
  844. }
  845. static int enic_set_mac_addr(struct net_device *netdev, char *addr)
  846. {
  847. struct enic *enic = netdev_priv(netdev);
  848. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
  849. if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
  850. return -EADDRNOTAVAIL;
  851. } else {
  852. if (!is_valid_ether_addr(addr))
  853. return -EADDRNOTAVAIL;
  854. }
  855. memcpy(netdev->dev_addr, addr, netdev->addr_len);
  856. return 0;
  857. }
  858. static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
  859. {
  860. struct enic *enic = netdev_priv(netdev);
  861. struct sockaddr *saddr = p;
  862. char *addr = saddr->sa_data;
  863. int err;
  864. if (netif_running(enic->netdev)) {
  865. err = enic_dev_del_station_addr(enic);
  866. if (err)
  867. return err;
  868. }
  869. err = enic_set_mac_addr(netdev, addr);
  870. if (err)
  871. return err;
  872. if (netif_running(enic->netdev)) {
  873. err = enic_dev_add_station_addr(enic);
  874. if (err)
  875. return err;
  876. }
  877. return err;
  878. }
  879. static int enic_set_mac_address(struct net_device *netdev, void *p)
  880. {
  881. struct sockaddr *saddr = p;
  882. char *addr = saddr->sa_data;
  883. struct enic *enic = netdev_priv(netdev);
  884. int err;
  885. err = enic_dev_del_station_addr(enic);
  886. if (err)
  887. return err;
  888. err = enic_set_mac_addr(netdev, addr);
  889. if (err)
  890. return err;
  891. return enic_dev_add_station_addr(enic);
  892. }
  893. /* netif_tx_lock held, BHs disabled */
  894. static void enic_set_rx_mode(struct net_device *netdev)
  895. {
  896. struct enic *enic = netdev_priv(netdev);
  897. int directed = 1;
  898. int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
  899. int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
  900. int promisc = (netdev->flags & IFF_PROMISC) ||
  901. netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
  902. int allmulti = (netdev->flags & IFF_ALLMULTI) ||
  903. netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
  904. unsigned int flags = netdev->flags |
  905. (allmulti ? IFF_ALLMULTI : 0) |
  906. (promisc ? IFF_PROMISC : 0);
  907. if (enic->flags != flags) {
  908. enic->flags = flags;
  909. enic_dev_packet_filter(enic, directed,
  910. multicast, broadcast, promisc, allmulti);
  911. }
  912. if (!promisc) {
  913. __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
  914. if (!allmulti)
  915. __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
  916. }
  917. }
  918. /* netif_tx_lock held, BHs disabled */
  919. static void enic_tx_timeout(struct net_device *netdev)
  920. {
  921. struct enic *enic = netdev_priv(netdev);
  922. schedule_work(&enic->tx_hang_reset);
  923. }
  924. static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
  925. {
  926. struct enic *enic = netdev_priv(netdev);
  927. struct enic_port_profile *pp;
  928. int err;
  929. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  930. if (err)
  931. return err;
  932. if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
  933. if (vf == PORT_SELF_VF) {
  934. memcpy(pp->vf_mac, mac, ETH_ALEN);
  935. return 0;
  936. } else {
  937. /*
  938. * For sriov vf's set the mac in hw
  939. */
  940. ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
  941. vnic_dev_set_mac_addr, mac);
  942. return enic_dev_status_to_errno(err);
  943. }
  944. } else
  945. return -EINVAL;
  946. }
  947. static int enic_set_vf_port(struct net_device *netdev, int vf,
  948. struct nlattr *port[])
  949. {
  950. struct enic *enic = netdev_priv(netdev);
  951. struct enic_port_profile prev_pp;
  952. struct enic_port_profile *pp;
  953. int err = 0, restore_pp = 1;
  954. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  955. if (err)
  956. return err;
  957. if (!port[IFLA_PORT_REQUEST])
  958. return -EOPNOTSUPP;
  959. memcpy(&prev_pp, pp, sizeof(*enic->pp));
  960. memset(pp, 0, sizeof(*enic->pp));
  961. pp->set |= ENIC_SET_REQUEST;
  962. pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
  963. if (port[IFLA_PORT_PROFILE]) {
  964. pp->set |= ENIC_SET_NAME;
  965. memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
  966. PORT_PROFILE_MAX);
  967. }
  968. if (port[IFLA_PORT_INSTANCE_UUID]) {
  969. pp->set |= ENIC_SET_INSTANCE;
  970. memcpy(pp->instance_uuid,
  971. nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
  972. }
  973. if (port[IFLA_PORT_HOST_UUID]) {
  974. pp->set |= ENIC_SET_HOST;
  975. memcpy(pp->host_uuid,
  976. nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
  977. }
  978. if (vf == PORT_SELF_VF) {
  979. /* Special case handling: mac came from IFLA_VF_MAC */
  980. if (!is_zero_ether_addr(prev_pp.vf_mac))
  981. memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
  982. if (is_zero_ether_addr(netdev->dev_addr))
  983. eth_hw_addr_random(netdev);
  984. } else {
  985. /* SR-IOV VF: get mac from adapter */
  986. ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
  987. vnic_dev_get_mac_addr, pp->mac_addr);
  988. if (err) {
  989. netdev_err(netdev, "Error getting mac for vf %d\n", vf);
  990. memcpy(pp, &prev_pp, sizeof(*pp));
  991. return enic_dev_status_to_errno(err);
  992. }
  993. }
  994. err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
  995. if (err) {
  996. if (restore_pp) {
  997. /* Things are still the way they were: Implicit
  998. * DISASSOCIATE failed
  999. */
  1000. memcpy(pp, &prev_pp, sizeof(*pp));
  1001. } else {
  1002. memset(pp, 0, sizeof(*pp));
  1003. if (vf == PORT_SELF_VF)
  1004. eth_zero_addr(netdev->dev_addr);
  1005. }
  1006. } else {
  1007. /* Set flag to indicate that the port assoc/disassoc
  1008. * request has been sent out to fw
  1009. */
  1010. pp->set |= ENIC_PORT_REQUEST_APPLIED;
  1011. /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
  1012. if (pp->request == PORT_REQUEST_DISASSOCIATE) {
  1013. eth_zero_addr(pp->mac_addr);
  1014. if (vf == PORT_SELF_VF)
  1015. eth_zero_addr(netdev->dev_addr);
  1016. }
  1017. }
  1018. if (vf == PORT_SELF_VF)
  1019. eth_zero_addr(pp->vf_mac);
  1020. return err;
  1021. }
  1022. static int enic_get_vf_port(struct net_device *netdev, int vf,
  1023. struct sk_buff *skb)
  1024. {
  1025. struct enic *enic = netdev_priv(netdev);
  1026. u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
  1027. struct enic_port_profile *pp;
  1028. int err;
  1029. ENIC_PP_BY_INDEX(enic, vf, pp, &err);
  1030. if (err)
  1031. return err;
  1032. if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
  1033. return -ENODATA;
  1034. err = enic_process_get_pp_request(enic, vf, pp->request, &response);
  1035. if (err)
  1036. return err;
  1037. if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
  1038. nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
  1039. ((pp->set & ENIC_SET_NAME) &&
  1040. nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
  1041. ((pp->set & ENIC_SET_INSTANCE) &&
  1042. nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
  1043. pp->instance_uuid)) ||
  1044. ((pp->set & ENIC_SET_HOST) &&
  1045. nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
  1046. goto nla_put_failure;
  1047. return 0;
  1048. nla_put_failure:
  1049. return -EMSGSIZE;
  1050. }
  1051. static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
  1052. {
  1053. struct enic *enic = vnic_dev_priv(rq->vdev);
  1054. if (!buf->os_buf)
  1055. return;
  1056. pci_unmap_single(enic->pdev, buf->dma_addr,
  1057. buf->len, PCI_DMA_FROMDEVICE);
  1058. dev_kfree_skb_any(buf->os_buf);
  1059. buf->os_buf = NULL;
  1060. }
  1061. static int enic_rq_alloc_buf(struct vnic_rq *rq)
  1062. {
  1063. struct enic *enic = vnic_dev_priv(rq->vdev);
  1064. struct net_device *netdev = enic->netdev;
  1065. struct sk_buff *skb;
  1066. unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
  1067. unsigned int os_buf_index = 0;
  1068. dma_addr_t dma_addr;
  1069. struct vnic_rq_buf *buf = rq->to_use;
  1070. if (buf->os_buf) {
  1071. enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
  1072. buf->len);
  1073. return 0;
  1074. }
  1075. skb = netdev_alloc_skb_ip_align(netdev, len);
  1076. if (!skb)
  1077. return -ENOMEM;
  1078. dma_addr = pci_map_single(enic->pdev, skb->data, len,
  1079. PCI_DMA_FROMDEVICE);
  1080. if (unlikely(enic_dma_map_check(enic, dma_addr))) {
  1081. dev_kfree_skb(skb);
  1082. return -ENOMEM;
  1083. }
  1084. enic_queue_rq_desc(rq, skb, os_buf_index,
  1085. dma_addr, len);
  1086. return 0;
  1087. }
  1088. static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
  1089. u32 pkt_len)
  1090. {
  1091. if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
  1092. pkt_size->large_pkt_bytes_cnt += pkt_len;
  1093. else
  1094. pkt_size->small_pkt_bytes_cnt += pkt_len;
  1095. }
  1096. static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
  1097. struct vnic_rq_buf *buf, u16 len)
  1098. {
  1099. struct enic *enic = netdev_priv(netdev);
  1100. struct sk_buff *new_skb;
  1101. if (len > enic->rx_copybreak)
  1102. return false;
  1103. new_skb = netdev_alloc_skb_ip_align(netdev, len);
  1104. if (!new_skb)
  1105. return false;
  1106. pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
  1107. DMA_FROM_DEVICE);
  1108. memcpy(new_skb->data, (*skb)->data, len);
  1109. *skb = new_skb;
  1110. return true;
  1111. }
  1112. static void enic_rq_indicate_buf(struct vnic_rq *rq,
  1113. struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
  1114. int skipped, void *opaque)
  1115. {
  1116. struct enic *enic = vnic_dev_priv(rq->vdev);
  1117. struct net_device *netdev = enic->netdev;
  1118. struct sk_buff *skb;
  1119. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  1120. u8 type, color, eop, sop, ingress_port, vlan_stripped;
  1121. u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
  1122. u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
  1123. u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
  1124. u8 packet_error;
  1125. u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
  1126. u32 rss_hash;
  1127. bool outer_csum_ok = true, encap = false;
  1128. if (skipped)
  1129. return;
  1130. skb = buf->os_buf;
  1131. cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
  1132. &type, &color, &q_number, &completed_index,
  1133. &ingress_port, &fcoe, &eop, &sop, &rss_type,
  1134. &csum_not_calc, &rss_hash, &bytes_written,
  1135. &packet_error, &vlan_stripped, &vlan_tci, &checksum,
  1136. &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
  1137. &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
  1138. &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
  1139. &fcs_ok);
  1140. if (packet_error) {
  1141. if (!fcs_ok) {
  1142. if (bytes_written > 0)
  1143. enic->rq_bad_fcs++;
  1144. else if (bytes_written == 0)
  1145. enic->rq_truncated_pkts++;
  1146. }
  1147. pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
  1148. PCI_DMA_FROMDEVICE);
  1149. dev_kfree_skb_any(skb);
  1150. buf->os_buf = NULL;
  1151. return;
  1152. }
  1153. if (eop && bytes_written > 0) {
  1154. /* Good receive
  1155. */
  1156. if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
  1157. buf->os_buf = NULL;
  1158. pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
  1159. PCI_DMA_FROMDEVICE);
  1160. }
  1161. prefetch(skb->data - NET_IP_ALIGN);
  1162. skb_put(skb, bytes_written);
  1163. skb->protocol = eth_type_trans(skb, netdev);
  1164. skb_record_rx_queue(skb, q_number);
  1165. if ((netdev->features & NETIF_F_RXHASH) && rss_hash &&
  1166. (type == 3)) {
  1167. switch (rss_type) {
  1168. case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4:
  1169. case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6:
  1170. case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX:
  1171. skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L4);
  1172. break;
  1173. case CQ_ENET_RQ_DESC_RSS_TYPE_IPv4:
  1174. case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6:
  1175. case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX:
  1176. skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L3);
  1177. break;
  1178. }
  1179. }
  1180. if (enic->vxlan.vxlan_udp_port_number) {
  1181. switch (enic->vxlan.patch_level) {
  1182. case 0:
  1183. if (fcoe) {
  1184. encap = true;
  1185. outer_csum_ok = fcoe_fc_crc_ok;
  1186. }
  1187. break;
  1188. case 2:
  1189. if ((type == 7) &&
  1190. (rss_hash & BIT(0))) {
  1191. encap = true;
  1192. outer_csum_ok = (rss_hash & BIT(1)) &&
  1193. (rss_hash & BIT(2));
  1194. }
  1195. break;
  1196. }
  1197. }
  1198. /* Hardware does not provide whole packet checksum. It only
  1199. * provides pseudo checksum. Since hw validates the packet
  1200. * checksum but not provide us the checksum value. use
  1201. * CHECSUM_UNNECESSARY.
  1202. *
  1203. * In case of encap pkt tcp_udp_csum_ok/tcp_udp_csum_ok is
  1204. * inner csum_ok. outer_csum_ok is set by hw when outer udp
  1205. * csum is correct or is zero.
  1206. */
  1207. if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc &&
  1208. tcp_udp_csum_ok && ipv4_csum_ok && outer_csum_ok) {
  1209. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1210. skb->csum_level = encap;
  1211. }
  1212. if (vlan_stripped)
  1213. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
  1214. skb_mark_napi_id(skb, &enic->napi[rq->index]);
  1215. if (!(netdev->features & NETIF_F_GRO))
  1216. netif_receive_skb(skb);
  1217. else
  1218. napi_gro_receive(&enic->napi[q_number], skb);
  1219. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1220. enic_intr_update_pkt_size(&cq->pkt_size_counter,
  1221. bytes_written);
  1222. } else {
  1223. /* Buffer overflow
  1224. */
  1225. pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
  1226. PCI_DMA_FROMDEVICE);
  1227. dev_kfree_skb_any(skb);
  1228. buf->os_buf = NULL;
  1229. }
  1230. }
  1231. static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  1232. u8 type, u16 q_number, u16 completed_index, void *opaque)
  1233. {
  1234. struct enic *enic = vnic_dev_priv(vdev);
  1235. vnic_rq_service(&enic->rq[q_number], cq_desc,
  1236. completed_index, VNIC_RQ_RETURN_DESC,
  1237. enic_rq_indicate_buf, opaque);
  1238. return 0;
  1239. }
  1240. static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
  1241. {
  1242. unsigned int intr = enic_msix_rq_intr(enic, rq->index);
  1243. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  1244. u32 timer = cq->tobe_rx_coal_timeval;
  1245. if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
  1246. vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
  1247. cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
  1248. }
  1249. }
  1250. static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
  1251. {
  1252. struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
  1253. struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
  1254. struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
  1255. int index;
  1256. u32 timer;
  1257. u32 range_start;
  1258. u32 traffic;
  1259. u64 delta;
  1260. ktime_t now = ktime_get();
  1261. delta = ktime_us_delta(now, cq->prev_ts);
  1262. if (delta < ENIC_AIC_TS_BREAK)
  1263. return;
  1264. cq->prev_ts = now;
  1265. traffic = pkt_size_counter->large_pkt_bytes_cnt +
  1266. pkt_size_counter->small_pkt_bytes_cnt;
  1267. /* The table takes Mbps
  1268. * traffic *= 8 => bits
  1269. * traffic *= (10^6 / delta) => bps
  1270. * traffic /= 10^6 => Mbps
  1271. *
  1272. * Combining, traffic *= (8 / delta)
  1273. */
  1274. traffic <<= 3;
  1275. traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
  1276. for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
  1277. if (traffic < mod_table[index].rx_rate)
  1278. break;
  1279. range_start = (pkt_size_counter->small_pkt_bytes_cnt >
  1280. pkt_size_counter->large_pkt_bytes_cnt << 1) ?
  1281. rx_coal->small_pkt_range_start :
  1282. rx_coal->large_pkt_range_start;
  1283. timer = range_start + ((rx_coal->range_end - range_start) *
  1284. mod_table[index].range_percent / 100);
  1285. /* Damping */
  1286. cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
  1287. pkt_size_counter->large_pkt_bytes_cnt = 0;
  1288. pkt_size_counter->small_pkt_bytes_cnt = 0;
  1289. }
  1290. static int enic_poll(struct napi_struct *napi, int budget)
  1291. {
  1292. struct net_device *netdev = napi->dev;
  1293. struct enic *enic = netdev_priv(netdev);
  1294. unsigned int cq_rq = enic_cq_rq(enic, 0);
  1295. unsigned int cq_wq = enic_cq_wq(enic, 0);
  1296. unsigned int intr = enic_legacy_io_intr();
  1297. unsigned int rq_work_to_do = budget;
  1298. unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
  1299. unsigned int work_done, rq_work_done = 0, wq_work_done;
  1300. int err;
  1301. wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
  1302. enic_wq_service, NULL);
  1303. if (budget > 0)
  1304. rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
  1305. rq_work_to_do, enic_rq_service, NULL);
  1306. /* Accumulate intr event credits for this polling
  1307. * cycle. An intr event is the completion of a
  1308. * a WQ or RQ packet.
  1309. */
  1310. work_done = rq_work_done + wq_work_done;
  1311. if (work_done > 0)
  1312. vnic_intr_return_credits(&enic->intr[intr],
  1313. work_done,
  1314. 0 /* don't unmask intr */,
  1315. 0 /* don't reset intr timer */);
  1316. err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
  1317. /* Buffer allocation failed. Stay in polling
  1318. * mode so we can try to fill the ring again.
  1319. */
  1320. if (err)
  1321. rq_work_done = rq_work_to_do;
  1322. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1323. /* Call the function which refreshes the intr coalescing timer
  1324. * value based on the traffic.
  1325. */
  1326. enic_calc_int_moderation(enic, &enic->rq[0]);
  1327. if ((rq_work_done < budget) && napi_complete_done(napi, rq_work_done)) {
  1328. /* Some work done, but not enough to stay in polling,
  1329. * exit polling
  1330. */
  1331. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1332. enic_set_int_moderation(enic, &enic->rq[0]);
  1333. vnic_intr_unmask(&enic->intr[intr]);
  1334. }
  1335. return rq_work_done;
  1336. }
  1337. #ifdef CONFIG_RFS_ACCEL
  1338. static void enic_free_rx_cpu_rmap(struct enic *enic)
  1339. {
  1340. free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
  1341. enic->netdev->rx_cpu_rmap = NULL;
  1342. }
  1343. static void enic_set_rx_cpu_rmap(struct enic *enic)
  1344. {
  1345. int i, res;
  1346. if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
  1347. enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
  1348. if (unlikely(!enic->netdev->rx_cpu_rmap))
  1349. return;
  1350. for (i = 0; i < enic->rq_count; i++) {
  1351. res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
  1352. enic->msix_entry[i].vector);
  1353. if (unlikely(res)) {
  1354. enic_free_rx_cpu_rmap(enic);
  1355. return;
  1356. }
  1357. }
  1358. }
  1359. }
  1360. #else
  1361. static void enic_free_rx_cpu_rmap(struct enic *enic)
  1362. {
  1363. }
  1364. static void enic_set_rx_cpu_rmap(struct enic *enic)
  1365. {
  1366. }
  1367. #endif /* CONFIG_RFS_ACCEL */
  1368. static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
  1369. {
  1370. struct net_device *netdev = napi->dev;
  1371. struct enic *enic = netdev_priv(netdev);
  1372. unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
  1373. struct vnic_wq *wq = &enic->wq[wq_index];
  1374. unsigned int cq;
  1375. unsigned int intr;
  1376. unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
  1377. unsigned int wq_work_done;
  1378. unsigned int wq_irq;
  1379. wq_irq = wq->index;
  1380. cq = enic_cq_wq(enic, wq_irq);
  1381. intr = enic_msix_wq_intr(enic, wq_irq);
  1382. wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
  1383. enic_wq_service, NULL);
  1384. vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
  1385. 0 /* don't unmask intr */,
  1386. 1 /* reset intr timer */);
  1387. if (!wq_work_done) {
  1388. napi_complete(napi);
  1389. vnic_intr_unmask(&enic->intr[intr]);
  1390. return 0;
  1391. }
  1392. return budget;
  1393. }
  1394. static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
  1395. {
  1396. struct net_device *netdev = napi->dev;
  1397. struct enic *enic = netdev_priv(netdev);
  1398. unsigned int rq = (napi - &enic->napi[0]);
  1399. unsigned int cq = enic_cq_rq(enic, rq);
  1400. unsigned int intr = enic_msix_rq_intr(enic, rq);
  1401. unsigned int work_to_do = budget;
  1402. unsigned int work_done = 0;
  1403. int err;
  1404. /* Service RQ
  1405. */
  1406. if (budget > 0)
  1407. work_done = vnic_cq_service(&enic->cq[cq],
  1408. work_to_do, enic_rq_service, NULL);
  1409. /* Return intr event credits for this polling
  1410. * cycle. An intr event is the completion of a
  1411. * RQ packet.
  1412. */
  1413. if (work_done > 0)
  1414. vnic_intr_return_credits(&enic->intr[intr],
  1415. work_done,
  1416. 0 /* don't unmask intr */,
  1417. 0 /* don't reset intr timer */);
  1418. err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
  1419. /* Buffer allocation failed. Stay in polling mode
  1420. * so we can try to fill the ring again.
  1421. */
  1422. if (err)
  1423. work_done = work_to_do;
  1424. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1425. /* Call the function which refreshes the intr coalescing timer
  1426. * value based on the traffic.
  1427. */
  1428. enic_calc_int_moderation(enic, &enic->rq[rq]);
  1429. if ((work_done < budget) && napi_complete_done(napi, work_done)) {
  1430. /* Some work done, but not enough to stay in polling,
  1431. * exit polling
  1432. */
  1433. if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
  1434. enic_set_int_moderation(enic, &enic->rq[rq]);
  1435. vnic_intr_unmask(&enic->intr[intr]);
  1436. }
  1437. return work_done;
  1438. }
  1439. static void enic_notify_timer(struct timer_list *t)
  1440. {
  1441. struct enic *enic = from_timer(enic, t, notify_timer);
  1442. enic_notify_check(enic);
  1443. mod_timer(&enic->notify_timer,
  1444. round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
  1445. }
  1446. static void enic_free_intr(struct enic *enic)
  1447. {
  1448. struct net_device *netdev = enic->netdev;
  1449. unsigned int i;
  1450. enic_free_rx_cpu_rmap(enic);
  1451. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1452. case VNIC_DEV_INTR_MODE_INTX:
  1453. free_irq(enic->pdev->irq, netdev);
  1454. break;
  1455. case VNIC_DEV_INTR_MODE_MSI:
  1456. free_irq(enic->pdev->irq, enic);
  1457. break;
  1458. case VNIC_DEV_INTR_MODE_MSIX:
  1459. for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
  1460. if (enic->msix[i].requested)
  1461. free_irq(enic->msix_entry[i].vector,
  1462. enic->msix[i].devid);
  1463. break;
  1464. default:
  1465. break;
  1466. }
  1467. }
  1468. static int enic_request_intr(struct enic *enic)
  1469. {
  1470. struct net_device *netdev = enic->netdev;
  1471. unsigned int i, intr;
  1472. int err = 0;
  1473. enic_set_rx_cpu_rmap(enic);
  1474. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1475. case VNIC_DEV_INTR_MODE_INTX:
  1476. err = request_irq(enic->pdev->irq, enic_isr_legacy,
  1477. IRQF_SHARED, netdev->name, netdev);
  1478. break;
  1479. case VNIC_DEV_INTR_MODE_MSI:
  1480. err = request_irq(enic->pdev->irq, enic_isr_msi,
  1481. 0, netdev->name, enic);
  1482. break;
  1483. case VNIC_DEV_INTR_MODE_MSIX:
  1484. for (i = 0; i < enic->rq_count; i++) {
  1485. intr = enic_msix_rq_intr(enic, i);
  1486. snprintf(enic->msix[intr].devname,
  1487. sizeof(enic->msix[intr].devname),
  1488. "%s-rx-%u", netdev->name, i);
  1489. enic->msix[intr].isr = enic_isr_msix;
  1490. enic->msix[intr].devid = &enic->napi[i];
  1491. }
  1492. for (i = 0; i < enic->wq_count; i++) {
  1493. int wq = enic_cq_wq(enic, i);
  1494. intr = enic_msix_wq_intr(enic, i);
  1495. snprintf(enic->msix[intr].devname,
  1496. sizeof(enic->msix[intr].devname),
  1497. "%s-tx-%u", netdev->name, i);
  1498. enic->msix[intr].isr = enic_isr_msix;
  1499. enic->msix[intr].devid = &enic->napi[wq];
  1500. }
  1501. intr = enic_msix_err_intr(enic);
  1502. snprintf(enic->msix[intr].devname,
  1503. sizeof(enic->msix[intr].devname),
  1504. "%s-err", netdev->name);
  1505. enic->msix[intr].isr = enic_isr_msix_err;
  1506. enic->msix[intr].devid = enic;
  1507. intr = enic_msix_notify_intr(enic);
  1508. snprintf(enic->msix[intr].devname,
  1509. sizeof(enic->msix[intr].devname),
  1510. "%s-notify", netdev->name);
  1511. enic->msix[intr].isr = enic_isr_msix_notify;
  1512. enic->msix[intr].devid = enic;
  1513. for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
  1514. enic->msix[i].requested = 0;
  1515. for (i = 0; i < enic->intr_count; i++) {
  1516. err = request_irq(enic->msix_entry[i].vector,
  1517. enic->msix[i].isr, 0,
  1518. enic->msix[i].devname,
  1519. enic->msix[i].devid);
  1520. if (err) {
  1521. enic_free_intr(enic);
  1522. break;
  1523. }
  1524. enic->msix[i].requested = 1;
  1525. }
  1526. break;
  1527. default:
  1528. break;
  1529. }
  1530. return err;
  1531. }
  1532. static void enic_synchronize_irqs(struct enic *enic)
  1533. {
  1534. unsigned int i;
  1535. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1536. case VNIC_DEV_INTR_MODE_INTX:
  1537. case VNIC_DEV_INTR_MODE_MSI:
  1538. synchronize_irq(enic->pdev->irq);
  1539. break;
  1540. case VNIC_DEV_INTR_MODE_MSIX:
  1541. for (i = 0; i < enic->intr_count; i++)
  1542. synchronize_irq(enic->msix_entry[i].vector);
  1543. break;
  1544. default:
  1545. break;
  1546. }
  1547. }
  1548. static void enic_set_rx_coal_setting(struct enic *enic)
  1549. {
  1550. unsigned int speed;
  1551. int index = -1;
  1552. struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
  1553. /* 1. Read the link speed from fw
  1554. * 2. Pick the default range for the speed
  1555. * 3. Update it in enic->rx_coalesce_setting
  1556. */
  1557. speed = vnic_dev_port_speed(enic->vdev);
  1558. if (ENIC_LINK_SPEED_10G < speed)
  1559. index = ENIC_LINK_40G_INDEX;
  1560. else if (ENIC_LINK_SPEED_4G < speed)
  1561. index = ENIC_LINK_10G_INDEX;
  1562. else
  1563. index = ENIC_LINK_4G_INDEX;
  1564. rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
  1565. rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
  1566. rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
  1567. /* Start with the value provided by UCSM */
  1568. for (index = 0; index < enic->rq_count; index++)
  1569. enic->cq[index].cur_rx_coal_timeval =
  1570. enic->config.intr_timer_usec;
  1571. rx_coal->use_adaptive_rx_coalesce = 1;
  1572. }
  1573. static int enic_dev_notify_set(struct enic *enic)
  1574. {
  1575. int err;
  1576. spin_lock_bh(&enic->devcmd_lock);
  1577. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1578. case VNIC_DEV_INTR_MODE_INTX:
  1579. err = vnic_dev_notify_set(enic->vdev,
  1580. enic_legacy_notify_intr());
  1581. break;
  1582. case VNIC_DEV_INTR_MODE_MSIX:
  1583. err = vnic_dev_notify_set(enic->vdev,
  1584. enic_msix_notify_intr(enic));
  1585. break;
  1586. default:
  1587. err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
  1588. break;
  1589. }
  1590. spin_unlock_bh(&enic->devcmd_lock);
  1591. return err;
  1592. }
  1593. static void enic_notify_timer_start(struct enic *enic)
  1594. {
  1595. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1596. case VNIC_DEV_INTR_MODE_MSI:
  1597. mod_timer(&enic->notify_timer, jiffies);
  1598. break;
  1599. default:
  1600. /* Using intr for notification for INTx/MSI-X */
  1601. break;
  1602. }
  1603. }
  1604. /* rtnl lock is held, process context */
  1605. static int enic_open(struct net_device *netdev)
  1606. {
  1607. struct enic *enic = netdev_priv(netdev);
  1608. unsigned int i;
  1609. int err;
  1610. err = enic_request_intr(enic);
  1611. if (err) {
  1612. netdev_err(netdev, "Unable to request irq.\n");
  1613. return err;
  1614. }
  1615. enic_init_affinity_hint(enic);
  1616. enic_set_affinity_hint(enic);
  1617. err = enic_dev_notify_set(enic);
  1618. if (err) {
  1619. netdev_err(netdev,
  1620. "Failed to alloc notify buffer, aborting.\n");
  1621. goto err_out_free_intr;
  1622. }
  1623. for (i = 0; i < enic->rq_count; i++) {
  1624. /* enable rq before updating rq desc */
  1625. vnic_rq_enable(&enic->rq[i]);
  1626. vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
  1627. /* Need at least one buffer on ring to get going */
  1628. if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
  1629. netdev_err(netdev, "Unable to alloc receive buffers\n");
  1630. err = -ENOMEM;
  1631. goto err_out_free_rq;
  1632. }
  1633. }
  1634. for (i = 0; i < enic->wq_count; i++)
  1635. vnic_wq_enable(&enic->wq[i]);
  1636. if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
  1637. enic_dev_add_station_addr(enic);
  1638. enic_set_rx_mode(netdev);
  1639. netif_tx_wake_all_queues(netdev);
  1640. for (i = 0; i < enic->rq_count; i++)
  1641. napi_enable(&enic->napi[i]);
  1642. if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
  1643. for (i = 0; i < enic->wq_count; i++)
  1644. napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
  1645. enic_dev_enable(enic);
  1646. for (i = 0; i < enic->intr_count; i++)
  1647. vnic_intr_unmask(&enic->intr[i]);
  1648. enic_notify_timer_start(enic);
  1649. enic_rfs_flw_tbl_init(enic);
  1650. return 0;
  1651. err_out_free_rq:
  1652. for (i = 0; i < enic->rq_count; i++) {
  1653. err = vnic_rq_disable(&enic->rq[i]);
  1654. if (err)
  1655. return err;
  1656. vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
  1657. }
  1658. enic_dev_notify_unset(enic);
  1659. err_out_free_intr:
  1660. enic_unset_affinity_hint(enic);
  1661. enic_free_intr(enic);
  1662. return err;
  1663. }
  1664. /* rtnl lock is held, process context */
  1665. static int enic_stop(struct net_device *netdev)
  1666. {
  1667. struct enic *enic = netdev_priv(netdev);
  1668. unsigned int i;
  1669. int err;
  1670. for (i = 0; i < enic->intr_count; i++) {
  1671. vnic_intr_mask(&enic->intr[i]);
  1672. (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
  1673. }
  1674. enic_synchronize_irqs(enic);
  1675. del_timer_sync(&enic->notify_timer);
  1676. enic_rfs_flw_tbl_free(enic);
  1677. enic_dev_disable(enic);
  1678. for (i = 0; i < enic->rq_count; i++)
  1679. napi_disable(&enic->napi[i]);
  1680. netif_carrier_off(netdev);
  1681. netif_tx_disable(netdev);
  1682. if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
  1683. for (i = 0; i < enic->wq_count; i++)
  1684. napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
  1685. if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
  1686. enic_dev_del_station_addr(enic);
  1687. for (i = 0; i < enic->wq_count; i++) {
  1688. err = vnic_wq_disable(&enic->wq[i]);
  1689. if (err)
  1690. return err;
  1691. }
  1692. for (i = 0; i < enic->rq_count; i++) {
  1693. err = vnic_rq_disable(&enic->rq[i]);
  1694. if (err)
  1695. return err;
  1696. }
  1697. enic_dev_notify_unset(enic);
  1698. enic_unset_affinity_hint(enic);
  1699. enic_free_intr(enic);
  1700. for (i = 0; i < enic->wq_count; i++)
  1701. vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
  1702. for (i = 0; i < enic->rq_count; i++)
  1703. vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
  1704. for (i = 0; i < enic->cq_count; i++)
  1705. vnic_cq_clean(&enic->cq[i]);
  1706. for (i = 0; i < enic->intr_count; i++)
  1707. vnic_intr_clean(&enic->intr[i]);
  1708. return 0;
  1709. }
  1710. static int enic_change_mtu(struct net_device *netdev, int new_mtu)
  1711. {
  1712. struct enic *enic = netdev_priv(netdev);
  1713. int running = netif_running(netdev);
  1714. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
  1715. return -EOPNOTSUPP;
  1716. if (running)
  1717. enic_stop(netdev);
  1718. netdev->mtu = new_mtu;
  1719. if (netdev->mtu > enic->port_mtu)
  1720. netdev_warn(netdev,
  1721. "interface MTU (%d) set higher than port MTU (%d)\n",
  1722. netdev->mtu, enic->port_mtu);
  1723. if (running)
  1724. enic_open(netdev);
  1725. return 0;
  1726. }
  1727. static void enic_change_mtu_work(struct work_struct *work)
  1728. {
  1729. struct enic *enic = container_of(work, struct enic, change_mtu_work);
  1730. struct net_device *netdev = enic->netdev;
  1731. int new_mtu = vnic_dev_mtu(enic->vdev);
  1732. int err;
  1733. unsigned int i;
  1734. new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
  1735. rtnl_lock();
  1736. /* Stop RQ */
  1737. del_timer_sync(&enic->notify_timer);
  1738. for (i = 0; i < enic->rq_count; i++)
  1739. napi_disable(&enic->napi[i]);
  1740. vnic_intr_mask(&enic->intr[0]);
  1741. enic_synchronize_irqs(enic);
  1742. err = vnic_rq_disable(&enic->rq[0]);
  1743. if (err) {
  1744. rtnl_unlock();
  1745. netdev_err(netdev, "Unable to disable RQ.\n");
  1746. return;
  1747. }
  1748. vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
  1749. vnic_cq_clean(&enic->cq[0]);
  1750. vnic_intr_clean(&enic->intr[0]);
  1751. /* Fill RQ with new_mtu-sized buffers */
  1752. netdev->mtu = new_mtu;
  1753. vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
  1754. /* Need at least one buffer on ring to get going */
  1755. if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
  1756. rtnl_unlock();
  1757. netdev_err(netdev, "Unable to alloc receive buffers.\n");
  1758. return;
  1759. }
  1760. /* Start RQ */
  1761. vnic_rq_enable(&enic->rq[0]);
  1762. napi_enable(&enic->napi[0]);
  1763. vnic_intr_unmask(&enic->intr[0]);
  1764. enic_notify_timer_start(enic);
  1765. rtnl_unlock();
  1766. netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
  1767. }
  1768. #ifdef CONFIG_NET_POLL_CONTROLLER
  1769. static void enic_poll_controller(struct net_device *netdev)
  1770. {
  1771. struct enic *enic = netdev_priv(netdev);
  1772. struct vnic_dev *vdev = enic->vdev;
  1773. unsigned int i, intr;
  1774. switch (vnic_dev_get_intr_mode(vdev)) {
  1775. case VNIC_DEV_INTR_MODE_MSIX:
  1776. for (i = 0; i < enic->rq_count; i++) {
  1777. intr = enic_msix_rq_intr(enic, i);
  1778. enic_isr_msix(enic->msix_entry[intr].vector,
  1779. &enic->napi[i]);
  1780. }
  1781. for (i = 0; i < enic->wq_count; i++) {
  1782. intr = enic_msix_wq_intr(enic, i);
  1783. enic_isr_msix(enic->msix_entry[intr].vector,
  1784. &enic->napi[enic_cq_wq(enic, i)]);
  1785. }
  1786. break;
  1787. case VNIC_DEV_INTR_MODE_MSI:
  1788. enic_isr_msi(enic->pdev->irq, enic);
  1789. break;
  1790. case VNIC_DEV_INTR_MODE_INTX:
  1791. enic_isr_legacy(enic->pdev->irq, netdev);
  1792. break;
  1793. default:
  1794. break;
  1795. }
  1796. }
  1797. #endif
  1798. static int enic_dev_wait(struct vnic_dev *vdev,
  1799. int (*start)(struct vnic_dev *, int),
  1800. int (*finished)(struct vnic_dev *, int *),
  1801. int arg)
  1802. {
  1803. unsigned long time;
  1804. int done;
  1805. int err;
  1806. BUG_ON(in_interrupt());
  1807. err = start(vdev, arg);
  1808. if (err)
  1809. return err;
  1810. /* Wait for func to complete...2 seconds max
  1811. */
  1812. time = jiffies + (HZ * 2);
  1813. do {
  1814. err = finished(vdev, &done);
  1815. if (err)
  1816. return err;
  1817. if (done)
  1818. return 0;
  1819. schedule_timeout_uninterruptible(HZ / 10);
  1820. } while (time_after(time, jiffies));
  1821. return -ETIMEDOUT;
  1822. }
  1823. static int enic_dev_open(struct enic *enic)
  1824. {
  1825. int err;
  1826. u32 flags = CMD_OPENF_IG_DESCCACHE;
  1827. err = enic_dev_wait(enic->vdev, vnic_dev_open,
  1828. vnic_dev_open_done, flags);
  1829. if (err)
  1830. dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
  1831. err);
  1832. return err;
  1833. }
  1834. static int enic_dev_soft_reset(struct enic *enic)
  1835. {
  1836. int err;
  1837. err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset,
  1838. vnic_dev_soft_reset_done, 0);
  1839. if (err)
  1840. netdev_err(enic->netdev, "vNIC soft reset failed, err %d\n",
  1841. err);
  1842. return err;
  1843. }
  1844. static int enic_dev_hang_reset(struct enic *enic)
  1845. {
  1846. int err;
  1847. err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
  1848. vnic_dev_hang_reset_done, 0);
  1849. if (err)
  1850. netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
  1851. err);
  1852. return err;
  1853. }
  1854. int __enic_set_rsskey(struct enic *enic)
  1855. {
  1856. union vnic_rss_key *rss_key_buf_va;
  1857. dma_addr_t rss_key_buf_pa;
  1858. int i, kidx, bidx, err;
  1859. rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
  1860. sizeof(union vnic_rss_key),
  1861. &rss_key_buf_pa);
  1862. if (!rss_key_buf_va)
  1863. return -ENOMEM;
  1864. for (i = 0; i < ENIC_RSS_LEN; i++) {
  1865. kidx = i / ENIC_RSS_BYTES_PER_KEY;
  1866. bidx = i % ENIC_RSS_BYTES_PER_KEY;
  1867. rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
  1868. }
  1869. spin_lock_bh(&enic->devcmd_lock);
  1870. err = enic_set_rss_key(enic,
  1871. rss_key_buf_pa,
  1872. sizeof(union vnic_rss_key));
  1873. spin_unlock_bh(&enic->devcmd_lock);
  1874. pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
  1875. rss_key_buf_va, rss_key_buf_pa);
  1876. return err;
  1877. }
  1878. static int enic_set_rsskey(struct enic *enic)
  1879. {
  1880. netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
  1881. return __enic_set_rsskey(enic);
  1882. }
  1883. static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
  1884. {
  1885. dma_addr_t rss_cpu_buf_pa;
  1886. union vnic_rss_cpu *rss_cpu_buf_va = NULL;
  1887. unsigned int i;
  1888. int err;
  1889. rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
  1890. sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
  1891. if (!rss_cpu_buf_va)
  1892. return -ENOMEM;
  1893. for (i = 0; i < (1 << rss_hash_bits); i++)
  1894. (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
  1895. spin_lock_bh(&enic->devcmd_lock);
  1896. err = enic_set_rss_cpu(enic,
  1897. rss_cpu_buf_pa,
  1898. sizeof(union vnic_rss_cpu));
  1899. spin_unlock_bh(&enic->devcmd_lock);
  1900. pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
  1901. rss_cpu_buf_va, rss_cpu_buf_pa);
  1902. return err;
  1903. }
  1904. static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
  1905. u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
  1906. {
  1907. const u8 tso_ipid_split_en = 0;
  1908. const u8 ig_vlan_strip_en = 1;
  1909. int err;
  1910. /* Enable VLAN tag stripping.
  1911. */
  1912. spin_lock_bh(&enic->devcmd_lock);
  1913. err = enic_set_nic_cfg(enic,
  1914. rss_default_cpu, rss_hash_type,
  1915. rss_hash_bits, rss_base_cpu,
  1916. rss_enable, tso_ipid_split_en,
  1917. ig_vlan_strip_en);
  1918. spin_unlock_bh(&enic->devcmd_lock);
  1919. return err;
  1920. }
  1921. static int enic_set_rss_nic_cfg(struct enic *enic)
  1922. {
  1923. struct device *dev = enic_get_dev(enic);
  1924. const u8 rss_default_cpu = 0;
  1925. u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
  1926. NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
  1927. NIC_CFG_RSS_HASH_TYPE_IPV6 |
  1928. NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
  1929. const u8 rss_hash_bits = 7;
  1930. const u8 rss_base_cpu = 0;
  1931. u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
  1932. if (vnic_dev_capable_udp_rss(enic->vdev))
  1933. rss_hash_type |= NIC_CFG_RSS_HASH_TYPE_UDP;
  1934. if (rss_enable) {
  1935. if (!enic_set_rsskey(enic)) {
  1936. if (enic_set_rsscpu(enic, rss_hash_bits)) {
  1937. rss_enable = 0;
  1938. dev_warn(dev, "RSS disabled, "
  1939. "Failed to set RSS cpu indirection table.");
  1940. }
  1941. } else {
  1942. rss_enable = 0;
  1943. dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
  1944. }
  1945. }
  1946. return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
  1947. rss_hash_bits, rss_base_cpu, rss_enable);
  1948. }
  1949. static void enic_reset(struct work_struct *work)
  1950. {
  1951. struct enic *enic = container_of(work, struct enic, reset);
  1952. if (!netif_running(enic->netdev))
  1953. return;
  1954. rtnl_lock();
  1955. spin_lock(&enic->enic_api_lock);
  1956. enic_stop(enic->netdev);
  1957. enic_dev_soft_reset(enic);
  1958. enic_reset_addr_lists(enic);
  1959. enic_init_vnic_resources(enic);
  1960. enic_set_rss_nic_cfg(enic);
  1961. enic_dev_set_ig_vlan_rewrite_mode(enic);
  1962. enic_open(enic->netdev);
  1963. spin_unlock(&enic->enic_api_lock);
  1964. call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
  1965. rtnl_unlock();
  1966. }
  1967. static void enic_tx_hang_reset(struct work_struct *work)
  1968. {
  1969. struct enic *enic = container_of(work, struct enic, tx_hang_reset);
  1970. rtnl_lock();
  1971. spin_lock(&enic->enic_api_lock);
  1972. enic_dev_hang_notify(enic);
  1973. enic_stop(enic->netdev);
  1974. enic_dev_hang_reset(enic);
  1975. enic_reset_addr_lists(enic);
  1976. enic_init_vnic_resources(enic);
  1977. enic_set_rss_nic_cfg(enic);
  1978. enic_dev_set_ig_vlan_rewrite_mode(enic);
  1979. enic_open(enic->netdev);
  1980. spin_unlock(&enic->enic_api_lock);
  1981. call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
  1982. rtnl_unlock();
  1983. }
  1984. static int enic_set_intr_mode(struct enic *enic)
  1985. {
  1986. unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
  1987. unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
  1988. unsigned int i;
  1989. /* Set interrupt mode (INTx, MSI, MSI-X) depending
  1990. * on system capabilities.
  1991. *
  1992. * Try MSI-X first
  1993. *
  1994. * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
  1995. * (the second to last INTR is used for WQ/RQ errors)
  1996. * (the last INTR is used for notifications)
  1997. */
  1998. BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
  1999. for (i = 0; i < n + m + 2; i++)
  2000. enic->msix_entry[i].entry = i;
  2001. /* Use multiple RQs if RSS is enabled
  2002. */
  2003. if (ENIC_SETTING(enic, RSS) &&
  2004. enic->config.intr_mode < 1 &&
  2005. enic->rq_count >= n &&
  2006. enic->wq_count >= m &&
  2007. enic->cq_count >= n + m &&
  2008. enic->intr_count >= n + m + 2) {
  2009. if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
  2010. n + m + 2, n + m + 2) > 0) {
  2011. enic->rq_count = n;
  2012. enic->wq_count = m;
  2013. enic->cq_count = n + m;
  2014. enic->intr_count = n + m + 2;
  2015. vnic_dev_set_intr_mode(enic->vdev,
  2016. VNIC_DEV_INTR_MODE_MSIX);
  2017. return 0;
  2018. }
  2019. }
  2020. if (enic->config.intr_mode < 1 &&
  2021. enic->rq_count >= 1 &&
  2022. enic->wq_count >= m &&
  2023. enic->cq_count >= 1 + m &&
  2024. enic->intr_count >= 1 + m + 2) {
  2025. if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
  2026. 1 + m + 2, 1 + m + 2) > 0) {
  2027. enic->rq_count = 1;
  2028. enic->wq_count = m;
  2029. enic->cq_count = 1 + m;
  2030. enic->intr_count = 1 + m + 2;
  2031. vnic_dev_set_intr_mode(enic->vdev,
  2032. VNIC_DEV_INTR_MODE_MSIX);
  2033. return 0;
  2034. }
  2035. }
  2036. /* Next try MSI
  2037. *
  2038. * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
  2039. */
  2040. if (enic->config.intr_mode < 2 &&
  2041. enic->rq_count >= 1 &&
  2042. enic->wq_count >= 1 &&
  2043. enic->cq_count >= 2 &&
  2044. enic->intr_count >= 1 &&
  2045. !pci_enable_msi(enic->pdev)) {
  2046. enic->rq_count = 1;
  2047. enic->wq_count = 1;
  2048. enic->cq_count = 2;
  2049. enic->intr_count = 1;
  2050. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
  2051. return 0;
  2052. }
  2053. /* Next try INTx
  2054. *
  2055. * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
  2056. * (the first INTR is used for WQ/RQ)
  2057. * (the second INTR is used for WQ/RQ errors)
  2058. * (the last INTR is used for notifications)
  2059. */
  2060. if (enic->config.intr_mode < 3 &&
  2061. enic->rq_count >= 1 &&
  2062. enic->wq_count >= 1 &&
  2063. enic->cq_count >= 2 &&
  2064. enic->intr_count >= 3) {
  2065. enic->rq_count = 1;
  2066. enic->wq_count = 1;
  2067. enic->cq_count = 2;
  2068. enic->intr_count = 3;
  2069. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
  2070. return 0;
  2071. }
  2072. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  2073. return -EINVAL;
  2074. }
  2075. static void enic_clear_intr_mode(struct enic *enic)
  2076. {
  2077. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  2078. case VNIC_DEV_INTR_MODE_MSIX:
  2079. pci_disable_msix(enic->pdev);
  2080. break;
  2081. case VNIC_DEV_INTR_MODE_MSI:
  2082. pci_disable_msi(enic->pdev);
  2083. break;
  2084. default:
  2085. break;
  2086. }
  2087. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  2088. }
  2089. static const struct net_device_ops enic_netdev_dynamic_ops = {
  2090. .ndo_open = enic_open,
  2091. .ndo_stop = enic_stop,
  2092. .ndo_start_xmit = enic_hard_start_xmit,
  2093. .ndo_get_stats64 = enic_get_stats,
  2094. .ndo_validate_addr = eth_validate_addr,
  2095. .ndo_set_rx_mode = enic_set_rx_mode,
  2096. .ndo_set_mac_address = enic_set_mac_address_dynamic,
  2097. .ndo_change_mtu = enic_change_mtu,
  2098. .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
  2099. .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
  2100. .ndo_tx_timeout = enic_tx_timeout,
  2101. .ndo_set_vf_port = enic_set_vf_port,
  2102. .ndo_get_vf_port = enic_get_vf_port,
  2103. .ndo_set_vf_mac = enic_set_vf_mac,
  2104. #ifdef CONFIG_NET_POLL_CONTROLLER
  2105. .ndo_poll_controller = enic_poll_controller,
  2106. #endif
  2107. #ifdef CONFIG_RFS_ACCEL
  2108. .ndo_rx_flow_steer = enic_rx_flow_steer,
  2109. #endif
  2110. .ndo_udp_tunnel_add = enic_udp_tunnel_add,
  2111. .ndo_udp_tunnel_del = enic_udp_tunnel_del,
  2112. .ndo_features_check = enic_features_check,
  2113. };
  2114. static const struct net_device_ops enic_netdev_ops = {
  2115. .ndo_open = enic_open,
  2116. .ndo_stop = enic_stop,
  2117. .ndo_start_xmit = enic_hard_start_xmit,
  2118. .ndo_get_stats64 = enic_get_stats,
  2119. .ndo_validate_addr = eth_validate_addr,
  2120. .ndo_set_mac_address = enic_set_mac_address,
  2121. .ndo_set_rx_mode = enic_set_rx_mode,
  2122. .ndo_change_mtu = enic_change_mtu,
  2123. .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
  2124. .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
  2125. .ndo_tx_timeout = enic_tx_timeout,
  2126. .ndo_set_vf_port = enic_set_vf_port,
  2127. .ndo_get_vf_port = enic_get_vf_port,
  2128. .ndo_set_vf_mac = enic_set_vf_mac,
  2129. #ifdef CONFIG_NET_POLL_CONTROLLER
  2130. .ndo_poll_controller = enic_poll_controller,
  2131. #endif
  2132. #ifdef CONFIG_RFS_ACCEL
  2133. .ndo_rx_flow_steer = enic_rx_flow_steer,
  2134. #endif
  2135. .ndo_udp_tunnel_add = enic_udp_tunnel_add,
  2136. .ndo_udp_tunnel_del = enic_udp_tunnel_del,
  2137. .ndo_features_check = enic_features_check,
  2138. };
  2139. static void enic_dev_deinit(struct enic *enic)
  2140. {
  2141. unsigned int i;
  2142. for (i = 0; i < enic->rq_count; i++) {
  2143. napi_hash_del(&enic->napi[i]);
  2144. netif_napi_del(&enic->napi[i]);
  2145. }
  2146. if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
  2147. for (i = 0; i < enic->wq_count; i++)
  2148. netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
  2149. enic_free_vnic_resources(enic);
  2150. enic_clear_intr_mode(enic);
  2151. enic_free_affinity_hint(enic);
  2152. }
  2153. static void enic_kdump_kernel_config(struct enic *enic)
  2154. {
  2155. if (is_kdump_kernel()) {
  2156. dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n");
  2157. enic->rq_count = 1;
  2158. enic->wq_count = 1;
  2159. enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS;
  2160. enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS;
  2161. enic->config.mtu = min_t(u16, 1500, enic->config.mtu);
  2162. }
  2163. }
  2164. static int enic_dev_init(struct enic *enic)
  2165. {
  2166. struct device *dev = enic_get_dev(enic);
  2167. struct net_device *netdev = enic->netdev;
  2168. unsigned int i;
  2169. int err;
  2170. /* Get interrupt coalesce timer info */
  2171. err = enic_dev_intr_coal_timer_info(enic);
  2172. if (err) {
  2173. dev_warn(dev, "Using default conversion factor for "
  2174. "interrupt coalesce timer\n");
  2175. vnic_dev_intr_coal_timer_info_default(enic->vdev);
  2176. }
  2177. /* Get vNIC configuration
  2178. */
  2179. err = enic_get_vnic_config(enic);
  2180. if (err) {
  2181. dev_err(dev, "Get vNIC configuration failed, aborting\n");
  2182. return err;
  2183. }
  2184. /* Get available resource counts
  2185. */
  2186. enic_get_res_counts(enic);
  2187. /* modify resource count if we are in kdump_kernel
  2188. */
  2189. enic_kdump_kernel_config(enic);
  2190. /* Set interrupt mode based on resource counts and system
  2191. * capabilities
  2192. */
  2193. err = enic_set_intr_mode(enic);
  2194. if (err) {
  2195. dev_err(dev, "Failed to set intr mode based on resource "
  2196. "counts and system capabilities, aborting\n");
  2197. return err;
  2198. }
  2199. /* Allocate and configure vNIC resources
  2200. */
  2201. err = enic_alloc_vnic_resources(enic);
  2202. if (err) {
  2203. dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
  2204. goto err_out_free_vnic_resources;
  2205. }
  2206. enic_init_vnic_resources(enic);
  2207. err = enic_set_rss_nic_cfg(enic);
  2208. if (err) {
  2209. dev_err(dev, "Failed to config nic, aborting\n");
  2210. goto err_out_free_vnic_resources;
  2211. }
  2212. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  2213. default:
  2214. netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
  2215. break;
  2216. case VNIC_DEV_INTR_MODE_MSIX:
  2217. for (i = 0; i < enic->rq_count; i++) {
  2218. netif_napi_add(netdev, &enic->napi[i],
  2219. enic_poll_msix_rq, NAPI_POLL_WEIGHT);
  2220. }
  2221. for (i = 0; i < enic->wq_count; i++)
  2222. netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
  2223. enic_poll_msix_wq, NAPI_POLL_WEIGHT);
  2224. break;
  2225. }
  2226. return 0;
  2227. err_out_free_vnic_resources:
  2228. enic_free_affinity_hint(enic);
  2229. enic_clear_intr_mode(enic);
  2230. enic_free_vnic_resources(enic);
  2231. return err;
  2232. }
  2233. static void enic_iounmap(struct enic *enic)
  2234. {
  2235. unsigned int i;
  2236. for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
  2237. if (enic->bar[i].vaddr)
  2238. iounmap(enic->bar[i].vaddr);
  2239. }
  2240. static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2241. {
  2242. struct device *dev = &pdev->dev;
  2243. struct net_device *netdev;
  2244. struct enic *enic;
  2245. int using_dac = 0;
  2246. unsigned int i;
  2247. int err;
  2248. #ifdef CONFIG_PCI_IOV
  2249. int pos = 0;
  2250. #endif
  2251. int num_pps = 1;
  2252. /* Allocate net device structure and initialize. Private
  2253. * instance data is initialized to zero.
  2254. */
  2255. netdev = alloc_etherdev_mqs(sizeof(struct enic),
  2256. ENIC_RQ_MAX, ENIC_WQ_MAX);
  2257. if (!netdev)
  2258. return -ENOMEM;
  2259. pci_set_drvdata(pdev, netdev);
  2260. SET_NETDEV_DEV(netdev, &pdev->dev);
  2261. enic = netdev_priv(netdev);
  2262. enic->netdev = netdev;
  2263. enic->pdev = pdev;
  2264. /* Setup PCI resources
  2265. */
  2266. err = pci_enable_device_mem(pdev);
  2267. if (err) {
  2268. dev_err(dev, "Cannot enable PCI device, aborting\n");
  2269. goto err_out_free_netdev;
  2270. }
  2271. err = pci_request_regions(pdev, DRV_NAME);
  2272. if (err) {
  2273. dev_err(dev, "Cannot request PCI regions, aborting\n");
  2274. goto err_out_disable_device;
  2275. }
  2276. pci_set_master(pdev);
  2277. /* Query PCI controller on system for DMA addressing
  2278. * limitation for the device. Try 64-bit first, and
  2279. * fail to 32-bit.
  2280. */
  2281. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  2282. if (err) {
  2283. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2284. if (err) {
  2285. dev_err(dev, "No usable DMA configuration, aborting\n");
  2286. goto err_out_release_regions;
  2287. }
  2288. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2289. if (err) {
  2290. dev_err(dev, "Unable to obtain %u-bit DMA "
  2291. "for consistent allocations, aborting\n", 32);
  2292. goto err_out_release_regions;
  2293. }
  2294. } else {
  2295. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  2296. if (err) {
  2297. dev_err(dev, "Unable to obtain %u-bit DMA "
  2298. "for consistent allocations, aborting\n", 64);
  2299. goto err_out_release_regions;
  2300. }
  2301. using_dac = 1;
  2302. }
  2303. /* Map vNIC resources from BAR0-5
  2304. */
  2305. for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
  2306. if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
  2307. continue;
  2308. enic->bar[i].len = pci_resource_len(pdev, i);
  2309. enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
  2310. if (!enic->bar[i].vaddr) {
  2311. dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
  2312. err = -ENODEV;
  2313. goto err_out_iounmap;
  2314. }
  2315. enic->bar[i].bus_addr = pci_resource_start(pdev, i);
  2316. }
  2317. /* Register vNIC device
  2318. */
  2319. enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
  2320. ARRAY_SIZE(enic->bar));
  2321. if (!enic->vdev) {
  2322. dev_err(dev, "vNIC registration failed, aborting\n");
  2323. err = -ENODEV;
  2324. goto err_out_iounmap;
  2325. }
  2326. err = vnic_devcmd_init(enic->vdev);
  2327. if (err)
  2328. goto err_out_vnic_unregister;
  2329. #ifdef CONFIG_PCI_IOV
  2330. /* Get number of subvnics */
  2331. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  2332. if (pos) {
  2333. pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
  2334. &enic->num_vfs);
  2335. if (enic->num_vfs) {
  2336. err = pci_enable_sriov(pdev, enic->num_vfs);
  2337. if (err) {
  2338. dev_err(dev, "SRIOV enable failed, aborting."
  2339. " pci_enable_sriov() returned %d\n",
  2340. err);
  2341. goto err_out_vnic_unregister;
  2342. }
  2343. enic->priv_flags |= ENIC_SRIOV_ENABLED;
  2344. num_pps = enic->num_vfs;
  2345. }
  2346. }
  2347. #endif
  2348. /* Allocate structure for port profiles */
  2349. enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
  2350. if (!enic->pp) {
  2351. err = -ENOMEM;
  2352. goto err_out_disable_sriov_pp;
  2353. }
  2354. /* Issue device open to get device in known state
  2355. */
  2356. err = enic_dev_open(enic);
  2357. if (err) {
  2358. dev_err(dev, "vNIC dev open failed, aborting\n");
  2359. goto err_out_disable_sriov;
  2360. }
  2361. /* Setup devcmd lock
  2362. */
  2363. spin_lock_init(&enic->devcmd_lock);
  2364. spin_lock_init(&enic->enic_api_lock);
  2365. /*
  2366. * Set ingress vlan rewrite mode before vnic initialization
  2367. */
  2368. err = enic_dev_set_ig_vlan_rewrite_mode(enic);
  2369. if (err) {
  2370. dev_err(dev,
  2371. "Failed to set ingress vlan rewrite mode, aborting.\n");
  2372. goto err_out_dev_close;
  2373. }
  2374. /* Issue device init to initialize the vnic-to-switch link.
  2375. * We'll start with carrier off and wait for link UP
  2376. * notification later to turn on carrier. We don't need
  2377. * to wait here for the vnic-to-switch link initialization
  2378. * to complete; link UP notification is the indication that
  2379. * the process is complete.
  2380. */
  2381. netif_carrier_off(netdev);
  2382. /* Do not call dev_init for a dynamic vnic.
  2383. * For a dynamic vnic, init_prov_info will be
  2384. * called later by an upper layer.
  2385. */
  2386. if (!enic_is_dynamic(enic)) {
  2387. err = vnic_dev_init(enic->vdev, 0);
  2388. if (err) {
  2389. dev_err(dev, "vNIC dev init failed, aborting\n");
  2390. goto err_out_dev_close;
  2391. }
  2392. }
  2393. err = enic_dev_init(enic);
  2394. if (err) {
  2395. dev_err(dev, "Device initialization failed, aborting\n");
  2396. goto err_out_dev_close;
  2397. }
  2398. netif_set_real_num_tx_queues(netdev, enic->wq_count);
  2399. netif_set_real_num_rx_queues(netdev, enic->rq_count);
  2400. /* Setup notification timer, HW reset task, and wq locks
  2401. */
  2402. timer_setup(&enic->notify_timer, enic_notify_timer, 0);
  2403. enic_set_rx_coal_setting(enic);
  2404. INIT_WORK(&enic->reset, enic_reset);
  2405. INIT_WORK(&enic->tx_hang_reset, enic_tx_hang_reset);
  2406. INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
  2407. for (i = 0; i < enic->wq_count; i++)
  2408. spin_lock_init(&enic->wq_lock[i]);
  2409. /* Register net device
  2410. */
  2411. enic->port_mtu = enic->config.mtu;
  2412. (void)enic_change_mtu(netdev, enic->port_mtu);
  2413. err = enic_set_mac_addr(netdev, enic->mac_addr);
  2414. if (err) {
  2415. dev_err(dev, "Invalid MAC address, aborting\n");
  2416. goto err_out_dev_deinit;
  2417. }
  2418. enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
  2419. /* rx coalesce time already got initialized. This gets used
  2420. * if adaptive coal is turned off
  2421. */
  2422. enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
  2423. if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
  2424. netdev->netdev_ops = &enic_netdev_dynamic_ops;
  2425. else
  2426. netdev->netdev_ops = &enic_netdev_ops;
  2427. netdev->watchdog_timeo = 2 * HZ;
  2428. enic_set_ethtool_ops(netdev);
  2429. netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  2430. if (ENIC_SETTING(enic, LOOP)) {
  2431. netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  2432. enic->loop_enable = 1;
  2433. enic->loop_tag = enic->config.loop_tag;
  2434. dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
  2435. }
  2436. if (ENIC_SETTING(enic, TXCSUM))
  2437. netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  2438. if (ENIC_SETTING(enic, TSO))
  2439. netdev->hw_features |= NETIF_F_TSO |
  2440. NETIF_F_TSO6 | NETIF_F_TSO_ECN;
  2441. if (ENIC_SETTING(enic, RSS))
  2442. netdev->hw_features |= NETIF_F_RXHASH;
  2443. if (ENIC_SETTING(enic, RXCSUM))
  2444. netdev->hw_features |= NETIF_F_RXCSUM;
  2445. if (ENIC_SETTING(enic, VXLAN)) {
  2446. u64 patch_level;
  2447. u64 a1 = 0;
  2448. netdev->hw_enc_features |= NETIF_F_RXCSUM |
  2449. NETIF_F_TSO |
  2450. NETIF_F_TSO6 |
  2451. NETIF_F_TSO_ECN |
  2452. NETIF_F_GSO_UDP_TUNNEL |
  2453. NETIF_F_HW_CSUM |
  2454. NETIF_F_GSO_UDP_TUNNEL_CSUM;
  2455. netdev->hw_features |= netdev->hw_enc_features;
  2456. /* get bit mask from hw about supported offload bit level
  2457. * BIT(0) = fw supports patch_level 0
  2458. * fcoe bit = encap
  2459. * fcoe_fc_crc_ok = outer csum ok
  2460. * BIT(1) = always set by fw
  2461. * BIT(2) = fw supports patch_level 2
  2462. * BIT(0) in rss_hash = encap
  2463. * BIT(1,2) in rss_hash = outer_ip_csum_ok/
  2464. * outer_tcp_csum_ok
  2465. * used in enic_rq_indicate_buf
  2466. */
  2467. err = vnic_dev_get_supported_feature_ver(enic->vdev,
  2468. VIC_FEATURE_VXLAN,
  2469. &patch_level, &a1);
  2470. if (err)
  2471. patch_level = 0;
  2472. enic->vxlan.flags = (u8)a1;
  2473. /* mask bits that are supported by driver
  2474. */
  2475. patch_level &= BIT_ULL(0) | BIT_ULL(2);
  2476. patch_level = fls(patch_level);
  2477. patch_level = patch_level ? patch_level - 1 : 0;
  2478. enic->vxlan.patch_level = patch_level;
  2479. }
  2480. netdev->features |= netdev->hw_features;
  2481. netdev->vlan_features |= netdev->features;
  2482. #ifdef CONFIG_RFS_ACCEL
  2483. netdev->hw_features |= NETIF_F_NTUPLE;
  2484. #endif
  2485. if (using_dac)
  2486. netdev->features |= NETIF_F_HIGHDMA;
  2487. netdev->priv_flags |= IFF_UNICAST_FLT;
  2488. /* MTU range: 68 - 9000 */
  2489. netdev->min_mtu = ENIC_MIN_MTU;
  2490. netdev->max_mtu = ENIC_MAX_MTU;
  2491. err = register_netdev(netdev);
  2492. if (err) {
  2493. dev_err(dev, "Cannot register net device, aborting\n");
  2494. goto err_out_dev_deinit;
  2495. }
  2496. enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
  2497. return 0;
  2498. err_out_dev_deinit:
  2499. enic_dev_deinit(enic);
  2500. err_out_dev_close:
  2501. vnic_dev_close(enic->vdev);
  2502. err_out_disable_sriov:
  2503. kfree(enic->pp);
  2504. err_out_disable_sriov_pp:
  2505. #ifdef CONFIG_PCI_IOV
  2506. if (enic_sriov_enabled(enic)) {
  2507. pci_disable_sriov(pdev);
  2508. enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
  2509. }
  2510. #endif
  2511. err_out_vnic_unregister:
  2512. vnic_dev_unregister(enic->vdev);
  2513. err_out_iounmap:
  2514. enic_iounmap(enic);
  2515. err_out_release_regions:
  2516. pci_release_regions(pdev);
  2517. err_out_disable_device:
  2518. pci_disable_device(pdev);
  2519. err_out_free_netdev:
  2520. free_netdev(netdev);
  2521. return err;
  2522. }
  2523. static void enic_remove(struct pci_dev *pdev)
  2524. {
  2525. struct net_device *netdev = pci_get_drvdata(pdev);
  2526. if (netdev) {
  2527. struct enic *enic = netdev_priv(netdev);
  2528. cancel_work_sync(&enic->reset);
  2529. cancel_work_sync(&enic->change_mtu_work);
  2530. unregister_netdev(netdev);
  2531. enic_dev_deinit(enic);
  2532. vnic_dev_close(enic->vdev);
  2533. #ifdef CONFIG_PCI_IOV
  2534. if (enic_sriov_enabled(enic)) {
  2535. pci_disable_sriov(pdev);
  2536. enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
  2537. }
  2538. #endif
  2539. kfree(enic->pp);
  2540. vnic_dev_unregister(enic->vdev);
  2541. enic_iounmap(enic);
  2542. pci_release_regions(pdev);
  2543. pci_disable_device(pdev);
  2544. free_netdev(netdev);
  2545. }
  2546. }
  2547. static struct pci_driver enic_driver = {
  2548. .name = DRV_NAME,
  2549. .id_table = enic_id_table,
  2550. .probe = enic_probe,
  2551. .remove = enic_remove,
  2552. };
  2553. static int __init enic_init_module(void)
  2554. {
  2555. pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
  2556. return pci_register_driver(&enic_driver);
  2557. }
  2558. static void __exit enic_cleanup_module(void)
  2559. {
  2560. pci_unregister_driver(&enic_driver);
  2561. }
  2562. module_init(enic_init_module);
  2563. module_exit(enic_cleanup_module);