spectrum.c 125 KB

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  1. /*
  2. * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
  3. * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
  5. * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
  6. * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions are met:
  10. *
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions and the following disclaimer.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. Neither the names of the copyright holders nor the names of its
  17. * contributors may be used to endorse or promote products derived from
  18. * this software without specific prior written permission.
  19. *
  20. * Alternatively, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") version 2 as published by the Free
  22. * Software Foundation.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34. * POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/types.h>
  39. #include <linux/pci.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/etherdevice.h>
  42. #include <linux/ethtool.h>
  43. #include <linux/slab.h>
  44. #include <linux/device.h>
  45. #include <linux/skbuff.h>
  46. #include <linux/if_vlan.h>
  47. #include <linux/if_bridge.h>
  48. #include <linux/workqueue.h>
  49. #include <linux/jiffies.h>
  50. #include <linux/bitops.h>
  51. #include <linux/list.h>
  52. #include <linux/notifier.h>
  53. #include <linux/dcbnl.h>
  54. #include <linux/inetdevice.h>
  55. #include <net/switchdev.h>
  56. #include <net/pkt_cls.h>
  57. #include <net/tc_act/tc_mirred.h>
  58. #include <net/netevent.h>
  59. #include <net/tc_act/tc_sample.h>
  60. #include <net/addrconf.h>
  61. #include "spectrum.h"
  62. #include "pci.h"
  63. #include "core.h"
  64. #include "reg.h"
  65. #include "port.h"
  66. #include "trap.h"
  67. #include "txheader.h"
  68. #include "spectrum_cnt.h"
  69. #include "spectrum_dpipe.h"
  70. #include "spectrum_acl_flex_actions.h"
  71. #include "../mlxfw/mlxfw.h"
  72. #define MLXSW_FWREV_MAJOR 13
  73. #define MLXSW_FWREV_MINOR 1420
  74. #define MLXSW_FWREV_SUBMINOR 122
  75. static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
  76. .major = MLXSW_FWREV_MAJOR,
  77. .minor = MLXSW_FWREV_MINOR,
  78. .subminor = MLXSW_FWREV_SUBMINOR
  79. };
  80. #define MLXSW_SP_FW_FILENAME \
  81. "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
  82. "." __stringify(MLXSW_FWREV_MINOR) \
  83. "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
  84. static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
  85. static const char mlxsw_sp_driver_version[] = "1.0";
  86. /* tx_hdr_version
  87. * Tx header version.
  88. * Must be set to 1.
  89. */
  90. MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  91. /* tx_hdr_ctl
  92. * Packet control type.
  93. * 0 - Ethernet control (e.g. EMADs, LACP)
  94. * 1 - Ethernet data
  95. */
  96. MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  97. /* tx_hdr_proto
  98. * Packet protocol type. Must be set to 1 (Ethernet).
  99. */
  100. MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  101. /* tx_hdr_rx_is_router
  102. * Packet is sent from the router. Valid for data packets only.
  103. */
  104. MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  105. /* tx_hdr_fid_valid
  106. * Indicates if the 'fid' field is valid and should be used for
  107. * forwarding lookup. Valid for data packets only.
  108. */
  109. MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
  110. /* tx_hdr_swid
  111. * Switch partition ID. Must be set to 0.
  112. */
  113. MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  114. /* tx_hdr_control_tclass
  115. * Indicates if the packet should use the control TClass and not one
  116. * of the data TClasses.
  117. */
  118. MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
  119. /* tx_hdr_etclass
  120. * Egress TClass to be used on the egress device on the egress port.
  121. */
  122. MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
  123. /* tx_hdr_port_mid
  124. * Destination local port for unicast packets.
  125. * Destination multicast ID for multicast packets.
  126. *
  127. * Control packets are directed to a specific egress port, while data
  128. * packets are transmitted through the CPU port (0) into the switch partition,
  129. * where forwarding rules are applied.
  130. */
  131. MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
  132. /* tx_hdr_fid
  133. * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
  134. * set, otherwise calculated based on the packet's VID using VID to FID mapping.
  135. * Valid for data packets only.
  136. */
  137. MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
  138. /* tx_hdr_type
  139. * 0 - Data packets
  140. * 6 - Control packets
  141. */
  142. MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
  143. struct mlxsw_sp_mlxfw_dev {
  144. struct mlxfw_dev mlxfw_dev;
  145. struct mlxsw_sp *mlxsw_sp;
  146. };
  147. static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
  148. u16 component_index, u32 *p_max_size,
  149. u8 *p_align_bits, u16 *p_max_write_size)
  150. {
  151. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  152. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  153. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  154. char mcqi_pl[MLXSW_REG_MCQI_LEN];
  155. int err;
  156. mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
  157. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
  158. if (err)
  159. return err;
  160. mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
  161. p_max_write_size);
  162. *p_align_bits = max_t(u8, *p_align_bits, 2);
  163. *p_max_write_size = min_t(u16, *p_max_write_size,
  164. MLXSW_REG_MCDA_MAX_DATA_LEN);
  165. return 0;
  166. }
  167. static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
  168. {
  169. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  170. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  171. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  172. char mcc_pl[MLXSW_REG_MCC_LEN];
  173. u8 control_state;
  174. int err;
  175. mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
  176. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  177. if (err)
  178. return err;
  179. mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
  180. if (control_state != MLXFW_FSM_STATE_IDLE)
  181. return -EBUSY;
  182. mlxsw_reg_mcc_pack(mcc_pl,
  183. MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
  184. 0, *fwhandle, 0);
  185. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  186. }
  187. static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
  188. u32 fwhandle, u16 component_index,
  189. u32 component_size)
  190. {
  191. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  192. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  193. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  194. char mcc_pl[MLXSW_REG_MCC_LEN];
  195. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
  196. component_index, fwhandle, component_size);
  197. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  198. }
  199. static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
  200. u32 fwhandle, u8 *data, u16 size,
  201. u32 offset)
  202. {
  203. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  204. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  205. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  206. char mcda_pl[MLXSW_REG_MCDA_LEN];
  207. mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
  208. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
  209. }
  210. static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
  211. u32 fwhandle, u16 component_index)
  212. {
  213. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  214. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  215. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  216. char mcc_pl[MLXSW_REG_MCC_LEN];
  217. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
  218. component_index, fwhandle, 0);
  219. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  220. }
  221. static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  222. {
  223. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  224. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  225. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  226. char mcc_pl[MLXSW_REG_MCC_LEN];
  227. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
  228. fwhandle, 0);
  229. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  230. }
  231. static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
  232. enum mlxfw_fsm_state *fsm_state,
  233. enum mlxfw_fsm_state_err *fsm_state_err)
  234. {
  235. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  236. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  237. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  238. char mcc_pl[MLXSW_REG_MCC_LEN];
  239. u8 control_state;
  240. u8 error_code;
  241. int err;
  242. mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
  243. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  244. if (err)
  245. return err;
  246. mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
  247. *fsm_state = control_state;
  248. *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
  249. MLXFW_FSM_STATE_ERR_MAX);
  250. return 0;
  251. }
  252. static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  253. {
  254. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  255. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  256. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  257. char mcc_pl[MLXSW_REG_MCC_LEN];
  258. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
  259. fwhandle, 0);
  260. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  261. }
  262. static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  263. {
  264. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  265. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  266. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  267. char mcc_pl[MLXSW_REG_MCC_LEN];
  268. mlxsw_reg_mcc_pack(mcc_pl,
  269. MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
  270. fwhandle, 0);
  271. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  272. }
  273. static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
  274. .component_query = mlxsw_sp_component_query,
  275. .fsm_lock = mlxsw_sp_fsm_lock,
  276. .fsm_component_update = mlxsw_sp_fsm_component_update,
  277. .fsm_block_download = mlxsw_sp_fsm_block_download,
  278. .fsm_component_verify = mlxsw_sp_fsm_component_verify,
  279. .fsm_activate = mlxsw_sp_fsm_activate,
  280. .fsm_query_state = mlxsw_sp_fsm_query_state,
  281. .fsm_cancel = mlxsw_sp_fsm_cancel,
  282. .fsm_release = mlxsw_sp_fsm_release
  283. };
  284. static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
  285. const struct firmware *firmware)
  286. {
  287. struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
  288. .mlxfw_dev = {
  289. .ops = &mlxsw_sp_mlxfw_dev_ops,
  290. .psid = mlxsw_sp->bus_info->psid,
  291. .psid_size = strlen(mlxsw_sp->bus_info->psid),
  292. },
  293. .mlxsw_sp = mlxsw_sp
  294. };
  295. return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
  296. }
  297. static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
  298. const struct mlxsw_fw_rev *b)
  299. {
  300. if (a->major != b->major)
  301. return a->major > b->major;
  302. if (a->minor != b->minor)
  303. return a->minor > b->minor;
  304. return a->subminor >= b->subminor;
  305. }
  306. static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
  307. {
  308. const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
  309. const struct firmware *firmware;
  310. int err;
  311. if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
  312. return 0;
  313. dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
  314. rev->major, rev->minor, rev->subminor);
  315. dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
  316. MLXSW_SP_FW_FILENAME);
  317. err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
  318. mlxsw_sp->bus_info->dev);
  319. if (err) {
  320. dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
  321. MLXSW_SP_FW_FILENAME);
  322. return err;
  323. }
  324. err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
  325. release_firmware(firmware);
  326. return err;
  327. }
  328. int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
  329. unsigned int counter_index, u64 *packets,
  330. u64 *bytes)
  331. {
  332. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  333. int err;
  334. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
  335. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  336. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  337. if (err)
  338. return err;
  339. if (packets)
  340. *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
  341. if (bytes)
  342. *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
  343. return 0;
  344. }
  345. static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
  346. unsigned int counter_index)
  347. {
  348. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  349. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
  350. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  351. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  352. }
  353. int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
  354. unsigned int *p_counter_index)
  355. {
  356. int err;
  357. err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  358. p_counter_index);
  359. if (err)
  360. return err;
  361. err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
  362. if (err)
  363. goto err_counter_clear;
  364. return 0;
  365. err_counter_clear:
  366. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  367. *p_counter_index);
  368. return err;
  369. }
  370. void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
  371. unsigned int counter_index)
  372. {
  373. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  374. counter_index);
  375. }
  376. static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
  377. const struct mlxsw_tx_info *tx_info)
  378. {
  379. char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
  380. memset(txhdr, 0, MLXSW_TXHDR_LEN);
  381. mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
  382. mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
  383. mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
  384. mlxsw_tx_hdr_swid_set(txhdr, 0);
  385. mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
  386. mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
  387. mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
  388. }
  389. int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  390. u8 state)
  391. {
  392. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  393. enum mlxsw_reg_spms_state spms_state;
  394. char *spms_pl;
  395. int err;
  396. switch (state) {
  397. case BR_STATE_FORWARDING:
  398. spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
  399. break;
  400. case BR_STATE_LEARNING:
  401. spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
  402. break;
  403. case BR_STATE_LISTENING: /* fall-through */
  404. case BR_STATE_DISABLED: /* fall-through */
  405. case BR_STATE_BLOCKING:
  406. spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
  407. break;
  408. default:
  409. BUG();
  410. }
  411. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  412. if (!spms_pl)
  413. return -ENOMEM;
  414. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  415. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  416. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  417. kfree(spms_pl);
  418. return err;
  419. }
  420. static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
  421. {
  422. char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
  423. int err;
  424. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
  425. if (err)
  426. return err;
  427. mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
  428. return 0;
  429. }
  430. static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
  431. {
  432. int i;
  433. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
  434. return -EIO;
  435. mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
  436. MAX_SPAN);
  437. mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
  438. sizeof(struct mlxsw_sp_span_entry),
  439. GFP_KERNEL);
  440. if (!mlxsw_sp->span.entries)
  441. return -ENOMEM;
  442. for (i = 0; i < mlxsw_sp->span.entries_count; i++)
  443. INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
  444. return 0;
  445. }
  446. static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
  447. {
  448. int i;
  449. for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
  450. struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
  451. WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
  452. }
  453. kfree(mlxsw_sp->span.entries);
  454. }
  455. static struct mlxsw_sp_span_entry *
  456. mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
  457. {
  458. struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
  459. struct mlxsw_sp_span_entry *span_entry;
  460. char mpat_pl[MLXSW_REG_MPAT_LEN];
  461. u8 local_port = port->local_port;
  462. int index;
  463. int i;
  464. int err;
  465. /* find a free entry to use */
  466. index = -1;
  467. for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
  468. if (!mlxsw_sp->span.entries[i].used) {
  469. index = i;
  470. span_entry = &mlxsw_sp->span.entries[i];
  471. break;
  472. }
  473. }
  474. if (index < 0)
  475. return NULL;
  476. /* create a new port analayzer entry for local_port */
  477. mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
  478. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
  479. if (err)
  480. return NULL;
  481. span_entry->used = true;
  482. span_entry->id = index;
  483. span_entry->ref_count = 1;
  484. span_entry->local_port = local_port;
  485. return span_entry;
  486. }
  487. static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
  488. struct mlxsw_sp_span_entry *span_entry)
  489. {
  490. u8 local_port = span_entry->local_port;
  491. char mpat_pl[MLXSW_REG_MPAT_LEN];
  492. int pa_id = span_entry->id;
  493. mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
  494. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
  495. span_entry->used = false;
  496. }
  497. static struct mlxsw_sp_span_entry *
  498. mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
  499. {
  500. int i;
  501. for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
  502. struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
  503. if (curr->used && curr->local_port == local_port)
  504. return curr;
  505. }
  506. return NULL;
  507. }
  508. static struct mlxsw_sp_span_entry
  509. *mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
  510. {
  511. struct mlxsw_sp_span_entry *span_entry;
  512. span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
  513. port->local_port);
  514. if (span_entry) {
  515. /* Already exists, just take a reference */
  516. span_entry->ref_count++;
  517. return span_entry;
  518. }
  519. return mlxsw_sp_span_entry_create(port);
  520. }
  521. static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
  522. struct mlxsw_sp_span_entry *span_entry)
  523. {
  524. WARN_ON(!span_entry->ref_count);
  525. if (--span_entry->ref_count == 0)
  526. mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
  527. return 0;
  528. }
  529. static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
  530. {
  531. struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
  532. struct mlxsw_sp_span_inspected_port *p;
  533. int i;
  534. for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
  535. struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
  536. list_for_each_entry(p, &curr->bound_ports_list, list)
  537. if (p->local_port == port->local_port &&
  538. p->type == MLXSW_SP_SPAN_EGRESS)
  539. return true;
  540. }
  541. return false;
  542. }
  543. static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
  544. int mtu)
  545. {
  546. return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
  547. }
  548. static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
  549. {
  550. struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
  551. char sbib_pl[MLXSW_REG_SBIB_LEN];
  552. int err;
  553. /* If port is egress mirrored, the shared buffer size should be
  554. * updated according to the mtu value
  555. */
  556. if (mlxsw_sp_span_is_egress_mirror(port)) {
  557. u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
  558. mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
  559. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
  560. if (err) {
  561. netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
  562. return err;
  563. }
  564. }
  565. return 0;
  566. }
  567. static struct mlxsw_sp_span_inspected_port *
  568. mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
  569. struct mlxsw_sp_span_entry *span_entry)
  570. {
  571. struct mlxsw_sp_span_inspected_port *p;
  572. list_for_each_entry(p, &span_entry->bound_ports_list, list)
  573. if (port->local_port == p->local_port)
  574. return p;
  575. return NULL;
  576. }
  577. static int
  578. mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
  579. struct mlxsw_sp_span_entry *span_entry,
  580. enum mlxsw_sp_span_type type)
  581. {
  582. struct mlxsw_sp_span_inspected_port *inspected_port;
  583. struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
  584. char mpar_pl[MLXSW_REG_MPAR_LEN];
  585. char sbib_pl[MLXSW_REG_SBIB_LEN];
  586. int pa_id = span_entry->id;
  587. int err;
  588. /* if it is an egress SPAN, bind a shared buffer to it */
  589. if (type == MLXSW_SP_SPAN_EGRESS) {
  590. u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
  591. port->dev->mtu);
  592. mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
  593. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
  594. if (err) {
  595. netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
  596. return err;
  597. }
  598. }
  599. /* bind the port to the SPAN entry */
  600. mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
  601. (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
  602. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
  603. if (err)
  604. goto err_mpar_reg_write;
  605. inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
  606. if (!inspected_port) {
  607. err = -ENOMEM;
  608. goto err_inspected_port_alloc;
  609. }
  610. inspected_port->local_port = port->local_port;
  611. inspected_port->type = type;
  612. list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
  613. return 0;
  614. err_mpar_reg_write:
  615. err_inspected_port_alloc:
  616. if (type == MLXSW_SP_SPAN_EGRESS) {
  617. mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
  618. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
  619. }
  620. return err;
  621. }
  622. static void
  623. mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
  624. struct mlxsw_sp_span_entry *span_entry,
  625. enum mlxsw_sp_span_type type)
  626. {
  627. struct mlxsw_sp_span_inspected_port *inspected_port;
  628. struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
  629. char mpar_pl[MLXSW_REG_MPAR_LEN];
  630. char sbib_pl[MLXSW_REG_SBIB_LEN];
  631. int pa_id = span_entry->id;
  632. inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
  633. if (!inspected_port)
  634. return;
  635. /* remove the inspected port */
  636. mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
  637. (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
  638. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
  639. /* remove the SBIB buffer if it was egress SPAN */
  640. if (type == MLXSW_SP_SPAN_EGRESS) {
  641. mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
  642. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
  643. }
  644. mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
  645. list_del(&inspected_port->list);
  646. kfree(inspected_port);
  647. }
  648. static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
  649. struct mlxsw_sp_port *to,
  650. enum mlxsw_sp_span_type type)
  651. {
  652. struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
  653. struct mlxsw_sp_span_entry *span_entry;
  654. int err;
  655. span_entry = mlxsw_sp_span_entry_get(to);
  656. if (!span_entry)
  657. return -ENOENT;
  658. netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
  659. span_entry->id);
  660. err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
  661. if (err)
  662. goto err_port_bind;
  663. return 0;
  664. err_port_bind:
  665. mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
  666. return err;
  667. }
  668. static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
  669. u8 destination_port,
  670. enum mlxsw_sp_span_type type)
  671. {
  672. struct mlxsw_sp_span_entry *span_entry;
  673. span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
  674. destination_port);
  675. if (!span_entry) {
  676. netdev_err(from->dev, "no span entry found\n");
  677. return;
  678. }
  679. netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
  680. span_entry->id);
  681. mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
  682. }
  683. static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
  684. bool enable, u32 rate)
  685. {
  686. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  687. char mpsc_pl[MLXSW_REG_MPSC_LEN];
  688. mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
  689. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
  690. }
  691. static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
  692. bool is_up)
  693. {
  694. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  695. char paos_pl[MLXSW_REG_PAOS_LEN];
  696. mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
  697. is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
  698. MLXSW_PORT_ADMIN_STATUS_DOWN);
  699. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
  700. }
  701. static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
  702. unsigned char *addr)
  703. {
  704. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  705. char ppad_pl[MLXSW_REG_PPAD_LEN];
  706. mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
  707. mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
  708. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
  709. }
  710. static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
  711. {
  712. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  713. unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
  714. ether_addr_copy(addr, mlxsw_sp->base_mac);
  715. addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
  716. return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
  717. }
  718. static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
  719. {
  720. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  721. char pmtu_pl[MLXSW_REG_PMTU_LEN];
  722. int max_mtu;
  723. int err;
  724. mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
  725. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
  726. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
  727. if (err)
  728. return err;
  729. max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
  730. if (mtu > max_mtu)
  731. return -EINVAL;
  732. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
  733. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
  734. }
  735. static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
  736. {
  737. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  738. char pspa_pl[MLXSW_REG_PSPA_LEN];
  739. mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
  740. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
  741. }
  742. int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
  743. {
  744. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  745. char svpe_pl[MLXSW_REG_SVPE_LEN];
  746. mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
  747. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
  748. }
  749. int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  750. bool learn_enable)
  751. {
  752. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  753. char *spvmlr_pl;
  754. int err;
  755. spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
  756. if (!spvmlr_pl)
  757. return -ENOMEM;
  758. mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
  759. learn_enable);
  760. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
  761. kfree(spvmlr_pl);
  762. return err;
  763. }
  764. static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
  765. u16 vid)
  766. {
  767. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  768. char spvid_pl[MLXSW_REG_SPVID_LEN];
  769. mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
  770. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
  771. }
  772. static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
  773. bool allow)
  774. {
  775. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  776. char spaft_pl[MLXSW_REG_SPAFT_LEN];
  777. mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
  778. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
  779. }
  780. int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  781. {
  782. int err;
  783. if (!vid) {
  784. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
  785. if (err)
  786. return err;
  787. } else {
  788. err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
  789. if (err)
  790. return err;
  791. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
  792. if (err)
  793. goto err_port_allow_untagged_set;
  794. }
  795. mlxsw_sp_port->pvid = vid;
  796. return 0;
  797. err_port_allow_untagged_set:
  798. __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
  799. return err;
  800. }
  801. static int
  802. mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
  803. {
  804. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  805. char sspr_pl[MLXSW_REG_SSPR_LEN];
  806. mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
  807. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
  808. }
  809. static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
  810. u8 local_port, u8 *p_module,
  811. u8 *p_width, u8 *p_lane)
  812. {
  813. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  814. int err;
  815. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  816. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  817. if (err)
  818. return err;
  819. *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
  820. *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
  821. *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
  822. return 0;
  823. }
  824. static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
  825. u8 module, u8 width, u8 lane)
  826. {
  827. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  828. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  829. int i;
  830. mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
  831. mlxsw_reg_pmlp_width_set(pmlp_pl, width);
  832. for (i = 0; i < width; i++) {
  833. mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
  834. mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
  835. }
  836. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  837. }
  838. static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
  839. {
  840. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  841. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  842. mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
  843. mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
  844. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  845. }
  846. static int mlxsw_sp_port_open(struct net_device *dev)
  847. {
  848. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  849. int err;
  850. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  851. if (err)
  852. return err;
  853. netif_start_queue(dev);
  854. return 0;
  855. }
  856. static int mlxsw_sp_port_stop(struct net_device *dev)
  857. {
  858. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  859. netif_stop_queue(dev);
  860. return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  861. }
  862. static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
  863. struct net_device *dev)
  864. {
  865. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  866. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  867. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  868. const struct mlxsw_tx_info tx_info = {
  869. .local_port = mlxsw_sp_port->local_port,
  870. .is_emad = false,
  871. };
  872. u64 len;
  873. int err;
  874. if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
  875. return NETDEV_TX_BUSY;
  876. if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
  877. struct sk_buff *skb_orig = skb;
  878. skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
  879. if (!skb) {
  880. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  881. dev_kfree_skb_any(skb_orig);
  882. return NETDEV_TX_OK;
  883. }
  884. dev_consume_skb_any(skb_orig);
  885. }
  886. if (eth_skb_pad(skb)) {
  887. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  888. return NETDEV_TX_OK;
  889. }
  890. mlxsw_sp_txhdr_construct(skb, &tx_info);
  891. /* TX header is consumed by HW on the way so we shouldn't count its
  892. * bytes as being sent.
  893. */
  894. len = skb->len - MLXSW_TXHDR_LEN;
  895. /* Due to a race we might fail here because of a full queue. In that
  896. * unlikely case we simply drop the packet.
  897. */
  898. err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
  899. if (!err) {
  900. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  901. u64_stats_update_begin(&pcpu_stats->syncp);
  902. pcpu_stats->tx_packets++;
  903. pcpu_stats->tx_bytes += len;
  904. u64_stats_update_end(&pcpu_stats->syncp);
  905. } else {
  906. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  907. dev_kfree_skb_any(skb);
  908. }
  909. return NETDEV_TX_OK;
  910. }
  911. static void mlxsw_sp_set_rx_mode(struct net_device *dev)
  912. {
  913. }
  914. static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
  915. {
  916. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  917. struct sockaddr *addr = p;
  918. int err;
  919. if (!is_valid_ether_addr(addr->sa_data))
  920. return -EADDRNOTAVAIL;
  921. err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
  922. if (err)
  923. return err;
  924. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  925. return 0;
  926. }
  927. static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
  928. int mtu)
  929. {
  930. return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
  931. }
  932. #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
  933. static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
  934. u16 delay)
  935. {
  936. delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
  937. BITS_PER_BYTE));
  938. return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
  939. mtu);
  940. }
  941. /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
  942. * Assumes 100m cable and maximum MTU.
  943. */
  944. #define MLXSW_SP_PAUSE_DELAY 58752
  945. static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
  946. u16 delay, bool pfc, bool pause)
  947. {
  948. if (pfc)
  949. return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
  950. else if (pause)
  951. return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
  952. else
  953. return 0;
  954. }
  955. static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
  956. bool lossy)
  957. {
  958. if (lossy)
  959. mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
  960. else
  961. mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
  962. thres);
  963. }
  964. int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
  965. u8 *prio_tc, bool pause_en,
  966. struct ieee_pfc *my_pfc)
  967. {
  968. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  969. u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
  970. u16 delay = !!my_pfc ? my_pfc->delay : 0;
  971. char pbmc_pl[MLXSW_REG_PBMC_LEN];
  972. int i, j, err;
  973. mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
  974. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
  975. if (err)
  976. return err;
  977. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  978. bool configure = false;
  979. bool pfc = false;
  980. bool lossy;
  981. u16 thres;
  982. for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
  983. if (prio_tc[j] == i) {
  984. pfc = pfc_en & BIT(j);
  985. configure = true;
  986. break;
  987. }
  988. }
  989. if (!configure)
  990. continue;
  991. lossy = !(pfc || pause_en);
  992. thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
  993. delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
  994. pause_en);
  995. mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
  996. }
  997. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
  998. }
  999. static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1000. int mtu, bool pause_en)
  1001. {
  1002. u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
  1003. bool dcb_en = !!mlxsw_sp_port->dcb.ets;
  1004. struct ieee_pfc *my_pfc;
  1005. u8 *prio_tc;
  1006. prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
  1007. my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
  1008. return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
  1009. pause_en, my_pfc);
  1010. }
  1011. static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
  1012. {
  1013. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1014. bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
  1015. int err;
  1016. err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
  1017. if (err)
  1018. return err;
  1019. err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
  1020. if (err)
  1021. goto err_span_port_mtu_update;
  1022. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
  1023. if (err)
  1024. goto err_port_mtu_set;
  1025. dev->mtu = mtu;
  1026. return 0;
  1027. err_port_mtu_set:
  1028. mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
  1029. err_span_port_mtu_update:
  1030. mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  1031. return err;
  1032. }
  1033. static int
  1034. mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
  1035. struct rtnl_link_stats64 *stats)
  1036. {
  1037. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1038. struct mlxsw_sp_port_pcpu_stats *p;
  1039. u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
  1040. u32 tx_dropped = 0;
  1041. unsigned int start;
  1042. int i;
  1043. for_each_possible_cpu(i) {
  1044. p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
  1045. do {
  1046. start = u64_stats_fetch_begin_irq(&p->syncp);
  1047. rx_packets = p->rx_packets;
  1048. rx_bytes = p->rx_bytes;
  1049. tx_packets = p->tx_packets;
  1050. tx_bytes = p->tx_bytes;
  1051. } while (u64_stats_fetch_retry_irq(&p->syncp, start));
  1052. stats->rx_packets += rx_packets;
  1053. stats->rx_bytes += rx_bytes;
  1054. stats->tx_packets += tx_packets;
  1055. stats->tx_bytes += tx_bytes;
  1056. /* tx_dropped is u32, updated without syncp protection. */
  1057. tx_dropped += p->tx_dropped;
  1058. }
  1059. stats->tx_dropped = tx_dropped;
  1060. return 0;
  1061. }
  1062. static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
  1063. {
  1064. switch (attr_id) {
  1065. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  1066. return true;
  1067. }
  1068. return false;
  1069. }
  1070. static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
  1071. void *sp)
  1072. {
  1073. switch (attr_id) {
  1074. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  1075. return mlxsw_sp_port_get_sw_stats64(dev, sp);
  1076. }
  1077. return -EINVAL;
  1078. }
  1079. static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
  1080. int prio, char *ppcnt_pl)
  1081. {
  1082. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1083. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1084. mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
  1085. return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
  1086. }
  1087. static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
  1088. struct rtnl_link_stats64 *stats)
  1089. {
  1090. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  1091. int err;
  1092. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
  1093. 0, ppcnt_pl);
  1094. if (err)
  1095. goto out;
  1096. stats->tx_packets =
  1097. mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
  1098. stats->rx_packets =
  1099. mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
  1100. stats->tx_bytes =
  1101. mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
  1102. stats->rx_bytes =
  1103. mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
  1104. stats->multicast =
  1105. mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
  1106. stats->rx_crc_errors =
  1107. mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
  1108. stats->rx_frame_errors =
  1109. mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
  1110. stats->rx_length_errors = (
  1111. mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
  1112. mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
  1113. mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
  1114. stats->rx_errors = (stats->rx_crc_errors +
  1115. stats->rx_frame_errors + stats->rx_length_errors);
  1116. out:
  1117. return err;
  1118. }
  1119. static void update_stats_cache(struct work_struct *work)
  1120. {
  1121. struct mlxsw_sp_port *mlxsw_sp_port =
  1122. container_of(work, struct mlxsw_sp_port,
  1123. hw_stats.update_dw.work);
  1124. if (!netif_carrier_ok(mlxsw_sp_port->dev))
  1125. goto out;
  1126. mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
  1127. mlxsw_sp_port->hw_stats.cache);
  1128. out:
  1129. mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
  1130. MLXSW_HW_STATS_UPDATE_TIME);
  1131. }
  1132. /* Return the stats from a cache that is updated periodically,
  1133. * as this function might get called in an atomic context.
  1134. */
  1135. static void
  1136. mlxsw_sp_port_get_stats64(struct net_device *dev,
  1137. struct rtnl_link_stats64 *stats)
  1138. {
  1139. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1140. memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
  1141. }
  1142. static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1143. u16 vid_begin, u16 vid_end,
  1144. bool is_member, bool untagged)
  1145. {
  1146. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1147. char *spvm_pl;
  1148. int err;
  1149. spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
  1150. if (!spvm_pl)
  1151. return -ENOMEM;
  1152. mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
  1153. vid_end, is_member, untagged);
  1154. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
  1155. kfree(spvm_pl);
  1156. return err;
  1157. }
  1158. int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
  1159. u16 vid_end, bool is_member, bool untagged)
  1160. {
  1161. u16 vid, vid_e;
  1162. int err;
  1163. for (vid = vid_begin; vid <= vid_end;
  1164. vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
  1165. vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
  1166. vid_end);
  1167. err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
  1168. is_member, untagged);
  1169. if (err)
  1170. return err;
  1171. }
  1172. return 0;
  1173. }
  1174. static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
  1175. {
  1176. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
  1177. list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
  1178. &mlxsw_sp_port->vlans_list, list)
  1179. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  1180. }
  1181. static struct mlxsw_sp_port_vlan *
  1182. mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  1183. {
  1184. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  1185. bool untagged = vid == 1;
  1186. int err;
  1187. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
  1188. if (err)
  1189. return ERR_PTR(err);
  1190. mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
  1191. if (!mlxsw_sp_port_vlan) {
  1192. err = -ENOMEM;
  1193. goto err_port_vlan_alloc;
  1194. }
  1195. mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
  1196. mlxsw_sp_port_vlan->vid = vid;
  1197. list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
  1198. return mlxsw_sp_port_vlan;
  1199. err_port_vlan_alloc:
  1200. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  1201. return ERR_PTR(err);
  1202. }
  1203. static void
  1204. mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  1205. {
  1206. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
  1207. u16 vid = mlxsw_sp_port_vlan->vid;
  1208. list_del(&mlxsw_sp_port_vlan->list);
  1209. kfree(mlxsw_sp_port_vlan);
  1210. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  1211. }
  1212. struct mlxsw_sp_port_vlan *
  1213. mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  1214. {
  1215. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  1216. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  1217. if (mlxsw_sp_port_vlan)
  1218. return mlxsw_sp_port_vlan;
  1219. return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
  1220. }
  1221. void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  1222. {
  1223. struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
  1224. if (mlxsw_sp_port_vlan->bridge_port)
  1225. mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
  1226. else if (fid)
  1227. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
  1228. mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
  1229. }
  1230. static int mlxsw_sp_port_add_vid(struct net_device *dev,
  1231. __be16 __always_unused proto, u16 vid)
  1232. {
  1233. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1234. /* VLAN 0 is added to HW filter when device goes up, but it is
  1235. * reserved in our case, so simply return.
  1236. */
  1237. if (!vid)
  1238. return 0;
  1239. return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
  1240. }
  1241. static int mlxsw_sp_port_kill_vid(struct net_device *dev,
  1242. __be16 __always_unused proto, u16 vid)
  1243. {
  1244. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1245. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  1246. /* VLAN 0 is removed from HW filter when device goes down, but
  1247. * it is reserved in our case, so simply return.
  1248. */
  1249. if (!vid)
  1250. return 0;
  1251. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  1252. if (!mlxsw_sp_port_vlan)
  1253. return 0;
  1254. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  1255. return 0;
  1256. }
  1257. static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
  1258. size_t len)
  1259. {
  1260. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1261. u8 module = mlxsw_sp_port->mapping.module;
  1262. u8 width = mlxsw_sp_port->mapping.width;
  1263. u8 lane = mlxsw_sp_port->mapping.lane;
  1264. int err;
  1265. if (!mlxsw_sp_port->split)
  1266. err = snprintf(name, len, "p%d", module + 1);
  1267. else
  1268. err = snprintf(name, len, "p%ds%d", module + 1,
  1269. lane / width);
  1270. if (err >= len)
  1271. return -EINVAL;
  1272. return 0;
  1273. }
  1274. static struct mlxsw_sp_port_mall_tc_entry *
  1275. mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
  1276. unsigned long cookie) {
  1277. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1278. list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
  1279. if (mall_tc_entry->cookie == cookie)
  1280. return mall_tc_entry;
  1281. return NULL;
  1282. }
  1283. static int
  1284. mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
  1285. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
  1286. const struct tc_action *a,
  1287. bool ingress)
  1288. {
  1289. struct net *net = dev_net(mlxsw_sp_port->dev);
  1290. enum mlxsw_sp_span_type span_type;
  1291. struct mlxsw_sp_port *to_port;
  1292. struct net_device *to_dev;
  1293. int ifindex;
  1294. ifindex = tcf_mirred_ifindex(a);
  1295. to_dev = __dev_get_by_index(net, ifindex);
  1296. if (!to_dev) {
  1297. netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
  1298. return -EINVAL;
  1299. }
  1300. if (!mlxsw_sp_port_dev_check(to_dev)) {
  1301. netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
  1302. return -EOPNOTSUPP;
  1303. }
  1304. to_port = netdev_priv(to_dev);
  1305. mirror->to_local_port = to_port->local_port;
  1306. mirror->ingress = ingress;
  1307. span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
  1308. return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
  1309. }
  1310. static void
  1311. mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
  1312. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
  1313. {
  1314. enum mlxsw_sp_span_type span_type;
  1315. span_type = mirror->ingress ?
  1316. MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
  1317. mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
  1318. span_type);
  1319. }
  1320. static int
  1321. mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
  1322. struct tc_cls_matchall_offload *cls,
  1323. const struct tc_action *a,
  1324. bool ingress)
  1325. {
  1326. int err;
  1327. if (!mlxsw_sp_port->sample)
  1328. return -EOPNOTSUPP;
  1329. if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
  1330. netdev_err(mlxsw_sp_port->dev, "sample already active\n");
  1331. return -EEXIST;
  1332. }
  1333. if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
  1334. netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
  1335. return -EOPNOTSUPP;
  1336. }
  1337. rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
  1338. tcf_sample_psample_group(a));
  1339. mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
  1340. mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
  1341. mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
  1342. err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
  1343. if (err)
  1344. goto err_port_sample_set;
  1345. return 0;
  1346. err_port_sample_set:
  1347. RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
  1348. return err;
  1349. }
  1350. static void
  1351. mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
  1352. {
  1353. if (!mlxsw_sp_port->sample)
  1354. return;
  1355. mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
  1356. RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
  1357. }
  1358. static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1359. struct tc_cls_matchall_offload *f,
  1360. bool ingress)
  1361. {
  1362. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1363. __be16 protocol = f->common.protocol;
  1364. const struct tc_action *a;
  1365. LIST_HEAD(actions);
  1366. int err;
  1367. if (!tcf_exts_has_one_action(f->exts)) {
  1368. netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
  1369. return -EOPNOTSUPP;
  1370. }
  1371. mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
  1372. if (!mall_tc_entry)
  1373. return -ENOMEM;
  1374. mall_tc_entry->cookie = f->cookie;
  1375. tcf_exts_to_list(f->exts, &actions);
  1376. a = list_first_entry(&actions, struct tc_action, list);
  1377. if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
  1378. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
  1379. mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
  1380. mirror = &mall_tc_entry->mirror;
  1381. err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
  1382. mirror, a, ingress);
  1383. } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
  1384. mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
  1385. err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
  1386. a, ingress);
  1387. } else {
  1388. err = -EOPNOTSUPP;
  1389. }
  1390. if (err)
  1391. goto err_add_action;
  1392. list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
  1393. return 0;
  1394. err_add_action:
  1395. kfree(mall_tc_entry);
  1396. return err;
  1397. }
  1398. static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1399. struct tc_cls_matchall_offload *f)
  1400. {
  1401. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1402. mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
  1403. f->cookie);
  1404. if (!mall_tc_entry) {
  1405. netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
  1406. return;
  1407. }
  1408. list_del(&mall_tc_entry->list);
  1409. switch (mall_tc_entry->type) {
  1410. case MLXSW_SP_PORT_MALL_MIRROR:
  1411. mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
  1412. &mall_tc_entry->mirror);
  1413. break;
  1414. case MLXSW_SP_PORT_MALL_SAMPLE:
  1415. mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
  1416. break;
  1417. default:
  1418. WARN_ON(1);
  1419. }
  1420. kfree(mall_tc_entry);
  1421. }
  1422. static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1423. struct tc_cls_matchall_offload *f)
  1424. {
  1425. bool ingress;
  1426. if (is_classid_clsact_ingress(f->common.classid))
  1427. ingress = true;
  1428. else if (is_classid_clsact_egress(f->common.classid))
  1429. ingress = false;
  1430. else
  1431. return -EOPNOTSUPP;
  1432. if (f->common.chain_index)
  1433. return -EOPNOTSUPP;
  1434. switch (f->command) {
  1435. case TC_CLSMATCHALL_REPLACE:
  1436. return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
  1437. ingress);
  1438. case TC_CLSMATCHALL_DESTROY:
  1439. mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
  1440. return 0;
  1441. default:
  1442. return -EOPNOTSUPP;
  1443. }
  1444. }
  1445. static int
  1446. mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
  1447. struct tc_cls_flower_offload *f)
  1448. {
  1449. bool ingress;
  1450. if (is_classid_clsact_ingress(f->common.classid))
  1451. ingress = true;
  1452. else if (is_classid_clsact_egress(f->common.classid))
  1453. ingress = false;
  1454. else
  1455. return -EOPNOTSUPP;
  1456. switch (f->command) {
  1457. case TC_CLSFLOWER_REPLACE:
  1458. return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
  1459. case TC_CLSFLOWER_DESTROY:
  1460. mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
  1461. return 0;
  1462. case TC_CLSFLOWER_STATS:
  1463. return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
  1464. default:
  1465. return -EOPNOTSUPP;
  1466. }
  1467. }
  1468. static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
  1469. void *type_data)
  1470. {
  1471. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1472. switch (type) {
  1473. case TC_SETUP_CLSMATCHALL:
  1474. return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data);
  1475. case TC_SETUP_CLSFLOWER:
  1476. return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data);
  1477. default:
  1478. return -EOPNOTSUPP;
  1479. }
  1480. }
  1481. static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
  1482. .ndo_open = mlxsw_sp_port_open,
  1483. .ndo_stop = mlxsw_sp_port_stop,
  1484. .ndo_start_xmit = mlxsw_sp_port_xmit,
  1485. .ndo_setup_tc = mlxsw_sp_setup_tc,
  1486. .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
  1487. .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
  1488. .ndo_change_mtu = mlxsw_sp_port_change_mtu,
  1489. .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
  1490. .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
  1491. .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
  1492. .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
  1493. .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
  1494. .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
  1495. };
  1496. static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
  1497. struct ethtool_drvinfo *drvinfo)
  1498. {
  1499. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1500. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1501. strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
  1502. strlcpy(drvinfo->version, mlxsw_sp_driver_version,
  1503. sizeof(drvinfo->version));
  1504. snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  1505. "%d.%d.%d",
  1506. mlxsw_sp->bus_info->fw_rev.major,
  1507. mlxsw_sp->bus_info->fw_rev.minor,
  1508. mlxsw_sp->bus_info->fw_rev.subminor);
  1509. strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
  1510. sizeof(drvinfo->bus_info));
  1511. }
  1512. static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
  1513. struct ethtool_pauseparam *pause)
  1514. {
  1515. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1516. pause->rx_pause = mlxsw_sp_port->link.rx_pause;
  1517. pause->tx_pause = mlxsw_sp_port->link.tx_pause;
  1518. }
  1519. static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1520. struct ethtool_pauseparam *pause)
  1521. {
  1522. char pfcc_pl[MLXSW_REG_PFCC_LEN];
  1523. mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
  1524. mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
  1525. mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
  1526. return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
  1527. pfcc_pl);
  1528. }
  1529. static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
  1530. struct ethtool_pauseparam *pause)
  1531. {
  1532. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1533. bool pause_en = pause->tx_pause || pause->rx_pause;
  1534. int err;
  1535. if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
  1536. netdev_err(dev, "PFC already enabled on port\n");
  1537. return -EINVAL;
  1538. }
  1539. if (pause->autoneg) {
  1540. netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
  1541. return -EINVAL;
  1542. }
  1543. err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  1544. if (err) {
  1545. netdev_err(dev, "Failed to configure port's headroom\n");
  1546. return err;
  1547. }
  1548. err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
  1549. if (err) {
  1550. netdev_err(dev, "Failed to set PAUSE parameters\n");
  1551. goto err_port_pause_configure;
  1552. }
  1553. mlxsw_sp_port->link.rx_pause = pause->rx_pause;
  1554. mlxsw_sp_port->link.tx_pause = pause->tx_pause;
  1555. return 0;
  1556. err_port_pause_configure:
  1557. pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
  1558. mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  1559. return err;
  1560. }
  1561. struct mlxsw_sp_port_hw_stats {
  1562. char str[ETH_GSTRING_LEN];
  1563. u64 (*getter)(const char *payload);
  1564. bool cells_bytes;
  1565. };
  1566. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
  1567. {
  1568. .str = "a_frames_transmitted_ok",
  1569. .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
  1570. },
  1571. {
  1572. .str = "a_frames_received_ok",
  1573. .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
  1574. },
  1575. {
  1576. .str = "a_frame_check_sequence_errors",
  1577. .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
  1578. },
  1579. {
  1580. .str = "a_alignment_errors",
  1581. .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
  1582. },
  1583. {
  1584. .str = "a_octets_transmitted_ok",
  1585. .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
  1586. },
  1587. {
  1588. .str = "a_octets_received_ok",
  1589. .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
  1590. },
  1591. {
  1592. .str = "a_multicast_frames_xmitted_ok",
  1593. .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
  1594. },
  1595. {
  1596. .str = "a_broadcast_frames_xmitted_ok",
  1597. .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
  1598. },
  1599. {
  1600. .str = "a_multicast_frames_received_ok",
  1601. .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
  1602. },
  1603. {
  1604. .str = "a_broadcast_frames_received_ok",
  1605. .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
  1606. },
  1607. {
  1608. .str = "a_in_range_length_errors",
  1609. .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
  1610. },
  1611. {
  1612. .str = "a_out_of_range_length_field",
  1613. .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
  1614. },
  1615. {
  1616. .str = "a_frame_too_long_errors",
  1617. .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
  1618. },
  1619. {
  1620. .str = "a_symbol_error_during_carrier",
  1621. .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
  1622. },
  1623. {
  1624. .str = "a_mac_control_frames_transmitted",
  1625. .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
  1626. },
  1627. {
  1628. .str = "a_mac_control_frames_received",
  1629. .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
  1630. },
  1631. {
  1632. .str = "a_unsupported_opcodes_received",
  1633. .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
  1634. },
  1635. {
  1636. .str = "a_pause_mac_ctrl_frames_received",
  1637. .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
  1638. },
  1639. {
  1640. .str = "a_pause_mac_ctrl_frames_xmitted",
  1641. .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
  1642. },
  1643. };
  1644. #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
  1645. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
  1646. {
  1647. .str = "rx_octets_prio",
  1648. .getter = mlxsw_reg_ppcnt_rx_octets_get,
  1649. },
  1650. {
  1651. .str = "rx_frames_prio",
  1652. .getter = mlxsw_reg_ppcnt_rx_frames_get,
  1653. },
  1654. {
  1655. .str = "tx_octets_prio",
  1656. .getter = mlxsw_reg_ppcnt_tx_octets_get,
  1657. },
  1658. {
  1659. .str = "tx_frames_prio",
  1660. .getter = mlxsw_reg_ppcnt_tx_frames_get,
  1661. },
  1662. {
  1663. .str = "rx_pause_prio",
  1664. .getter = mlxsw_reg_ppcnt_rx_pause_get,
  1665. },
  1666. {
  1667. .str = "rx_pause_duration_prio",
  1668. .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
  1669. },
  1670. {
  1671. .str = "tx_pause_prio",
  1672. .getter = mlxsw_reg_ppcnt_tx_pause_get,
  1673. },
  1674. {
  1675. .str = "tx_pause_duration_prio",
  1676. .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
  1677. },
  1678. };
  1679. #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
  1680. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
  1681. {
  1682. .str = "tc_transmit_queue_tc",
  1683. .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
  1684. .cells_bytes = true,
  1685. },
  1686. {
  1687. .str = "tc_no_buffer_discard_uc_tc",
  1688. .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
  1689. },
  1690. };
  1691. #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
  1692. #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
  1693. (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
  1694. MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
  1695. IEEE_8021QAZ_MAX_TCS)
  1696. static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
  1697. {
  1698. int i;
  1699. for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
  1700. snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
  1701. mlxsw_sp_port_hw_prio_stats[i].str, prio);
  1702. *p += ETH_GSTRING_LEN;
  1703. }
  1704. }
  1705. static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
  1706. {
  1707. int i;
  1708. for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
  1709. snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
  1710. mlxsw_sp_port_hw_tc_stats[i].str, tc);
  1711. *p += ETH_GSTRING_LEN;
  1712. }
  1713. }
  1714. static void mlxsw_sp_port_get_strings(struct net_device *dev,
  1715. u32 stringset, u8 *data)
  1716. {
  1717. u8 *p = data;
  1718. int i;
  1719. switch (stringset) {
  1720. case ETH_SS_STATS:
  1721. for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
  1722. memcpy(p, mlxsw_sp_port_hw_stats[i].str,
  1723. ETH_GSTRING_LEN);
  1724. p += ETH_GSTRING_LEN;
  1725. }
  1726. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  1727. mlxsw_sp_port_get_prio_strings(&p, i);
  1728. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  1729. mlxsw_sp_port_get_tc_strings(&p, i);
  1730. break;
  1731. }
  1732. }
  1733. static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
  1734. enum ethtool_phys_id_state state)
  1735. {
  1736. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1737. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1738. char mlcr_pl[MLXSW_REG_MLCR_LEN];
  1739. bool active;
  1740. switch (state) {
  1741. case ETHTOOL_ID_ACTIVE:
  1742. active = true;
  1743. break;
  1744. case ETHTOOL_ID_INACTIVE:
  1745. active = false;
  1746. break;
  1747. default:
  1748. return -EOPNOTSUPP;
  1749. }
  1750. mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
  1751. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
  1752. }
  1753. static int
  1754. mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
  1755. int *p_len, enum mlxsw_reg_ppcnt_grp grp)
  1756. {
  1757. switch (grp) {
  1758. case MLXSW_REG_PPCNT_IEEE_8023_CNT:
  1759. *p_hw_stats = mlxsw_sp_port_hw_stats;
  1760. *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
  1761. break;
  1762. case MLXSW_REG_PPCNT_PRIO_CNT:
  1763. *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
  1764. *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
  1765. break;
  1766. case MLXSW_REG_PPCNT_TC_CNT:
  1767. *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
  1768. *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
  1769. break;
  1770. default:
  1771. WARN_ON(1);
  1772. return -EOPNOTSUPP;
  1773. }
  1774. return 0;
  1775. }
  1776. static void __mlxsw_sp_port_get_stats(struct net_device *dev,
  1777. enum mlxsw_reg_ppcnt_grp grp, int prio,
  1778. u64 *data, int data_index)
  1779. {
  1780. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1781. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1782. struct mlxsw_sp_port_hw_stats *hw_stats;
  1783. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  1784. int i, len;
  1785. int err;
  1786. err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
  1787. if (err)
  1788. return;
  1789. mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
  1790. for (i = 0; i < len; i++) {
  1791. data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
  1792. if (!hw_stats[i].cells_bytes)
  1793. continue;
  1794. data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
  1795. data[data_index + i]);
  1796. }
  1797. }
  1798. static void mlxsw_sp_port_get_stats(struct net_device *dev,
  1799. struct ethtool_stats *stats, u64 *data)
  1800. {
  1801. int i, data_index = 0;
  1802. /* IEEE 802.3 Counters */
  1803. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
  1804. data, data_index);
  1805. data_index = MLXSW_SP_PORT_HW_STATS_LEN;
  1806. /* Per-Priority Counters */
  1807. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1808. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
  1809. data, data_index);
  1810. data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
  1811. }
  1812. /* Per-TC Counters */
  1813. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1814. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
  1815. data, data_index);
  1816. data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
  1817. }
  1818. }
  1819. static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
  1820. {
  1821. switch (sset) {
  1822. case ETH_SS_STATS:
  1823. return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
  1824. default:
  1825. return -EOPNOTSUPP;
  1826. }
  1827. }
  1828. struct mlxsw_sp_port_link_mode {
  1829. enum ethtool_link_mode_bit_indices mask_ethtool;
  1830. u32 mask;
  1831. u32 speed;
  1832. };
  1833. static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
  1834. {
  1835. .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
  1836. .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
  1837. .speed = SPEED_100,
  1838. },
  1839. {
  1840. .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
  1841. MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
  1842. .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
  1843. .speed = SPEED_1000,
  1844. },
  1845. {
  1846. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
  1847. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  1848. .speed = SPEED_10000,
  1849. },
  1850. {
  1851. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
  1852. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
  1853. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
  1854. .speed = SPEED_10000,
  1855. },
  1856. {
  1857. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  1858. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  1859. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  1860. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
  1861. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
  1862. .speed = SPEED_10000,
  1863. },
  1864. {
  1865. .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
  1866. .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
  1867. .speed = SPEED_20000,
  1868. },
  1869. {
  1870. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
  1871. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
  1872. .speed = SPEED_40000,
  1873. },
  1874. {
  1875. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
  1876. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
  1877. .speed = SPEED_40000,
  1878. },
  1879. {
  1880. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
  1881. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
  1882. .speed = SPEED_40000,
  1883. },
  1884. {
  1885. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
  1886. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
  1887. .speed = SPEED_40000,
  1888. },
  1889. {
  1890. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
  1891. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
  1892. .speed = SPEED_25000,
  1893. },
  1894. {
  1895. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
  1896. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
  1897. .speed = SPEED_25000,
  1898. },
  1899. {
  1900. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
  1901. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
  1902. .speed = SPEED_25000,
  1903. },
  1904. {
  1905. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
  1906. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
  1907. .speed = SPEED_25000,
  1908. },
  1909. {
  1910. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
  1911. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
  1912. .speed = SPEED_50000,
  1913. },
  1914. {
  1915. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
  1916. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
  1917. .speed = SPEED_50000,
  1918. },
  1919. {
  1920. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
  1921. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
  1922. .speed = SPEED_50000,
  1923. },
  1924. {
  1925. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1926. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
  1927. .speed = SPEED_56000,
  1928. },
  1929. {
  1930. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1931. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
  1932. .speed = SPEED_56000,
  1933. },
  1934. {
  1935. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1936. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
  1937. .speed = SPEED_56000,
  1938. },
  1939. {
  1940. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1941. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
  1942. .speed = SPEED_56000,
  1943. },
  1944. {
  1945. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
  1946. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
  1947. .speed = SPEED_100000,
  1948. },
  1949. {
  1950. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
  1951. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
  1952. .speed = SPEED_100000,
  1953. },
  1954. {
  1955. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
  1956. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
  1957. .speed = SPEED_100000,
  1958. },
  1959. {
  1960. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
  1961. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
  1962. .speed = SPEED_100000,
  1963. },
  1964. };
  1965. #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
  1966. static void
  1967. mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
  1968. struct ethtool_link_ksettings *cmd)
  1969. {
  1970. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  1971. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  1972. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
  1973. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
  1974. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
  1975. MLXSW_REG_PTYS_ETH_SPEED_SGMII))
  1976. ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
  1977. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  1978. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
  1979. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
  1980. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
  1981. MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
  1982. ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
  1983. }
  1984. static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
  1985. {
  1986. int i;
  1987. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  1988. if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
  1989. __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
  1990. mode);
  1991. }
  1992. }
  1993. static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
  1994. struct ethtool_link_ksettings *cmd)
  1995. {
  1996. u32 speed = SPEED_UNKNOWN;
  1997. u8 duplex = DUPLEX_UNKNOWN;
  1998. int i;
  1999. if (!carrier_ok)
  2000. goto out;
  2001. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2002. if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
  2003. speed = mlxsw_sp_port_link_mode[i].speed;
  2004. duplex = DUPLEX_FULL;
  2005. break;
  2006. }
  2007. }
  2008. out:
  2009. cmd->base.speed = speed;
  2010. cmd->base.duplex = duplex;
  2011. }
  2012. static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
  2013. {
  2014. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  2015. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
  2016. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
  2017. MLXSW_REG_PTYS_ETH_SPEED_SGMII))
  2018. return PORT_FIBRE;
  2019. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  2020. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
  2021. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
  2022. return PORT_DA;
  2023. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  2024. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
  2025. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
  2026. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
  2027. return PORT_NONE;
  2028. return PORT_OTHER;
  2029. }
  2030. static u32
  2031. mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
  2032. {
  2033. u32 ptys_proto = 0;
  2034. int i;
  2035. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2036. if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
  2037. cmd->link_modes.advertising))
  2038. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2039. }
  2040. return ptys_proto;
  2041. }
  2042. static u32 mlxsw_sp_to_ptys_speed(u32 speed)
  2043. {
  2044. u32 ptys_proto = 0;
  2045. int i;
  2046. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2047. if (speed == mlxsw_sp_port_link_mode[i].speed)
  2048. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2049. }
  2050. return ptys_proto;
  2051. }
  2052. static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
  2053. {
  2054. u32 ptys_proto = 0;
  2055. int i;
  2056. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2057. if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
  2058. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2059. }
  2060. return ptys_proto;
  2061. }
  2062. static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
  2063. struct ethtool_link_ksettings *cmd)
  2064. {
  2065. ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
  2066. ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
  2067. ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
  2068. mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
  2069. mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
  2070. }
  2071. static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
  2072. struct ethtool_link_ksettings *cmd)
  2073. {
  2074. if (!autoneg)
  2075. return;
  2076. ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
  2077. mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
  2078. }
  2079. static void
  2080. mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
  2081. struct ethtool_link_ksettings *cmd)
  2082. {
  2083. if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
  2084. return;
  2085. ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
  2086. mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
  2087. }
  2088. static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
  2089. struct ethtool_link_ksettings *cmd)
  2090. {
  2091. u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
  2092. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2093. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2094. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2095. u8 autoneg_status;
  2096. bool autoneg;
  2097. int err;
  2098. autoneg = mlxsw_sp_port->link.autoneg;
  2099. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
  2100. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2101. if (err)
  2102. return err;
  2103. mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
  2104. &eth_proto_oper);
  2105. mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
  2106. mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
  2107. eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
  2108. autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
  2109. mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
  2110. cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  2111. cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
  2112. mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
  2113. cmd);
  2114. return 0;
  2115. }
  2116. static int
  2117. mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
  2118. const struct ethtool_link_ksettings *cmd)
  2119. {
  2120. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2121. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2122. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2123. u32 eth_proto_cap, eth_proto_new;
  2124. bool autoneg;
  2125. int err;
  2126. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
  2127. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2128. if (err)
  2129. return err;
  2130. mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
  2131. autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
  2132. eth_proto_new = autoneg ?
  2133. mlxsw_sp_to_ptys_advert_link(cmd) :
  2134. mlxsw_sp_to_ptys_speed(cmd->base.speed);
  2135. eth_proto_new = eth_proto_new & eth_proto_cap;
  2136. if (!eth_proto_new) {
  2137. netdev_err(dev, "No supported speed requested\n");
  2138. return -EINVAL;
  2139. }
  2140. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
  2141. eth_proto_new);
  2142. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2143. if (err)
  2144. return err;
  2145. if (!netif_running(dev))
  2146. return 0;
  2147. mlxsw_sp_port->link.autoneg = autoneg;
  2148. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  2149. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  2150. return 0;
  2151. }
  2152. static int mlxsw_sp_flash_device(struct net_device *dev,
  2153. struct ethtool_flash *flash)
  2154. {
  2155. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2156. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2157. const struct firmware *firmware;
  2158. int err;
  2159. if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
  2160. return -EOPNOTSUPP;
  2161. dev_hold(dev);
  2162. rtnl_unlock();
  2163. err = request_firmware_direct(&firmware, flash->data, &dev->dev);
  2164. if (err)
  2165. goto out;
  2166. err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
  2167. release_firmware(firmware);
  2168. out:
  2169. rtnl_lock();
  2170. dev_put(dev);
  2171. return err;
  2172. }
  2173. #define MLXSW_SP_I2C_ADDR_LOW 0x50
  2174. #define MLXSW_SP_I2C_ADDR_HIGH 0x51
  2175. #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
  2176. static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
  2177. u16 offset, u16 size, void *data,
  2178. unsigned int *p_read_size)
  2179. {
  2180. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2181. char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
  2182. char mcia_pl[MLXSW_REG_MCIA_LEN];
  2183. u16 i2c_addr;
  2184. int status;
  2185. int err;
  2186. size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
  2187. if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
  2188. offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
  2189. /* Cross pages read, read until offset 256 in low page */
  2190. size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
  2191. i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
  2192. if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
  2193. i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
  2194. offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
  2195. }
  2196. mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
  2197. 0, 0, offset, size, i2c_addr);
  2198. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
  2199. if (err)
  2200. return err;
  2201. status = mlxsw_reg_mcia_status_get(mcia_pl);
  2202. if (status)
  2203. return -EIO;
  2204. mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
  2205. memcpy(data, eeprom_tmp, size);
  2206. *p_read_size = size;
  2207. return 0;
  2208. }
  2209. enum mlxsw_sp_eeprom_module_info_rev_id {
  2210. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
  2211. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
  2212. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
  2213. };
  2214. enum mlxsw_sp_eeprom_module_info_id {
  2215. MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
  2216. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
  2217. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
  2218. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
  2219. };
  2220. enum mlxsw_sp_eeprom_module_info {
  2221. MLXSW_SP_EEPROM_MODULE_INFO_ID,
  2222. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
  2223. MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
  2224. };
  2225. static int mlxsw_sp_get_module_info(struct net_device *netdev,
  2226. struct ethtool_modinfo *modinfo)
  2227. {
  2228. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
  2229. u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
  2230. u8 module_rev_id, module_id;
  2231. unsigned int read_size;
  2232. int err;
  2233. err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
  2234. MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
  2235. module_info, &read_size);
  2236. if (err)
  2237. return err;
  2238. if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
  2239. return -EIO;
  2240. module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
  2241. module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
  2242. switch (module_id) {
  2243. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
  2244. modinfo->type = ETH_MODULE_SFF_8436;
  2245. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  2246. break;
  2247. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
  2248. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
  2249. if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
  2250. module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
  2251. modinfo->type = ETH_MODULE_SFF_8636;
  2252. modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
  2253. } else {
  2254. modinfo->type = ETH_MODULE_SFF_8436;
  2255. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  2256. }
  2257. break;
  2258. case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
  2259. modinfo->type = ETH_MODULE_SFF_8472;
  2260. modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
  2261. break;
  2262. default:
  2263. return -EINVAL;
  2264. }
  2265. return 0;
  2266. }
  2267. static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
  2268. struct ethtool_eeprom *ee,
  2269. u8 *data)
  2270. {
  2271. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
  2272. int offset = ee->offset;
  2273. unsigned int read_size;
  2274. int i = 0;
  2275. int err;
  2276. if (!ee->len)
  2277. return -EINVAL;
  2278. memset(data, 0, ee->len);
  2279. while (i < ee->len) {
  2280. err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
  2281. ee->len - i, data + i,
  2282. &read_size);
  2283. if (err) {
  2284. netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
  2285. return err;
  2286. }
  2287. i += read_size;
  2288. offset += read_size;
  2289. }
  2290. return 0;
  2291. }
  2292. static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
  2293. .get_drvinfo = mlxsw_sp_port_get_drvinfo,
  2294. .get_link = ethtool_op_get_link,
  2295. .get_pauseparam = mlxsw_sp_port_get_pauseparam,
  2296. .set_pauseparam = mlxsw_sp_port_set_pauseparam,
  2297. .get_strings = mlxsw_sp_port_get_strings,
  2298. .set_phys_id = mlxsw_sp_port_set_phys_id,
  2299. .get_ethtool_stats = mlxsw_sp_port_get_stats,
  2300. .get_sset_count = mlxsw_sp_port_get_sset_count,
  2301. .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
  2302. .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
  2303. .flash_device = mlxsw_sp_flash_device,
  2304. .get_module_info = mlxsw_sp_get_module_info,
  2305. .get_module_eeprom = mlxsw_sp_get_module_eeprom,
  2306. };
  2307. static int
  2308. mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
  2309. {
  2310. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2311. u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
  2312. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2313. u32 eth_proto_admin;
  2314. eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
  2315. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
  2316. eth_proto_admin);
  2317. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2318. }
  2319. int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2320. enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
  2321. bool dwrr, u8 dwrr_weight)
  2322. {
  2323. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2324. char qeec_pl[MLXSW_REG_QEEC_LEN];
  2325. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  2326. next_index);
  2327. mlxsw_reg_qeec_de_set(qeec_pl, true);
  2328. mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
  2329. mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
  2330. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  2331. }
  2332. int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2333. enum mlxsw_reg_qeec_hr hr, u8 index,
  2334. u8 next_index, u32 maxrate)
  2335. {
  2336. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2337. char qeec_pl[MLXSW_REG_QEEC_LEN];
  2338. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  2339. next_index);
  2340. mlxsw_reg_qeec_mase_set(qeec_pl, true);
  2341. mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
  2342. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  2343. }
  2344. int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2345. u8 switch_prio, u8 tclass)
  2346. {
  2347. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2348. char qtct_pl[MLXSW_REG_QTCT_LEN];
  2349. mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
  2350. tclass);
  2351. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
  2352. }
  2353. static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
  2354. {
  2355. int err, i;
  2356. /* Setup the elements hierarcy, so that each TC is linked to
  2357. * one subgroup, which are all member in the same group.
  2358. */
  2359. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2360. MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
  2361. 0);
  2362. if (err)
  2363. return err;
  2364. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2365. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2366. MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
  2367. 0, false, 0);
  2368. if (err)
  2369. return err;
  2370. }
  2371. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2372. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2373. MLXSW_REG_QEEC_HIERARCY_TC, i, i,
  2374. false, 0);
  2375. if (err)
  2376. return err;
  2377. }
  2378. /* Make sure the max shaper is disabled in all hierarcies that
  2379. * support it.
  2380. */
  2381. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2382. MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
  2383. MLXSW_REG_QEEC_MAS_DIS);
  2384. if (err)
  2385. return err;
  2386. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2387. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2388. MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
  2389. i, 0,
  2390. MLXSW_REG_QEEC_MAS_DIS);
  2391. if (err)
  2392. return err;
  2393. }
  2394. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2395. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2396. MLXSW_REG_QEEC_HIERARCY_TC,
  2397. i, i,
  2398. MLXSW_REG_QEEC_MAS_DIS);
  2399. if (err)
  2400. return err;
  2401. }
  2402. /* Map all priorities to traffic class 0. */
  2403. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2404. err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
  2405. if (err)
  2406. return err;
  2407. }
  2408. return 0;
  2409. }
  2410. static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  2411. bool split, u8 module, u8 width, u8 lane)
  2412. {
  2413. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  2414. struct mlxsw_sp_port *mlxsw_sp_port;
  2415. struct net_device *dev;
  2416. int err;
  2417. err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
  2418. if (err) {
  2419. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
  2420. local_port);
  2421. return err;
  2422. }
  2423. dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
  2424. if (!dev) {
  2425. err = -ENOMEM;
  2426. goto err_alloc_etherdev;
  2427. }
  2428. SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
  2429. mlxsw_sp_port = netdev_priv(dev);
  2430. mlxsw_sp_port->dev = dev;
  2431. mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
  2432. mlxsw_sp_port->local_port = local_port;
  2433. mlxsw_sp_port->pvid = 1;
  2434. mlxsw_sp_port->split = split;
  2435. mlxsw_sp_port->mapping.module = module;
  2436. mlxsw_sp_port->mapping.width = width;
  2437. mlxsw_sp_port->mapping.lane = lane;
  2438. mlxsw_sp_port->link.autoneg = 1;
  2439. INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
  2440. INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
  2441. mlxsw_sp_port->pcpu_stats =
  2442. netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
  2443. if (!mlxsw_sp_port->pcpu_stats) {
  2444. err = -ENOMEM;
  2445. goto err_alloc_stats;
  2446. }
  2447. mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
  2448. GFP_KERNEL);
  2449. if (!mlxsw_sp_port->sample) {
  2450. err = -ENOMEM;
  2451. goto err_alloc_sample;
  2452. }
  2453. mlxsw_sp_port->hw_stats.cache =
  2454. kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
  2455. if (!mlxsw_sp_port->hw_stats.cache) {
  2456. err = -ENOMEM;
  2457. goto err_alloc_hw_stats;
  2458. }
  2459. INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
  2460. &update_stats_cache);
  2461. dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
  2462. dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
  2463. err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
  2464. if (err) {
  2465. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
  2466. mlxsw_sp_port->local_port);
  2467. goto err_port_module_map;
  2468. }
  2469. err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
  2470. if (err) {
  2471. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
  2472. mlxsw_sp_port->local_port);
  2473. goto err_port_swid_set;
  2474. }
  2475. err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
  2476. if (err) {
  2477. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
  2478. mlxsw_sp_port->local_port);
  2479. goto err_dev_addr_init;
  2480. }
  2481. netif_carrier_off(dev);
  2482. dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
  2483. NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
  2484. dev->hw_features |= NETIF_F_HW_TC;
  2485. dev->min_mtu = 0;
  2486. dev->max_mtu = ETH_MAX_MTU;
  2487. /* Each packet needs to have a Tx header (metadata) on top all other
  2488. * headers.
  2489. */
  2490. dev->needed_headroom = MLXSW_TXHDR_LEN;
  2491. err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
  2492. if (err) {
  2493. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
  2494. mlxsw_sp_port->local_port);
  2495. goto err_port_system_port_mapping_set;
  2496. }
  2497. err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
  2498. if (err) {
  2499. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
  2500. mlxsw_sp_port->local_port);
  2501. goto err_port_speed_by_width_set;
  2502. }
  2503. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
  2504. if (err) {
  2505. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
  2506. mlxsw_sp_port->local_port);
  2507. goto err_port_mtu_set;
  2508. }
  2509. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  2510. if (err)
  2511. goto err_port_admin_status_set;
  2512. err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
  2513. if (err) {
  2514. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
  2515. mlxsw_sp_port->local_port);
  2516. goto err_port_buffers_init;
  2517. }
  2518. err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
  2519. if (err) {
  2520. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
  2521. mlxsw_sp_port->local_port);
  2522. goto err_port_ets_init;
  2523. }
  2524. /* ETS and buffers must be initialized before DCB. */
  2525. err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
  2526. if (err) {
  2527. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
  2528. mlxsw_sp_port->local_port);
  2529. goto err_port_dcb_init;
  2530. }
  2531. err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
  2532. if (err) {
  2533. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
  2534. mlxsw_sp_port->local_port);
  2535. goto err_port_fids_init;
  2536. }
  2537. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
  2538. if (IS_ERR(mlxsw_sp_port_vlan)) {
  2539. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
  2540. mlxsw_sp_port->local_port);
  2541. goto err_port_vlan_get;
  2542. }
  2543. mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
  2544. mlxsw_sp->ports[local_port] = mlxsw_sp_port;
  2545. err = register_netdev(dev);
  2546. if (err) {
  2547. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
  2548. mlxsw_sp_port->local_port);
  2549. goto err_register_netdev;
  2550. }
  2551. mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
  2552. mlxsw_sp_port, dev, mlxsw_sp_port->split,
  2553. module);
  2554. mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
  2555. return 0;
  2556. err_register_netdev:
  2557. mlxsw_sp->ports[local_port] = NULL;
  2558. mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
  2559. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  2560. err_port_vlan_get:
  2561. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  2562. err_port_fids_init:
  2563. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  2564. err_port_dcb_init:
  2565. err_port_ets_init:
  2566. err_port_buffers_init:
  2567. err_port_admin_status_set:
  2568. err_port_mtu_set:
  2569. err_port_speed_by_width_set:
  2570. err_port_system_port_mapping_set:
  2571. err_dev_addr_init:
  2572. mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
  2573. err_port_swid_set:
  2574. mlxsw_sp_port_module_unmap(mlxsw_sp_port);
  2575. err_port_module_map:
  2576. kfree(mlxsw_sp_port->hw_stats.cache);
  2577. err_alloc_hw_stats:
  2578. kfree(mlxsw_sp_port->sample);
  2579. err_alloc_sample:
  2580. free_percpu(mlxsw_sp_port->pcpu_stats);
  2581. err_alloc_stats:
  2582. free_netdev(dev);
  2583. err_alloc_etherdev:
  2584. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  2585. return err;
  2586. }
  2587. static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
  2588. {
  2589. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2590. cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
  2591. mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
  2592. unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
  2593. mlxsw_sp->ports[local_port] = NULL;
  2594. mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
  2595. mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
  2596. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  2597. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  2598. mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
  2599. mlxsw_sp_port_module_unmap(mlxsw_sp_port);
  2600. kfree(mlxsw_sp_port->hw_stats.cache);
  2601. kfree(mlxsw_sp_port->sample);
  2602. free_percpu(mlxsw_sp_port->pcpu_stats);
  2603. WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
  2604. free_netdev(mlxsw_sp_port->dev);
  2605. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  2606. }
  2607. static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
  2608. {
  2609. return mlxsw_sp->ports[local_port] != NULL;
  2610. }
  2611. static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
  2612. {
  2613. int i;
  2614. for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
  2615. if (mlxsw_sp_port_created(mlxsw_sp, i))
  2616. mlxsw_sp_port_remove(mlxsw_sp, i);
  2617. kfree(mlxsw_sp->port_to_module);
  2618. kfree(mlxsw_sp->ports);
  2619. }
  2620. static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
  2621. {
  2622. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  2623. u8 module, width, lane;
  2624. size_t alloc_size;
  2625. int i;
  2626. int err;
  2627. alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
  2628. mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
  2629. if (!mlxsw_sp->ports)
  2630. return -ENOMEM;
  2631. mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
  2632. if (!mlxsw_sp->port_to_module) {
  2633. err = -ENOMEM;
  2634. goto err_port_to_module_alloc;
  2635. }
  2636. for (i = 1; i < max_ports; i++) {
  2637. err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
  2638. &width, &lane);
  2639. if (err)
  2640. goto err_port_module_info_get;
  2641. if (!width)
  2642. continue;
  2643. mlxsw_sp->port_to_module[i] = module;
  2644. err = mlxsw_sp_port_create(mlxsw_sp, i, false,
  2645. module, width, lane);
  2646. if (err)
  2647. goto err_port_create;
  2648. }
  2649. return 0;
  2650. err_port_create:
  2651. err_port_module_info_get:
  2652. for (i--; i >= 1; i--)
  2653. if (mlxsw_sp_port_created(mlxsw_sp, i))
  2654. mlxsw_sp_port_remove(mlxsw_sp, i);
  2655. kfree(mlxsw_sp->port_to_module);
  2656. err_port_to_module_alloc:
  2657. kfree(mlxsw_sp->ports);
  2658. return err;
  2659. }
  2660. static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
  2661. {
  2662. u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
  2663. return local_port - offset;
  2664. }
  2665. static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
  2666. u8 module, unsigned int count)
  2667. {
  2668. u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
  2669. int err, i;
  2670. for (i = 0; i < count; i++) {
  2671. err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
  2672. module, width, i * width);
  2673. if (err)
  2674. goto err_port_create;
  2675. }
  2676. return 0;
  2677. err_port_create:
  2678. for (i--; i >= 0; i--)
  2679. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2680. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2681. return err;
  2682. }
  2683. static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
  2684. u8 base_port, unsigned int count)
  2685. {
  2686. u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
  2687. int i;
  2688. /* Split by four means we need to re-create two ports, otherwise
  2689. * only one.
  2690. */
  2691. count = count / 2;
  2692. for (i = 0; i < count; i++) {
  2693. local_port = base_port + i * 2;
  2694. module = mlxsw_sp->port_to_module[local_port];
  2695. mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
  2696. width, 0);
  2697. }
  2698. }
  2699. static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
  2700. unsigned int count)
  2701. {
  2702. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2703. struct mlxsw_sp_port *mlxsw_sp_port;
  2704. u8 module, cur_width, base_port;
  2705. int i;
  2706. int err;
  2707. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2708. if (!mlxsw_sp_port) {
  2709. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  2710. local_port);
  2711. return -EINVAL;
  2712. }
  2713. module = mlxsw_sp_port->mapping.module;
  2714. cur_width = mlxsw_sp_port->mapping.width;
  2715. if (count != 2 && count != 4) {
  2716. netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
  2717. return -EINVAL;
  2718. }
  2719. if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
  2720. netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
  2721. return -EINVAL;
  2722. }
  2723. /* Make sure we have enough slave (even) ports for the split. */
  2724. if (count == 2) {
  2725. base_port = local_port;
  2726. if (mlxsw_sp->ports[base_port + 1]) {
  2727. netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
  2728. return -EINVAL;
  2729. }
  2730. } else {
  2731. base_port = mlxsw_sp_cluster_base_port_get(local_port);
  2732. if (mlxsw_sp->ports[base_port + 1] ||
  2733. mlxsw_sp->ports[base_port + 3]) {
  2734. netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
  2735. return -EINVAL;
  2736. }
  2737. }
  2738. for (i = 0; i < count; i++)
  2739. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2740. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2741. err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
  2742. if (err) {
  2743. dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
  2744. goto err_port_split_create;
  2745. }
  2746. return 0;
  2747. err_port_split_create:
  2748. mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
  2749. return err;
  2750. }
  2751. static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
  2752. {
  2753. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2754. struct mlxsw_sp_port *mlxsw_sp_port;
  2755. u8 cur_width, base_port;
  2756. unsigned int count;
  2757. int i;
  2758. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2759. if (!mlxsw_sp_port) {
  2760. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  2761. local_port);
  2762. return -EINVAL;
  2763. }
  2764. if (!mlxsw_sp_port->split) {
  2765. netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
  2766. return -EINVAL;
  2767. }
  2768. cur_width = mlxsw_sp_port->mapping.width;
  2769. count = cur_width == 1 ? 4 : 2;
  2770. base_port = mlxsw_sp_cluster_base_port_get(local_port);
  2771. /* Determine which ports to remove. */
  2772. if (count == 2 && local_port >= base_port + 2)
  2773. base_port = base_port + 2;
  2774. for (i = 0; i < count; i++)
  2775. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2776. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2777. mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
  2778. return 0;
  2779. }
  2780. static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
  2781. char *pude_pl, void *priv)
  2782. {
  2783. struct mlxsw_sp *mlxsw_sp = priv;
  2784. struct mlxsw_sp_port *mlxsw_sp_port;
  2785. enum mlxsw_reg_pude_oper_status status;
  2786. u8 local_port;
  2787. local_port = mlxsw_reg_pude_local_port_get(pude_pl);
  2788. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2789. if (!mlxsw_sp_port)
  2790. return;
  2791. status = mlxsw_reg_pude_oper_status_get(pude_pl);
  2792. if (status == MLXSW_PORT_OPER_STATUS_UP) {
  2793. netdev_info(mlxsw_sp_port->dev, "link up\n");
  2794. netif_carrier_on(mlxsw_sp_port->dev);
  2795. } else {
  2796. netdev_info(mlxsw_sp_port->dev, "link down\n");
  2797. netif_carrier_off(mlxsw_sp_port->dev);
  2798. }
  2799. }
  2800. static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
  2801. u8 local_port, void *priv)
  2802. {
  2803. struct mlxsw_sp *mlxsw_sp = priv;
  2804. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2805. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  2806. if (unlikely(!mlxsw_sp_port)) {
  2807. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
  2808. local_port);
  2809. return;
  2810. }
  2811. skb->dev = mlxsw_sp_port->dev;
  2812. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  2813. u64_stats_update_begin(&pcpu_stats->syncp);
  2814. pcpu_stats->rx_packets++;
  2815. pcpu_stats->rx_bytes += skb->len;
  2816. u64_stats_update_end(&pcpu_stats->syncp);
  2817. skb->protocol = eth_type_trans(skb, skb->dev);
  2818. netif_receive_skb(skb);
  2819. }
  2820. static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
  2821. void *priv)
  2822. {
  2823. skb->offload_fwd_mark = 1;
  2824. return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
  2825. }
  2826. static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
  2827. void *priv)
  2828. {
  2829. struct mlxsw_sp *mlxsw_sp = priv;
  2830. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2831. struct psample_group *psample_group;
  2832. u32 size;
  2833. if (unlikely(!mlxsw_sp_port)) {
  2834. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
  2835. local_port);
  2836. goto out;
  2837. }
  2838. if (unlikely(!mlxsw_sp_port->sample)) {
  2839. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
  2840. local_port);
  2841. goto out;
  2842. }
  2843. size = mlxsw_sp_port->sample->truncate ?
  2844. mlxsw_sp_port->sample->trunc_size : skb->len;
  2845. rcu_read_lock();
  2846. psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
  2847. if (!psample_group)
  2848. goto out_unlock;
  2849. psample_sample_packet(psample_group, skb, size,
  2850. mlxsw_sp_port->dev->ifindex, 0,
  2851. mlxsw_sp_port->sample->rate);
  2852. out_unlock:
  2853. rcu_read_unlock();
  2854. out:
  2855. consume_skb(skb);
  2856. }
  2857. #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2858. MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
  2859. _is_ctrl, SP_##_trap_group, DISCARD)
  2860. #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2861. MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
  2862. _is_ctrl, SP_##_trap_group, DISCARD)
  2863. #define MLXSW_SP_EVENTL(_func, _trap_id) \
  2864. MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
  2865. static const struct mlxsw_listener mlxsw_sp_listener[] = {
  2866. /* Events */
  2867. MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
  2868. /* L2 traps */
  2869. MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
  2870. MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
  2871. MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
  2872. MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
  2873. MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
  2874. MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
  2875. MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
  2876. MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
  2877. MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
  2878. MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
  2879. MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
  2880. MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
  2881. MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
  2882. false),
  2883. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
  2884. false),
  2885. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
  2886. false),
  2887. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
  2888. false),
  2889. /* L3 traps */
  2890. MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2891. MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2892. MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2893. MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
  2894. MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
  2895. false),
  2896. MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
  2897. MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
  2898. MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
  2899. MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
  2900. false),
  2901. MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
  2902. MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
  2903. MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
  2904. MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
  2905. MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
  2906. MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
  2907. MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
  2908. false),
  2909. MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
  2910. false),
  2911. MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
  2912. false),
  2913. MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
  2914. false),
  2915. MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
  2916. MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
  2917. false),
  2918. MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
  2919. MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
  2920. MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
  2921. MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
  2922. MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2923. /* PKT Sample trap */
  2924. MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
  2925. false, SP_IP2ME, DISCARD),
  2926. /* ACL trap */
  2927. MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
  2928. /* Multicast Router Traps */
  2929. MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
  2930. MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
  2931. MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
  2932. };
  2933. static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
  2934. {
  2935. char qpcr_pl[MLXSW_REG_QPCR_LEN];
  2936. enum mlxsw_reg_qpcr_ir_units ir_units;
  2937. int max_cpu_policers;
  2938. bool is_bytes;
  2939. u8 burst_size;
  2940. u32 rate;
  2941. int i, err;
  2942. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
  2943. return -EIO;
  2944. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  2945. ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
  2946. for (i = 0; i < max_cpu_policers; i++) {
  2947. is_bytes = false;
  2948. switch (i) {
  2949. case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
  2950. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
  2951. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
  2952. case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
  2953. case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
  2954. case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
  2955. rate = 128;
  2956. burst_size = 7;
  2957. break;
  2958. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
  2959. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
  2960. rate = 16 * 1024;
  2961. burst_size = 10;
  2962. break;
  2963. case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
  2964. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
  2965. case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
  2966. case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
  2967. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  2968. case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
  2969. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
  2970. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  2971. rate = 1024;
  2972. burst_size = 7;
  2973. break;
  2974. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
  2975. is_bytes = true;
  2976. rate = 4 * 1024;
  2977. burst_size = 4;
  2978. break;
  2979. default:
  2980. continue;
  2981. }
  2982. mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
  2983. burst_size);
  2984. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
  2985. if (err)
  2986. return err;
  2987. }
  2988. return 0;
  2989. }
  2990. static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
  2991. {
  2992. char htgt_pl[MLXSW_REG_HTGT_LEN];
  2993. enum mlxsw_reg_htgt_trap_group i;
  2994. int max_cpu_policers;
  2995. int max_trap_groups;
  2996. u8 priority, tc;
  2997. u16 policer_id;
  2998. int err;
  2999. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
  3000. return -EIO;
  3001. max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
  3002. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  3003. for (i = 0; i < max_trap_groups; i++) {
  3004. policer_id = i;
  3005. switch (i) {
  3006. case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
  3007. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
  3008. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
  3009. case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
  3010. case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
  3011. priority = 5;
  3012. tc = 5;
  3013. break;
  3014. case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
  3015. case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
  3016. priority = 4;
  3017. tc = 4;
  3018. break;
  3019. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
  3020. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
  3021. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
  3022. priority = 3;
  3023. tc = 3;
  3024. break;
  3025. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
  3026. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
  3027. case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
  3028. priority = 2;
  3029. tc = 2;
  3030. break;
  3031. case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
  3032. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  3033. case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
  3034. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  3035. priority = 1;
  3036. tc = 1;
  3037. break;
  3038. case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
  3039. priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
  3040. tc = MLXSW_REG_HTGT_DEFAULT_TC;
  3041. policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
  3042. break;
  3043. default:
  3044. continue;
  3045. }
  3046. if (max_cpu_policers <= policer_id &&
  3047. policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
  3048. return -EIO;
  3049. mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
  3050. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  3051. if (err)
  3052. return err;
  3053. }
  3054. return 0;
  3055. }
  3056. static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
  3057. {
  3058. int i;
  3059. int err;
  3060. err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
  3061. if (err)
  3062. return err;
  3063. err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
  3064. if (err)
  3065. return err;
  3066. for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
  3067. err = mlxsw_core_trap_register(mlxsw_sp->core,
  3068. &mlxsw_sp_listener[i],
  3069. mlxsw_sp);
  3070. if (err)
  3071. goto err_listener_register;
  3072. }
  3073. return 0;
  3074. err_listener_register:
  3075. for (i--; i >= 0; i--) {
  3076. mlxsw_core_trap_unregister(mlxsw_sp->core,
  3077. &mlxsw_sp_listener[i],
  3078. mlxsw_sp);
  3079. }
  3080. return err;
  3081. }
  3082. static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
  3083. {
  3084. int i;
  3085. for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
  3086. mlxsw_core_trap_unregister(mlxsw_sp->core,
  3087. &mlxsw_sp_listener[i],
  3088. mlxsw_sp);
  3089. }
  3090. }
  3091. static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
  3092. {
  3093. char slcr_pl[MLXSW_REG_SLCR_LEN];
  3094. int err;
  3095. mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
  3096. MLXSW_REG_SLCR_LAG_HASH_DMAC |
  3097. MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
  3098. MLXSW_REG_SLCR_LAG_HASH_VLANID |
  3099. MLXSW_REG_SLCR_LAG_HASH_SIP |
  3100. MLXSW_REG_SLCR_LAG_HASH_DIP |
  3101. MLXSW_REG_SLCR_LAG_HASH_SPORT |
  3102. MLXSW_REG_SLCR_LAG_HASH_DPORT |
  3103. MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
  3104. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
  3105. if (err)
  3106. return err;
  3107. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
  3108. !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
  3109. return -EIO;
  3110. mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
  3111. sizeof(struct mlxsw_sp_upper),
  3112. GFP_KERNEL);
  3113. if (!mlxsw_sp->lags)
  3114. return -ENOMEM;
  3115. return 0;
  3116. }
  3117. static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
  3118. {
  3119. kfree(mlxsw_sp->lags);
  3120. }
  3121. static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
  3122. {
  3123. char htgt_pl[MLXSW_REG_HTGT_LEN];
  3124. mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
  3125. MLXSW_REG_HTGT_INVALID_POLICER,
  3126. MLXSW_REG_HTGT_DEFAULT_PRIORITY,
  3127. MLXSW_REG_HTGT_DEFAULT_TC);
  3128. return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  3129. }
  3130. static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
  3131. const struct mlxsw_bus_info *mlxsw_bus_info)
  3132. {
  3133. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3134. int err;
  3135. mlxsw_sp->core = mlxsw_core;
  3136. mlxsw_sp->bus_info = mlxsw_bus_info;
  3137. err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
  3138. if (err) {
  3139. dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
  3140. return err;
  3141. }
  3142. err = mlxsw_sp_base_mac_get(mlxsw_sp);
  3143. if (err) {
  3144. dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
  3145. return err;
  3146. }
  3147. err = mlxsw_sp_fids_init(mlxsw_sp);
  3148. if (err) {
  3149. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
  3150. return err;
  3151. }
  3152. err = mlxsw_sp_traps_init(mlxsw_sp);
  3153. if (err) {
  3154. dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
  3155. goto err_traps_init;
  3156. }
  3157. err = mlxsw_sp_buffers_init(mlxsw_sp);
  3158. if (err) {
  3159. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
  3160. goto err_buffers_init;
  3161. }
  3162. err = mlxsw_sp_lag_init(mlxsw_sp);
  3163. if (err) {
  3164. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
  3165. goto err_lag_init;
  3166. }
  3167. err = mlxsw_sp_switchdev_init(mlxsw_sp);
  3168. if (err) {
  3169. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
  3170. goto err_switchdev_init;
  3171. }
  3172. err = mlxsw_sp_counter_pool_init(mlxsw_sp);
  3173. if (err) {
  3174. dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
  3175. goto err_counter_pool_init;
  3176. }
  3177. err = mlxsw_sp_afa_init(mlxsw_sp);
  3178. if (err) {
  3179. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
  3180. goto err_afa_init;
  3181. }
  3182. err = mlxsw_sp_router_init(mlxsw_sp);
  3183. if (err) {
  3184. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
  3185. goto err_router_init;
  3186. }
  3187. err = mlxsw_sp_span_init(mlxsw_sp);
  3188. if (err) {
  3189. dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
  3190. goto err_span_init;
  3191. }
  3192. err = mlxsw_sp_acl_init(mlxsw_sp);
  3193. if (err) {
  3194. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
  3195. goto err_acl_init;
  3196. }
  3197. err = mlxsw_sp_dpipe_init(mlxsw_sp);
  3198. if (err) {
  3199. dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
  3200. goto err_dpipe_init;
  3201. }
  3202. err = mlxsw_sp_ports_create(mlxsw_sp);
  3203. if (err) {
  3204. dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
  3205. goto err_ports_create;
  3206. }
  3207. return 0;
  3208. err_ports_create:
  3209. mlxsw_sp_dpipe_fini(mlxsw_sp);
  3210. err_dpipe_init:
  3211. mlxsw_sp_acl_fini(mlxsw_sp);
  3212. err_acl_init:
  3213. mlxsw_sp_span_fini(mlxsw_sp);
  3214. err_span_init:
  3215. mlxsw_sp_router_fini(mlxsw_sp);
  3216. err_router_init:
  3217. mlxsw_sp_afa_fini(mlxsw_sp);
  3218. err_afa_init:
  3219. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  3220. err_counter_pool_init:
  3221. mlxsw_sp_switchdev_fini(mlxsw_sp);
  3222. err_switchdev_init:
  3223. mlxsw_sp_lag_fini(mlxsw_sp);
  3224. err_lag_init:
  3225. mlxsw_sp_buffers_fini(mlxsw_sp);
  3226. err_buffers_init:
  3227. mlxsw_sp_traps_fini(mlxsw_sp);
  3228. err_traps_init:
  3229. mlxsw_sp_fids_fini(mlxsw_sp);
  3230. return err;
  3231. }
  3232. static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
  3233. {
  3234. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3235. mlxsw_sp_ports_remove(mlxsw_sp);
  3236. mlxsw_sp_dpipe_fini(mlxsw_sp);
  3237. mlxsw_sp_acl_fini(mlxsw_sp);
  3238. mlxsw_sp_span_fini(mlxsw_sp);
  3239. mlxsw_sp_router_fini(mlxsw_sp);
  3240. mlxsw_sp_afa_fini(mlxsw_sp);
  3241. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  3242. mlxsw_sp_switchdev_fini(mlxsw_sp);
  3243. mlxsw_sp_lag_fini(mlxsw_sp);
  3244. mlxsw_sp_buffers_fini(mlxsw_sp);
  3245. mlxsw_sp_traps_fini(mlxsw_sp);
  3246. mlxsw_sp_fids_fini(mlxsw_sp);
  3247. }
  3248. static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
  3249. .used_max_vepa_channels = 1,
  3250. .max_vepa_channels = 0,
  3251. .used_max_mid = 1,
  3252. .max_mid = MLXSW_SP_MID_MAX,
  3253. .used_max_pgt = 1,
  3254. .max_pgt = 0,
  3255. .used_flood_tables = 1,
  3256. .used_flood_mode = 1,
  3257. .flood_mode = 3,
  3258. .max_fid_offset_flood_tables = 3,
  3259. .fid_offset_flood_table_size = VLAN_N_VID - 1,
  3260. .max_fid_flood_tables = 3,
  3261. .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
  3262. .used_max_ib_mc = 1,
  3263. .max_ib_mc = 0,
  3264. .used_max_pkey = 1,
  3265. .max_pkey = 0,
  3266. .used_kvd_split_data = 1,
  3267. .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
  3268. .kvd_hash_single_parts = 2,
  3269. .kvd_hash_double_parts = 1,
  3270. .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
  3271. .swid_config = {
  3272. {
  3273. .used_type = 1,
  3274. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3275. }
  3276. },
  3277. .resource_query_enable = 1,
  3278. };
  3279. static struct mlxsw_driver mlxsw_sp_driver = {
  3280. .kind = mlxsw_sp_driver_name,
  3281. .priv_size = sizeof(struct mlxsw_sp),
  3282. .init = mlxsw_sp_init,
  3283. .fini = mlxsw_sp_fini,
  3284. .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
  3285. .port_split = mlxsw_sp_port_split,
  3286. .port_unsplit = mlxsw_sp_port_unsplit,
  3287. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3288. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3289. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3290. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3291. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3292. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3293. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3294. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3295. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3296. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3297. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3298. .txhdr_len = MLXSW_TXHDR_LEN,
  3299. .profile = &mlxsw_sp_config_profile,
  3300. };
  3301. bool mlxsw_sp_port_dev_check(const struct net_device *dev)
  3302. {
  3303. return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
  3304. }
  3305. static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
  3306. {
  3307. struct mlxsw_sp_port **p_mlxsw_sp_port = data;
  3308. int ret = 0;
  3309. if (mlxsw_sp_port_dev_check(lower_dev)) {
  3310. *p_mlxsw_sp_port = netdev_priv(lower_dev);
  3311. ret = 1;
  3312. }
  3313. return ret;
  3314. }
  3315. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
  3316. {
  3317. struct mlxsw_sp_port *mlxsw_sp_port;
  3318. if (mlxsw_sp_port_dev_check(dev))
  3319. return netdev_priv(dev);
  3320. mlxsw_sp_port = NULL;
  3321. netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
  3322. return mlxsw_sp_port;
  3323. }
  3324. struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
  3325. {
  3326. struct mlxsw_sp_port *mlxsw_sp_port;
  3327. mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
  3328. return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
  3329. }
  3330. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
  3331. {
  3332. struct mlxsw_sp_port *mlxsw_sp_port;
  3333. if (mlxsw_sp_port_dev_check(dev))
  3334. return netdev_priv(dev);
  3335. mlxsw_sp_port = NULL;
  3336. netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
  3337. &mlxsw_sp_port);
  3338. return mlxsw_sp_port;
  3339. }
  3340. struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
  3341. {
  3342. struct mlxsw_sp_port *mlxsw_sp_port;
  3343. rcu_read_lock();
  3344. mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
  3345. if (mlxsw_sp_port)
  3346. dev_hold(mlxsw_sp_port->dev);
  3347. rcu_read_unlock();
  3348. return mlxsw_sp_port;
  3349. }
  3350. void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
  3351. {
  3352. dev_put(mlxsw_sp_port->dev);
  3353. }
  3354. static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
  3355. {
  3356. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3357. mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
  3358. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3359. }
  3360. static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
  3361. {
  3362. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3363. mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
  3364. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3365. }
  3366. static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3367. u16 lag_id, u8 port_index)
  3368. {
  3369. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3370. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3371. mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
  3372. lag_id, port_index);
  3373. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3374. }
  3375. static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3376. u16 lag_id)
  3377. {
  3378. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3379. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3380. mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
  3381. lag_id);
  3382. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3383. }
  3384. static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
  3385. u16 lag_id)
  3386. {
  3387. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3388. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3389. mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3390. lag_id);
  3391. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3392. }
  3393. static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
  3394. u16 lag_id)
  3395. {
  3396. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3397. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3398. mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3399. lag_id);
  3400. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3401. }
  3402. static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
  3403. struct net_device *lag_dev,
  3404. u16 *p_lag_id)
  3405. {
  3406. struct mlxsw_sp_upper *lag;
  3407. int free_lag_id = -1;
  3408. u64 max_lag;
  3409. int i;
  3410. max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
  3411. for (i = 0; i < max_lag; i++) {
  3412. lag = mlxsw_sp_lag_get(mlxsw_sp, i);
  3413. if (lag->ref_count) {
  3414. if (lag->dev == lag_dev) {
  3415. *p_lag_id = i;
  3416. return 0;
  3417. }
  3418. } else if (free_lag_id < 0) {
  3419. free_lag_id = i;
  3420. }
  3421. }
  3422. if (free_lag_id < 0)
  3423. return -EBUSY;
  3424. *p_lag_id = free_lag_id;
  3425. return 0;
  3426. }
  3427. static bool
  3428. mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
  3429. struct net_device *lag_dev,
  3430. struct netdev_lag_upper_info *lag_upper_info)
  3431. {
  3432. u16 lag_id;
  3433. if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
  3434. return false;
  3435. if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
  3436. return false;
  3437. return true;
  3438. }
  3439. static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
  3440. u16 lag_id, u8 *p_port_index)
  3441. {
  3442. u64 max_lag_members;
  3443. int i;
  3444. max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
  3445. MAX_LAG_MEMBERS);
  3446. for (i = 0; i < max_lag_members; i++) {
  3447. if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
  3448. *p_port_index = i;
  3449. return 0;
  3450. }
  3451. }
  3452. return -EBUSY;
  3453. }
  3454. static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
  3455. struct net_device *lag_dev)
  3456. {
  3457. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3458. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  3459. struct mlxsw_sp_upper *lag;
  3460. u16 lag_id;
  3461. u8 port_index;
  3462. int err;
  3463. err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
  3464. if (err)
  3465. return err;
  3466. lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
  3467. if (!lag->ref_count) {
  3468. err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
  3469. if (err)
  3470. return err;
  3471. lag->dev = lag_dev;
  3472. }
  3473. err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
  3474. if (err)
  3475. return err;
  3476. err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
  3477. if (err)
  3478. goto err_col_port_add;
  3479. err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
  3480. if (err)
  3481. goto err_col_port_enable;
  3482. mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
  3483. mlxsw_sp_port->local_port);
  3484. mlxsw_sp_port->lag_id = lag_id;
  3485. mlxsw_sp_port->lagged = 1;
  3486. lag->ref_count++;
  3487. /* Port is no longer usable as a router interface */
  3488. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
  3489. if (mlxsw_sp_port_vlan->fid)
  3490. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
  3491. return 0;
  3492. err_col_port_enable:
  3493. mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
  3494. err_col_port_add:
  3495. if (!lag->ref_count)
  3496. mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
  3497. return err;
  3498. }
  3499. static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
  3500. struct net_device *lag_dev)
  3501. {
  3502. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3503. u16 lag_id = mlxsw_sp_port->lag_id;
  3504. struct mlxsw_sp_upper *lag;
  3505. if (!mlxsw_sp_port->lagged)
  3506. return;
  3507. lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
  3508. WARN_ON(lag->ref_count == 0);
  3509. mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
  3510. mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
  3511. /* Any VLANs configured on the port are no longer valid */
  3512. mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
  3513. if (lag->ref_count == 1)
  3514. mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
  3515. mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
  3516. mlxsw_sp_port->local_port);
  3517. mlxsw_sp_port->lagged = 0;
  3518. lag->ref_count--;
  3519. mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
  3520. /* Make sure untagged frames are allowed to ingress */
  3521. mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
  3522. }
  3523. static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3524. u16 lag_id)
  3525. {
  3526. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3527. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3528. mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
  3529. mlxsw_sp_port->local_port);
  3530. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3531. }
  3532. static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3533. u16 lag_id)
  3534. {
  3535. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3536. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3537. mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
  3538. mlxsw_sp_port->local_port);
  3539. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3540. }
  3541. static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
  3542. bool lag_tx_enabled)
  3543. {
  3544. if (lag_tx_enabled)
  3545. return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
  3546. mlxsw_sp_port->lag_id);
  3547. else
  3548. return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
  3549. mlxsw_sp_port->lag_id);
  3550. }
  3551. static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
  3552. struct netdev_lag_lower_state_info *info)
  3553. {
  3554. return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
  3555. }
  3556. static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
  3557. bool enable)
  3558. {
  3559. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3560. enum mlxsw_reg_spms_state spms_state;
  3561. char *spms_pl;
  3562. u16 vid;
  3563. int err;
  3564. spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
  3565. MLXSW_REG_SPMS_STATE_DISCARDING;
  3566. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  3567. if (!spms_pl)
  3568. return -ENOMEM;
  3569. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  3570. for (vid = 0; vid < VLAN_N_VID; vid++)
  3571. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  3572. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  3573. kfree(spms_pl);
  3574. return err;
  3575. }
  3576. static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
  3577. {
  3578. int err;
  3579. err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
  3580. if (err)
  3581. return err;
  3582. err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
  3583. if (err)
  3584. goto err_port_stp_set;
  3585. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
  3586. true, false);
  3587. if (err)
  3588. goto err_port_vlan_set;
  3589. return 0;
  3590. err_port_vlan_set:
  3591. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  3592. err_port_stp_set:
  3593. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  3594. return err;
  3595. }
  3596. static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
  3597. {
  3598. mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
  3599. false, false);
  3600. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  3601. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  3602. }
  3603. static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
  3604. struct net_device *dev,
  3605. unsigned long event, void *ptr)
  3606. {
  3607. struct netdev_notifier_changeupper_info *info;
  3608. struct mlxsw_sp_port *mlxsw_sp_port;
  3609. struct net_device *upper_dev;
  3610. struct mlxsw_sp *mlxsw_sp;
  3611. int err = 0;
  3612. mlxsw_sp_port = netdev_priv(dev);
  3613. mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3614. info = ptr;
  3615. switch (event) {
  3616. case NETDEV_PRECHANGEUPPER:
  3617. upper_dev = info->upper_dev;
  3618. if (!is_vlan_dev(upper_dev) &&
  3619. !netif_is_lag_master(upper_dev) &&
  3620. !netif_is_bridge_master(upper_dev) &&
  3621. !netif_is_ovs_master(upper_dev))
  3622. return -EINVAL;
  3623. if (!info->linking)
  3624. break;
  3625. if (netdev_has_any_upper_dev(upper_dev))
  3626. return -EINVAL;
  3627. if (netif_is_lag_master(upper_dev) &&
  3628. !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
  3629. info->upper_info))
  3630. return -EINVAL;
  3631. if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
  3632. return -EINVAL;
  3633. if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
  3634. !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
  3635. return -EINVAL;
  3636. if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
  3637. return -EINVAL;
  3638. if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
  3639. return -EINVAL;
  3640. break;
  3641. case NETDEV_CHANGEUPPER:
  3642. upper_dev = info->upper_dev;
  3643. if (netif_is_bridge_master(upper_dev)) {
  3644. if (info->linking)
  3645. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  3646. lower_dev,
  3647. upper_dev);
  3648. else
  3649. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  3650. lower_dev,
  3651. upper_dev);
  3652. } else if (netif_is_lag_master(upper_dev)) {
  3653. if (info->linking)
  3654. err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
  3655. upper_dev);
  3656. else
  3657. mlxsw_sp_port_lag_leave(mlxsw_sp_port,
  3658. upper_dev);
  3659. } else if (netif_is_ovs_master(upper_dev)) {
  3660. if (info->linking)
  3661. err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
  3662. else
  3663. mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
  3664. }
  3665. break;
  3666. }
  3667. return err;
  3668. }
  3669. static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
  3670. unsigned long event, void *ptr)
  3671. {
  3672. struct netdev_notifier_changelowerstate_info *info;
  3673. struct mlxsw_sp_port *mlxsw_sp_port;
  3674. int err;
  3675. mlxsw_sp_port = netdev_priv(dev);
  3676. info = ptr;
  3677. switch (event) {
  3678. case NETDEV_CHANGELOWERSTATE:
  3679. if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
  3680. err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
  3681. info->lower_state_info);
  3682. if (err)
  3683. netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
  3684. }
  3685. break;
  3686. }
  3687. return 0;
  3688. }
  3689. static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
  3690. struct net_device *port_dev,
  3691. unsigned long event, void *ptr)
  3692. {
  3693. switch (event) {
  3694. case NETDEV_PRECHANGEUPPER:
  3695. case NETDEV_CHANGEUPPER:
  3696. return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
  3697. event, ptr);
  3698. case NETDEV_CHANGELOWERSTATE:
  3699. return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
  3700. ptr);
  3701. }
  3702. return 0;
  3703. }
  3704. static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
  3705. unsigned long event, void *ptr)
  3706. {
  3707. struct net_device *dev;
  3708. struct list_head *iter;
  3709. int ret;
  3710. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  3711. if (mlxsw_sp_port_dev_check(dev)) {
  3712. ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
  3713. ptr);
  3714. if (ret)
  3715. return ret;
  3716. }
  3717. }
  3718. return 0;
  3719. }
  3720. static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
  3721. struct net_device *dev,
  3722. unsigned long event, void *ptr,
  3723. u16 vid)
  3724. {
  3725. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  3726. struct netdev_notifier_changeupper_info *info = ptr;
  3727. struct net_device *upper_dev;
  3728. int err = 0;
  3729. switch (event) {
  3730. case NETDEV_PRECHANGEUPPER:
  3731. upper_dev = info->upper_dev;
  3732. if (!netif_is_bridge_master(upper_dev))
  3733. return -EINVAL;
  3734. if (!info->linking)
  3735. break;
  3736. if (netdev_has_any_upper_dev(upper_dev))
  3737. return -EINVAL;
  3738. break;
  3739. case NETDEV_CHANGEUPPER:
  3740. upper_dev = info->upper_dev;
  3741. if (netif_is_bridge_master(upper_dev)) {
  3742. if (info->linking)
  3743. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  3744. vlan_dev,
  3745. upper_dev);
  3746. else
  3747. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  3748. vlan_dev,
  3749. upper_dev);
  3750. } else {
  3751. err = -EINVAL;
  3752. WARN_ON(1);
  3753. }
  3754. break;
  3755. }
  3756. return err;
  3757. }
  3758. static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
  3759. struct net_device *lag_dev,
  3760. unsigned long event,
  3761. void *ptr, u16 vid)
  3762. {
  3763. struct net_device *dev;
  3764. struct list_head *iter;
  3765. int ret;
  3766. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  3767. if (mlxsw_sp_port_dev_check(dev)) {
  3768. ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
  3769. event, ptr,
  3770. vid);
  3771. if (ret)
  3772. return ret;
  3773. }
  3774. }
  3775. return 0;
  3776. }
  3777. static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
  3778. unsigned long event, void *ptr)
  3779. {
  3780. struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
  3781. u16 vid = vlan_dev_vlan_id(vlan_dev);
  3782. if (mlxsw_sp_port_dev_check(real_dev))
  3783. return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
  3784. event, ptr, vid);
  3785. else if (netif_is_lag_master(real_dev))
  3786. return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
  3787. real_dev, event,
  3788. ptr, vid);
  3789. return 0;
  3790. }
  3791. static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
  3792. {
  3793. struct netdev_notifier_changeupper_info *info = ptr;
  3794. if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
  3795. return false;
  3796. return netif_is_l3_master(info->upper_dev);
  3797. }
  3798. static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
  3799. unsigned long event, void *ptr)
  3800. {
  3801. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  3802. int err = 0;
  3803. if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
  3804. err = mlxsw_sp_netdevice_router_port_event(dev);
  3805. else if (mlxsw_sp_is_vrf_event(event, ptr))
  3806. err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
  3807. else if (mlxsw_sp_port_dev_check(dev))
  3808. err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
  3809. else if (netif_is_lag_master(dev))
  3810. err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
  3811. else if (is_vlan_dev(dev))
  3812. err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
  3813. return notifier_from_errno(err);
  3814. }
  3815. static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
  3816. .notifier_call = mlxsw_sp_netdevice_event,
  3817. };
  3818. static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
  3819. .notifier_call = mlxsw_sp_inetaddr_event,
  3820. .priority = 10, /* Must be called before FIB notifier block */
  3821. };
  3822. static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
  3823. .notifier_call = mlxsw_sp_inet6addr_event,
  3824. };
  3825. static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
  3826. .notifier_call = mlxsw_sp_router_netevent_event,
  3827. };
  3828. static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
  3829. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
  3830. {0, },
  3831. };
  3832. static struct pci_driver mlxsw_sp_pci_driver = {
  3833. .name = mlxsw_sp_driver_name,
  3834. .id_table = mlxsw_sp_pci_id_table,
  3835. };
  3836. static int __init mlxsw_sp_module_init(void)
  3837. {
  3838. int err;
  3839. register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
  3840. register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  3841. register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  3842. register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
  3843. err = mlxsw_core_driver_register(&mlxsw_sp_driver);
  3844. if (err)
  3845. goto err_core_driver_register;
  3846. err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
  3847. if (err)
  3848. goto err_pci_driver_register;
  3849. return 0;
  3850. err_pci_driver_register:
  3851. mlxsw_core_driver_unregister(&mlxsw_sp_driver);
  3852. err_core_driver_register:
  3853. unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
  3854. unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  3855. unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  3856. unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
  3857. return err;
  3858. }
  3859. static void __exit mlxsw_sp_module_exit(void)
  3860. {
  3861. mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
  3862. mlxsw_core_driver_unregister(&mlxsw_sp_driver);
  3863. unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
  3864. unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  3865. unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  3866. unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
  3867. }
  3868. module_init(mlxsw_sp_module_init);
  3869. module_exit(mlxsw_sp_module_exit);
  3870. MODULE_LICENSE("Dual BSD/GPL");
  3871. MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
  3872. MODULE_DESCRIPTION("Mellanox Spectrum driver");
  3873. MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
  3874. MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);