am33xx.dtsi 23 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/pinctrl/am33xx.h>
  12. / {
  13. compatible = "ti,am33xx";
  14. interrupt-parent = <&intc>;
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. chosen { };
  18. aliases {
  19. i2c0 = &i2c0;
  20. i2c1 = &i2c1;
  21. i2c2 = &i2c2;
  22. serial0 = &uart0;
  23. serial1 = &uart1;
  24. serial2 = &uart2;
  25. serial3 = &uart3;
  26. serial4 = &uart4;
  27. serial5 = &uart5;
  28. d_can0 = &dcan0;
  29. d_can1 = &dcan1;
  30. usb0 = &usb0;
  31. usb1 = &usb1;
  32. phy0 = &usb0_phy;
  33. phy1 = &usb1_phy;
  34. ethernet0 = &cpsw_emac0;
  35. ethernet1 = &cpsw_emac1;
  36. spi0 = &spi0;
  37. spi1 = &spi1;
  38. };
  39. cpus {
  40. #address-cells = <1>;
  41. #size-cells = <0>;
  42. cpu@0 {
  43. compatible = "arm,cortex-a8";
  44. device_type = "cpu";
  45. reg = <0>;
  46. operating-points-v2 = <&cpu0_opp_table>;
  47. clocks = <&dpll_mpu_ck>;
  48. clock-names = "cpu";
  49. clock-latency = <300000>; /* From omap-cpufreq driver */
  50. };
  51. };
  52. cpu0_opp_table: opp-table {
  53. compatible = "operating-points-v2-ti-cpu";
  54. syscon = <&scm_conf>;
  55. /*
  56. * The three following nodes are marked with opp-suspend
  57. * because the can not be enabled simultaneously on a
  58. * single SoC.
  59. */
  60. opp50-300000000 {
  61. opp-hz = /bits/ 64 <300000000>;
  62. opp-microvolt = <950000 931000 969000>;
  63. opp-supported-hw = <0x06 0x0010>;
  64. opp-suspend;
  65. };
  66. opp100-275000000 {
  67. opp-hz = /bits/ 64 <275000000>;
  68. opp-microvolt = <1100000 1078000 1122000>;
  69. opp-supported-hw = <0x01 0x00FF>;
  70. opp-suspend;
  71. };
  72. opp100-300000000 {
  73. opp-hz = /bits/ 64 <300000000>;
  74. opp-microvolt = <1100000 1078000 1122000>;
  75. opp-supported-hw = <0x06 0x0020>;
  76. opp-suspend;
  77. };
  78. opp100-500000000 {
  79. opp-hz = /bits/ 64 <500000000>;
  80. opp-microvolt = <1100000 1078000 1122000>;
  81. opp-supported-hw = <0x01 0xFFFF>;
  82. };
  83. opp100-600000000 {
  84. opp-hz = /bits/ 64 <600000000>;
  85. opp-microvolt = <1100000 1078000 1122000>;
  86. opp-supported-hw = <0x06 0x0040>;
  87. };
  88. opp120-600000000 {
  89. opp-hz = /bits/ 64 <600000000>;
  90. opp-microvolt = <1200000 1176000 1224000>;
  91. opp-supported-hw = <0x01 0xFFFF>;
  92. };
  93. opp120-720000000 {
  94. opp-hz = /bits/ 64 <720000000>;
  95. opp-microvolt = <1200000 1176000 1224000>;
  96. opp-supported-hw = <0x06 0x0080>;
  97. };
  98. oppturbo-720000000 {
  99. opp-hz = /bits/ 64 <720000000>;
  100. opp-microvolt = <1260000 1234800 1285200>;
  101. opp-supported-hw = <0x01 0xFFFF>;
  102. };
  103. oppturbo-800000000 {
  104. opp-hz = /bits/ 64 <800000000>;
  105. opp-microvolt = <1260000 1234800 1285200>;
  106. opp-supported-hw = <0x06 0x0100>;
  107. };
  108. oppnitro-1000000000 {
  109. opp-hz = /bits/ 64 <1000000000>;
  110. opp-microvolt = <1325000 1298500 1351500>;
  111. opp-supported-hw = <0x04 0x0200>;
  112. };
  113. };
  114. pmu {
  115. compatible = "arm,cortex-a8-pmu";
  116. interrupts = <3>;
  117. };
  118. /*
  119. * The soc node represents the soc top level view. It is used for IPs
  120. * that are not memory mapped in the MPU view or for the MPU itself.
  121. */
  122. soc {
  123. compatible = "ti,omap-infra";
  124. mpu {
  125. compatible = "ti,omap3-mpu";
  126. ti,hwmods = "mpu";
  127. };
  128. };
  129. /*
  130. * XXX: Use a flat representation of the AM33XX interconnect.
  131. * The real AM33XX interconnect network is quite complex. Since
  132. * it will not bring real advantage to represent that in DT
  133. * for the moment, just use a fake OCP bus entry to represent
  134. * the whole bus hierarchy.
  135. */
  136. ocp {
  137. compatible = "simple-bus";
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. ranges;
  141. ti,hwmods = "l3_main";
  142. l4_wkup: l4_wkup@44c00000 {
  143. compatible = "ti,am3-l4-wkup", "simple-bus";
  144. #address-cells = <1>;
  145. #size-cells = <1>;
  146. ranges = <0 0x44c00000 0x280000>;
  147. wkup_m3: wkup_m3@100000 {
  148. compatible = "ti,am3352-wkup-m3";
  149. reg = <0x100000 0x4000>,
  150. <0x180000 0x2000>;
  151. reg-names = "umem", "dmem";
  152. ti,hwmods = "wkup_m3";
  153. ti,pm-firmware = "am335x-pm-firmware.elf";
  154. };
  155. prcm: prcm@200000 {
  156. compatible = "ti,am3-prcm";
  157. reg = <0x200000 0x4000>;
  158. prcm_clocks: clocks {
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. };
  162. prcm_clockdomains: clockdomains {
  163. };
  164. };
  165. scm: scm@210000 {
  166. compatible = "ti,am3-scm", "simple-bus";
  167. reg = <0x210000 0x2000>;
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. #pinctrl-cells = <1>;
  171. ranges = <0 0x210000 0x2000>;
  172. am33xx_pinmux: pinmux@800 {
  173. compatible = "pinctrl-single";
  174. reg = <0x800 0x238>;
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. #pinctrl-cells = <1>;
  178. pinctrl-single,register-width = <32>;
  179. pinctrl-single,function-mask = <0x7f>;
  180. };
  181. scm_conf: scm_conf@0 {
  182. compatible = "syscon", "simple-bus";
  183. reg = <0x0 0x800>;
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. ranges = <0 0 0x800>;
  187. scm_clocks: clocks {
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. };
  191. };
  192. wkup_m3_ipc: wkup_m3_ipc@1324 {
  193. compatible = "ti,am3352-wkup-m3-ipc";
  194. reg = <0x1324 0x24>;
  195. interrupts = <78>;
  196. ti,rproc = <&wkup_m3>;
  197. mboxes = <&mailbox &mbox_wkupm3>;
  198. };
  199. edma_xbar: dma-router@f90 {
  200. compatible = "ti,am335x-edma-crossbar";
  201. reg = <0xf90 0x40>;
  202. #dma-cells = <3>;
  203. dma-requests = <32>;
  204. dma-masters = <&edma>;
  205. };
  206. scm_clockdomains: clockdomains {
  207. };
  208. };
  209. };
  210. intc: interrupt-controller@48200000 {
  211. compatible = "ti,am33xx-intc";
  212. interrupt-controller;
  213. #interrupt-cells = <1>;
  214. reg = <0x48200000 0x1000>;
  215. };
  216. edma: edma@49000000 {
  217. compatible = "ti,edma3-tpcc";
  218. ti,hwmods = "tpcc";
  219. reg = <0x49000000 0x10000>;
  220. reg-names = "edma3_cc";
  221. interrupts = <12 13 14>;
  222. interrupt-names = "edma3_ccint", "edma3_mperr",
  223. "edma3_ccerrint";
  224. dma-requests = <64>;
  225. #dma-cells = <2>;
  226. ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
  227. <&edma_tptc2 0>;
  228. ti,edma-memcpy-channels = <20 21>;
  229. };
  230. edma_tptc0: tptc@49800000 {
  231. compatible = "ti,edma3-tptc";
  232. ti,hwmods = "tptc0";
  233. reg = <0x49800000 0x100000>;
  234. interrupts = <112>;
  235. interrupt-names = "edma3_tcerrint";
  236. };
  237. edma_tptc1: tptc@49900000 {
  238. compatible = "ti,edma3-tptc";
  239. ti,hwmods = "tptc1";
  240. reg = <0x49900000 0x100000>;
  241. interrupts = <113>;
  242. interrupt-names = "edma3_tcerrint";
  243. };
  244. edma_tptc2: tptc@49a00000 {
  245. compatible = "ti,edma3-tptc";
  246. ti,hwmods = "tptc2";
  247. reg = <0x49a00000 0x100000>;
  248. interrupts = <114>;
  249. interrupt-names = "edma3_tcerrint";
  250. };
  251. gpio0: gpio@44e07000 {
  252. compatible = "ti,omap4-gpio";
  253. ti,hwmods = "gpio1";
  254. gpio-controller;
  255. #gpio-cells = <2>;
  256. interrupt-controller;
  257. #interrupt-cells = <2>;
  258. reg = <0x44e07000 0x1000>;
  259. interrupts = <96>;
  260. };
  261. gpio1: gpio@4804c000 {
  262. compatible = "ti,omap4-gpio";
  263. ti,hwmods = "gpio2";
  264. gpio-controller;
  265. #gpio-cells = <2>;
  266. interrupt-controller;
  267. #interrupt-cells = <2>;
  268. reg = <0x4804c000 0x1000>;
  269. interrupts = <98>;
  270. };
  271. gpio2: gpio@481ac000 {
  272. compatible = "ti,omap4-gpio";
  273. ti,hwmods = "gpio3";
  274. gpio-controller;
  275. #gpio-cells = <2>;
  276. interrupt-controller;
  277. #interrupt-cells = <2>;
  278. reg = <0x481ac000 0x1000>;
  279. interrupts = <32>;
  280. };
  281. gpio3: gpio@481ae000 {
  282. compatible = "ti,omap4-gpio";
  283. ti,hwmods = "gpio4";
  284. gpio-controller;
  285. #gpio-cells = <2>;
  286. interrupt-controller;
  287. #interrupt-cells = <2>;
  288. reg = <0x481ae000 0x1000>;
  289. interrupts = <62>;
  290. };
  291. uart0: serial@44e09000 {
  292. compatible = "ti,am3352-uart", "ti,omap3-uart";
  293. ti,hwmods = "uart1";
  294. clock-frequency = <48000000>;
  295. reg = <0x44e09000 0x2000>;
  296. interrupts = <72>;
  297. status = "disabled";
  298. dmas = <&edma 26 0>, <&edma 27 0>;
  299. dma-names = "tx", "rx";
  300. };
  301. uart1: serial@48022000 {
  302. compatible = "ti,am3352-uart", "ti,omap3-uart";
  303. ti,hwmods = "uart2";
  304. clock-frequency = <48000000>;
  305. reg = <0x48022000 0x2000>;
  306. interrupts = <73>;
  307. status = "disabled";
  308. dmas = <&edma 28 0>, <&edma 29 0>;
  309. dma-names = "tx", "rx";
  310. };
  311. uart2: serial@48024000 {
  312. compatible = "ti,am3352-uart", "ti,omap3-uart";
  313. ti,hwmods = "uart3";
  314. clock-frequency = <48000000>;
  315. reg = <0x48024000 0x2000>;
  316. interrupts = <74>;
  317. status = "disabled";
  318. dmas = <&edma 30 0>, <&edma 31 0>;
  319. dma-names = "tx", "rx";
  320. };
  321. uart3: serial@481a6000 {
  322. compatible = "ti,am3352-uart", "ti,omap3-uart";
  323. ti,hwmods = "uart4";
  324. clock-frequency = <48000000>;
  325. reg = <0x481a6000 0x2000>;
  326. interrupts = <44>;
  327. status = "disabled";
  328. };
  329. uart4: serial@481a8000 {
  330. compatible = "ti,am3352-uart", "ti,omap3-uart";
  331. ti,hwmods = "uart5";
  332. clock-frequency = <48000000>;
  333. reg = <0x481a8000 0x2000>;
  334. interrupts = <45>;
  335. status = "disabled";
  336. };
  337. uart5: serial@481aa000 {
  338. compatible = "ti,am3352-uart", "ti,omap3-uart";
  339. ti,hwmods = "uart6";
  340. clock-frequency = <48000000>;
  341. reg = <0x481aa000 0x2000>;
  342. interrupts = <46>;
  343. status = "disabled";
  344. };
  345. i2c0: i2c@44e0b000 {
  346. compatible = "ti,omap4-i2c";
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. ti,hwmods = "i2c1";
  350. reg = <0x44e0b000 0x1000>;
  351. interrupts = <70>;
  352. status = "disabled";
  353. };
  354. i2c1: i2c@4802a000 {
  355. compatible = "ti,omap4-i2c";
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. ti,hwmods = "i2c2";
  359. reg = <0x4802a000 0x1000>;
  360. interrupts = <71>;
  361. status = "disabled";
  362. };
  363. i2c2: i2c@4819c000 {
  364. compatible = "ti,omap4-i2c";
  365. #address-cells = <1>;
  366. #size-cells = <0>;
  367. ti,hwmods = "i2c3";
  368. reg = <0x4819c000 0x1000>;
  369. interrupts = <30>;
  370. status = "disabled";
  371. };
  372. mmc1: mmc@48060000 {
  373. compatible = "ti,omap4-hsmmc";
  374. ti,hwmods = "mmc1";
  375. ti,dual-volt;
  376. ti,needs-special-reset;
  377. ti,needs-special-hs-handling;
  378. dmas = <&edma_xbar 24 0 0
  379. &edma_xbar 25 0 0>;
  380. dma-names = "tx", "rx";
  381. interrupts = <64>;
  382. reg = <0x48060000 0x1000>;
  383. status = "disabled";
  384. };
  385. mmc2: mmc@481d8000 {
  386. compatible = "ti,omap4-hsmmc";
  387. ti,hwmods = "mmc2";
  388. ti,needs-special-reset;
  389. dmas = <&edma 2 0
  390. &edma 3 0>;
  391. dma-names = "tx", "rx";
  392. interrupts = <28>;
  393. reg = <0x481d8000 0x1000>;
  394. status = "disabled";
  395. };
  396. mmc3: mmc@47810000 {
  397. compatible = "ti,omap4-hsmmc";
  398. ti,hwmods = "mmc3";
  399. ti,needs-special-reset;
  400. interrupts = <29>;
  401. reg = <0x47810000 0x1000>;
  402. status = "disabled";
  403. };
  404. hwspinlock: spinlock@480ca000 {
  405. compatible = "ti,omap4-hwspinlock";
  406. reg = <0x480ca000 0x1000>;
  407. ti,hwmods = "spinlock";
  408. #hwlock-cells = <1>;
  409. };
  410. wdt2: wdt@44e35000 {
  411. compatible = "ti,omap3-wdt";
  412. ti,hwmods = "wd_timer2";
  413. reg = <0x44e35000 0x1000>;
  414. interrupts = <91>;
  415. };
  416. dcan0: can@481cc000 {
  417. compatible = "ti,am3352-d_can";
  418. ti,hwmods = "d_can0";
  419. reg = <0x481cc000 0x2000>;
  420. clocks = <&dcan0_fck>;
  421. clock-names = "fck";
  422. syscon-raminit = <&scm_conf 0x644 0>;
  423. interrupts = <52>;
  424. status = "disabled";
  425. };
  426. dcan1: can@481d0000 {
  427. compatible = "ti,am3352-d_can";
  428. ti,hwmods = "d_can1";
  429. reg = <0x481d0000 0x2000>;
  430. clocks = <&dcan1_fck>;
  431. clock-names = "fck";
  432. syscon-raminit = <&scm_conf 0x644 1>;
  433. interrupts = <55>;
  434. status = "disabled";
  435. };
  436. mailbox: mailbox@480C8000 {
  437. compatible = "ti,omap4-mailbox";
  438. reg = <0x480C8000 0x200>;
  439. interrupts = <77>;
  440. ti,hwmods = "mailbox";
  441. #mbox-cells = <1>;
  442. ti,mbox-num-users = <4>;
  443. ti,mbox-num-fifos = <8>;
  444. mbox_wkupm3: wkup_m3 {
  445. ti,mbox-send-noirq;
  446. ti,mbox-tx = <0 0 0>;
  447. ti,mbox-rx = <0 0 3>;
  448. };
  449. };
  450. timer1: timer@44e31000 {
  451. compatible = "ti,am335x-timer-1ms";
  452. reg = <0x44e31000 0x400>;
  453. interrupts = <67>;
  454. ti,hwmods = "timer1";
  455. ti,timer-alwon;
  456. };
  457. timer2: timer@48040000 {
  458. compatible = "ti,am335x-timer";
  459. reg = <0x48040000 0x400>;
  460. interrupts = <68>;
  461. ti,hwmods = "timer2";
  462. };
  463. timer3: timer@48042000 {
  464. compatible = "ti,am335x-timer";
  465. reg = <0x48042000 0x400>;
  466. interrupts = <69>;
  467. ti,hwmods = "timer3";
  468. };
  469. timer4: timer@48044000 {
  470. compatible = "ti,am335x-timer";
  471. reg = <0x48044000 0x400>;
  472. interrupts = <92>;
  473. ti,hwmods = "timer4";
  474. ti,timer-pwm;
  475. };
  476. timer5: timer@48046000 {
  477. compatible = "ti,am335x-timer";
  478. reg = <0x48046000 0x400>;
  479. interrupts = <93>;
  480. ti,hwmods = "timer5";
  481. ti,timer-pwm;
  482. };
  483. timer6: timer@48048000 {
  484. compatible = "ti,am335x-timer";
  485. reg = <0x48048000 0x400>;
  486. interrupts = <94>;
  487. ti,hwmods = "timer6";
  488. ti,timer-pwm;
  489. };
  490. timer7: timer@4804a000 {
  491. compatible = "ti,am335x-timer";
  492. reg = <0x4804a000 0x400>;
  493. interrupts = <95>;
  494. ti,hwmods = "timer7";
  495. ti,timer-pwm;
  496. };
  497. rtc: rtc@44e3e000 {
  498. compatible = "ti,am3352-rtc", "ti,da830-rtc";
  499. reg = <0x44e3e000 0x1000>;
  500. interrupts = <75
  501. 76>;
  502. ti,hwmods = "rtc";
  503. clocks = <&clkdiv32k_ick>;
  504. clock-names = "int-clk";
  505. };
  506. spi0: spi@48030000 {
  507. compatible = "ti,omap4-mcspi";
  508. #address-cells = <1>;
  509. #size-cells = <0>;
  510. reg = <0x48030000 0x400>;
  511. interrupts = <65>;
  512. ti,spi-num-cs = <2>;
  513. ti,hwmods = "spi0";
  514. dmas = <&edma 16 0
  515. &edma 17 0
  516. &edma 18 0
  517. &edma 19 0>;
  518. dma-names = "tx0", "rx0", "tx1", "rx1";
  519. status = "disabled";
  520. };
  521. spi1: spi@481a0000 {
  522. compatible = "ti,omap4-mcspi";
  523. #address-cells = <1>;
  524. #size-cells = <0>;
  525. reg = <0x481a0000 0x400>;
  526. interrupts = <125>;
  527. ti,spi-num-cs = <2>;
  528. ti,hwmods = "spi1";
  529. dmas = <&edma 42 0
  530. &edma 43 0
  531. &edma 44 0
  532. &edma 45 0>;
  533. dma-names = "tx0", "rx0", "tx1", "rx1";
  534. status = "disabled";
  535. };
  536. usb: usb@47400000 {
  537. compatible = "ti,am33xx-usb";
  538. reg = <0x47400000 0x1000>;
  539. ranges;
  540. #address-cells = <1>;
  541. #size-cells = <1>;
  542. ti,hwmods = "usb_otg_hs";
  543. status = "disabled";
  544. usb_ctrl_mod: control@44e10620 {
  545. compatible = "ti,am335x-usb-ctrl-module";
  546. reg = <0x44e10620 0x10
  547. 0x44e10648 0x4>;
  548. reg-names = "phy_ctrl", "wakeup";
  549. status = "disabled";
  550. };
  551. usb0_phy: usb-phy@47401300 {
  552. compatible = "ti,am335x-usb-phy";
  553. reg = <0x47401300 0x100>;
  554. reg-names = "phy";
  555. status = "disabled";
  556. ti,ctrl_mod = <&usb_ctrl_mod>;
  557. };
  558. usb0: usb@47401000 {
  559. compatible = "ti,musb-am33xx";
  560. status = "disabled";
  561. reg = <0x47401400 0x400
  562. 0x47401000 0x200>;
  563. reg-names = "mc", "control";
  564. interrupts = <18>;
  565. interrupt-names = "mc";
  566. dr_mode = "otg";
  567. mentor,multipoint = <1>;
  568. mentor,num-eps = <16>;
  569. mentor,ram-bits = <12>;
  570. mentor,power = <500>;
  571. phys = <&usb0_phy>;
  572. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  573. &cppi41dma 2 0 &cppi41dma 3 0
  574. &cppi41dma 4 0 &cppi41dma 5 0
  575. &cppi41dma 6 0 &cppi41dma 7 0
  576. &cppi41dma 8 0 &cppi41dma 9 0
  577. &cppi41dma 10 0 &cppi41dma 11 0
  578. &cppi41dma 12 0 &cppi41dma 13 0
  579. &cppi41dma 14 0 &cppi41dma 0 1
  580. &cppi41dma 1 1 &cppi41dma 2 1
  581. &cppi41dma 3 1 &cppi41dma 4 1
  582. &cppi41dma 5 1 &cppi41dma 6 1
  583. &cppi41dma 7 1 &cppi41dma 8 1
  584. &cppi41dma 9 1 &cppi41dma 10 1
  585. &cppi41dma 11 1 &cppi41dma 12 1
  586. &cppi41dma 13 1 &cppi41dma 14 1>;
  587. dma-names =
  588. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  589. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  590. "rx14", "rx15",
  591. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  592. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  593. "tx14", "tx15";
  594. };
  595. usb1_phy: usb-phy@47401b00 {
  596. compatible = "ti,am335x-usb-phy";
  597. reg = <0x47401b00 0x100>;
  598. reg-names = "phy";
  599. status = "disabled";
  600. ti,ctrl_mod = <&usb_ctrl_mod>;
  601. };
  602. usb1: usb@47401800 {
  603. compatible = "ti,musb-am33xx";
  604. status = "disabled";
  605. reg = <0x47401c00 0x400
  606. 0x47401800 0x200>;
  607. reg-names = "mc", "control";
  608. interrupts = <19>;
  609. interrupt-names = "mc";
  610. dr_mode = "otg";
  611. mentor,multipoint = <1>;
  612. mentor,num-eps = <16>;
  613. mentor,ram-bits = <12>;
  614. mentor,power = <500>;
  615. phys = <&usb1_phy>;
  616. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  617. &cppi41dma 17 0 &cppi41dma 18 0
  618. &cppi41dma 19 0 &cppi41dma 20 0
  619. &cppi41dma 21 0 &cppi41dma 22 0
  620. &cppi41dma 23 0 &cppi41dma 24 0
  621. &cppi41dma 25 0 &cppi41dma 26 0
  622. &cppi41dma 27 0 &cppi41dma 28 0
  623. &cppi41dma 29 0 &cppi41dma 15 1
  624. &cppi41dma 16 1 &cppi41dma 17 1
  625. &cppi41dma 18 1 &cppi41dma 19 1
  626. &cppi41dma 20 1 &cppi41dma 21 1
  627. &cppi41dma 22 1 &cppi41dma 23 1
  628. &cppi41dma 24 1 &cppi41dma 25 1
  629. &cppi41dma 26 1 &cppi41dma 27 1
  630. &cppi41dma 28 1 &cppi41dma 29 1>;
  631. dma-names =
  632. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  633. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  634. "rx14", "rx15",
  635. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  636. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  637. "tx14", "tx15";
  638. };
  639. cppi41dma: dma-controller@47402000 {
  640. compatible = "ti,am3359-cppi41";
  641. reg = <0x47400000 0x1000
  642. 0x47402000 0x1000
  643. 0x47403000 0x1000
  644. 0x47404000 0x4000>;
  645. reg-names = "glue", "controller", "scheduler", "queuemgr";
  646. interrupts = <17>;
  647. interrupt-names = "glue";
  648. #dma-cells = <2>;
  649. #dma-channels = <30>;
  650. #dma-requests = <256>;
  651. status = "disabled";
  652. };
  653. };
  654. epwmss0: epwmss@48300000 {
  655. compatible = "ti,am33xx-pwmss";
  656. reg = <0x48300000 0x10>;
  657. ti,hwmods = "epwmss0";
  658. #address-cells = <1>;
  659. #size-cells = <1>;
  660. status = "disabled";
  661. ranges = <0x48300100 0x48300100 0x80 /* ECAP */
  662. 0x48300180 0x48300180 0x80 /* EQEP */
  663. 0x48300200 0x48300200 0x80>; /* EHRPWM */
  664. ecap0: ecap@48300100 {
  665. compatible = "ti,am3352-ecap",
  666. "ti,am33xx-ecap";
  667. #pwm-cells = <3>;
  668. reg = <0x48300100 0x80>;
  669. clocks = <&l4ls_gclk>;
  670. clock-names = "fck";
  671. interrupts = <31>;
  672. interrupt-names = "ecap0";
  673. status = "disabled";
  674. };
  675. ehrpwm0: pwm@48300200 {
  676. compatible = "ti,am3352-ehrpwm",
  677. "ti,am33xx-ehrpwm";
  678. #pwm-cells = <3>;
  679. reg = <0x48300200 0x80>;
  680. clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
  681. clock-names = "tbclk", "fck";
  682. status = "disabled";
  683. };
  684. };
  685. epwmss1: epwmss@48302000 {
  686. compatible = "ti,am33xx-pwmss";
  687. reg = <0x48302000 0x10>;
  688. ti,hwmods = "epwmss1";
  689. #address-cells = <1>;
  690. #size-cells = <1>;
  691. status = "disabled";
  692. ranges = <0x48302100 0x48302100 0x80 /* ECAP */
  693. 0x48302180 0x48302180 0x80 /* EQEP */
  694. 0x48302200 0x48302200 0x80>; /* EHRPWM */
  695. ecap1: ecap@48302100 {
  696. compatible = "ti,am3352-ecap",
  697. "ti,am33xx-ecap";
  698. #pwm-cells = <3>;
  699. reg = <0x48302100 0x80>;
  700. clocks = <&l4ls_gclk>;
  701. clock-names = "fck";
  702. interrupts = <47>;
  703. interrupt-names = "ecap1";
  704. status = "disabled";
  705. };
  706. ehrpwm1: pwm@48302200 {
  707. compatible = "ti,am3352-ehrpwm",
  708. "ti,am33xx-ehrpwm";
  709. #pwm-cells = <3>;
  710. reg = <0x48302200 0x80>;
  711. clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
  712. clock-names = "tbclk", "fck";
  713. status = "disabled";
  714. };
  715. };
  716. epwmss2: epwmss@48304000 {
  717. compatible = "ti,am33xx-pwmss";
  718. reg = <0x48304000 0x10>;
  719. ti,hwmods = "epwmss2";
  720. #address-cells = <1>;
  721. #size-cells = <1>;
  722. status = "disabled";
  723. ranges = <0x48304100 0x48304100 0x80 /* ECAP */
  724. 0x48304180 0x48304180 0x80 /* EQEP */
  725. 0x48304200 0x48304200 0x80>; /* EHRPWM */
  726. ecap2: ecap@48304100 {
  727. compatible = "ti,am3352-ecap",
  728. "ti,am33xx-ecap";
  729. #pwm-cells = <3>;
  730. reg = <0x48304100 0x80>;
  731. clocks = <&l4ls_gclk>;
  732. clock-names = "fck";
  733. interrupts = <61>;
  734. interrupt-names = "ecap2";
  735. status = "disabled";
  736. };
  737. ehrpwm2: pwm@48304200 {
  738. compatible = "ti,am3352-ehrpwm",
  739. "ti,am33xx-ehrpwm";
  740. #pwm-cells = <3>;
  741. reg = <0x48304200 0x80>;
  742. clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
  743. clock-names = "tbclk", "fck";
  744. status = "disabled";
  745. };
  746. };
  747. mac: ethernet@4a100000 {
  748. compatible = "ti,am335x-cpsw","ti,cpsw";
  749. ti,hwmods = "cpgmac0";
  750. clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
  751. clock-names = "fck", "cpts";
  752. cpdma_channels = <8>;
  753. ale_entries = <1024>;
  754. bd_ram_size = <0x2000>;
  755. mac_control = <0x20>;
  756. slaves = <2>;
  757. active_slave = <0>;
  758. cpts_clock_mult = <0x80000000>;
  759. cpts_clock_shift = <29>;
  760. reg = <0x4a100000 0x800
  761. 0x4a101200 0x100>;
  762. #address-cells = <1>;
  763. #size-cells = <1>;
  764. /*
  765. * c0_rx_thresh_pend
  766. * c0_rx_pend
  767. * c0_tx_pend
  768. * c0_misc_pend
  769. */
  770. interrupts = <40 41 42 43>;
  771. ranges;
  772. syscon = <&scm_conf>;
  773. status = "disabled";
  774. davinci_mdio: mdio@4a101000 {
  775. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  776. #address-cells = <1>;
  777. #size-cells = <0>;
  778. ti,hwmods = "davinci_mdio";
  779. bus_freq = <1000000>;
  780. reg = <0x4a101000 0x100>;
  781. status = "disabled";
  782. };
  783. cpsw_emac0: slave@4a100200 {
  784. /* Filled in by U-Boot */
  785. mac-address = [ 00 00 00 00 00 00 ];
  786. };
  787. cpsw_emac1: slave@4a100300 {
  788. /* Filled in by U-Boot */
  789. mac-address = [ 00 00 00 00 00 00 ];
  790. };
  791. phy_sel: cpsw-phy-sel@44e10650 {
  792. compatible = "ti,am3352-cpsw-phy-sel";
  793. reg= <0x44e10650 0x4>;
  794. reg-names = "gmii-sel";
  795. };
  796. };
  797. ocmcram: ocmcram@40300000 {
  798. compatible = "mmio-sram";
  799. reg = <0x40300000 0x10000>; /* 64k */
  800. };
  801. elm: elm@48080000 {
  802. compatible = "ti,am3352-elm";
  803. reg = <0x48080000 0x2000>;
  804. interrupts = <4>;
  805. ti,hwmods = "elm";
  806. status = "disabled";
  807. };
  808. lcdc: lcdc@4830e000 {
  809. compatible = "ti,am33xx-tilcdc";
  810. reg = <0x4830e000 0x1000>;
  811. interrupts = <36>;
  812. ti,hwmods = "lcdc";
  813. status = "disabled";
  814. };
  815. tscadc: tscadc@44e0d000 {
  816. compatible = "ti,am3359-tscadc";
  817. reg = <0x44e0d000 0x1000>;
  818. interrupts = <16>;
  819. ti,hwmods = "adc_tsc";
  820. status = "disabled";
  821. dmas = <&edma 53 0>, <&edma 57 0>;
  822. dma-names = "fifo0", "fifo1";
  823. tsc {
  824. compatible = "ti,am3359-tsc";
  825. };
  826. am335x_adc: adc {
  827. #io-channel-cells = <1>;
  828. compatible = "ti,am3359-adc";
  829. };
  830. };
  831. gpmc: gpmc@50000000 {
  832. compatible = "ti,am3352-gpmc";
  833. ti,hwmods = "gpmc";
  834. ti,no-idle-on-init;
  835. reg = <0x50000000 0x2000>;
  836. interrupts = <100>;
  837. dmas = <&edma 52 0>;
  838. dma-names = "rxtx";
  839. gpmc,num-cs = <7>;
  840. gpmc,num-waitpins = <2>;
  841. #address-cells = <2>;
  842. #size-cells = <1>;
  843. interrupt-controller;
  844. #interrupt-cells = <2>;
  845. gpio-controller;
  846. #gpio-cells = <2>;
  847. status = "disabled";
  848. };
  849. sham: sham@53100000 {
  850. compatible = "ti,omap4-sham";
  851. ti,hwmods = "sham";
  852. reg = <0x53100000 0x200>;
  853. interrupts = <109>;
  854. dmas = <&edma 36 0>;
  855. dma-names = "rx";
  856. };
  857. aes: aes@53500000 {
  858. compatible = "ti,omap4-aes";
  859. ti,hwmods = "aes";
  860. reg = <0x53500000 0xa0>;
  861. interrupts = <103>;
  862. dmas = <&edma 6 0>,
  863. <&edma 5 0>;
  864. dma-names = "tx", "rx";
  865. };
  866. mcasp0: mcasp@48038000 {
  867. compatible = "ti,am33xx-mcasp-audio";
  868. ti,hwmods = "mcasp0";
  869. reg = <0x48038000 0x2000>,
  870. <0x46000000 0x400000>;
  871. reg-names = "mpu", "dat";
  872. interrupts = <80>, <81>;
  873. interrupt-names = "tx", "rx";
  874. status = "disabled";
  875. dmas = <&edma 8 2>,
  876. <&edma 9 2>;
  877. dma-names = "tx", "rx";
  878. };
  879. mcasp1: mcasp@4803C000 {
  880. compatible = "ti,am33xx-mcasp-audio";
  881. ti,hwmods = "mcasp1";
  882. reg = <0x4803C000 0x2000>,
  883. <0x46400000 0x400000>;
  884. reg-names = "mpu", "dat";
  885. interrupts = <82>, <83>;
  886. interrupt-names = "tx", "rx";
  887. status = "disabled";
  888. dmas = <&edma 10 2>,
  889. <&edma 11 2>;
  890. dma-names = "tx", "rx";
  891. };
  892. rng: rng@48310000 {
  893. compatible = "ti,omap4-rng";
  894. ti,hwmods = "rng";
  895. reg = <0x48310000 0x2000>;
  896. interrupts = <111>;
  897. };
  898. };
  899. };
  900. /include/ "am33xx-clocks.dtsi"